WO2006053314A2 - Apparatus and method for high-voltage transient blocking using low-voltage elements - Google Patents

Apparatus and method for high-voltage transient blocking using low-voltage elements Download PDF

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Publication number
WO2006053314A2
WO2006053314A2 PCT/US2005/041292 US2005041292W WO2006053314A2 WO 2006053314 A2 WO2006053314 A2 WO 2006053314A2 US 2005041292 W US2005041292 W US 2005041292W WO 2006053314 A2 WO2006053314 A2 WO 2006053314A2
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WIPO (PCT)
Prior art keywords
voltage
depletion mode
channel device
low
field effect
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PCT/US2005/041292
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French (fr)
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WO2006053314A3 (en
Inventor
Richard A. Harris
Francois Hebert
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Fultec Semiconductor, Inc.
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Priority to PCT/US2005/041292 priority Critical patent/WO2006053314A2/en
Publication of WO2006053314A2 publication Critical patent/WO2006053314A2/en
Publication of WO2006053314A3 publication Critical patent/WO2006053314A3/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • This invention relates generally to apparatus and methods that employ a transient blocking unit (TBU) that uses a set of cascaded low-voltage elements to achieve high-voltage capability and thereby improve performance.
  • TBU transient blocking unit
  • Protection circuits are further specialized depending on conditions and application. For example, in the case of protecting batteries or rechargeable elements arging and over-discharging one can refer to utions described in U.S. Pat. Nos. 5,789,900; 6,313,610; 6,331,763; 6,518,731; 6,914,416; 6,948,078; 6,958,591 and U.S. Published Application 2001/00210192. Still other protection circuits, e.g., ones associated with power converters for IC circuits and devices that need to control device parameters and electric parameters simultaneously also use these elements. Examples can be found in U.S. Pat. Nos. 5,929,665; 6,768,623; 6,855,988; 6,861,828.
  • TBUs transient blocking units
  • TBUs transient blocking units
  • the objects and advantages of the invention are addressed by an apparatus for high-voltage transient blocking employing a transient blocking unit (TBU) .
  • TBU transient blocking unit
  • the TBU has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage V p of the p-channel device and a bias voltage V n of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient.
  • At least one of the depletion mode n- channel device and the depletion mode p-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) connected source-to-drain.
  • FETs field effect transistors
  • the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs.
  • the set includes two low-voltage
  • MOSFETs metal-oxide-semiconductors
  • JFETs e FETs also known as JFETs.
  • Other types of FETs can also be used, as will be appreciated by those skilled in the art.
  • the set also has an arrangement for providing a bias to a gate of a first of the two MOSFETs.
  • the arrangement has a resistor R and diode D selected such that a drain-to-source voltage V dsT2 on the second of the two MOSFETs, a diode voltage V dbD across the diode D and a current I R flowing through the resistor R obey the relationship:
  • V dsT2 -V gsT2 + V dbD + I R - R ,
  • V gsT2 is a gate-to-source voltage on the second MOSFET.
  • the diode is preferably an avalanche diode.
  • the two MOSFETs have equal pinch- off voltages.
  • the MOSFETs are stacked. In other words they are implemented in a merged structure with a top MOSFET stacked on a bottom MOSFET.
  • the TBU is interconnected as described above and it employs a set of cascaded low-voltage depletion mode FETs to achieve high- voltage transient blocking.
  • the set is employed as the depletion mode n-channel device and is preferably made up of two low-voltage MOSFETs that have equal pinch-off or switch- off voltages.
  • the low-voltage MOSFETs are preferably stacked on top of each other.
  • a bias is provided to the gate of the first MOSFET with the appropriate arrangement.
  • the arrangement has ind diode D chosen such that the drain-to-source voltage V dsT2 on the second MOSFET, diode voltage V dbD across the diode D and current I R flowing through resistor R obey the relationship:
  • V dsT 2 -V 11T2 + V dbD + I R ' R ,
  • V gsT2 is a gate-to-source voltage on the second MOSFET.
  • Fig. 1 is a diagram illustrating the basic principle of operation of a prior art uni-directional transient blocking unit (TBU) .
  • Fig. 2 is a diagram illustrating the basic principle of operation of a prior art bi-directional TBU.
  • Fig. 3 is a diagram of a high-voltage transient blocking apparatus according to the invention employing a uni-directional TBU.
  • Fig. 4 is a diagram of illustrating a bi-directional TBU employing a set of cascaded MOSFETs according to the invention.
  • Fig. 5 is a diagram of an alternative set of cascaded low-voltage n-channel devices for use in any TBU in accordance with the invention.
  • Fig. 6 is a diagram of still another alternative set of cascaded low-voltage NMOS devices for use in any
  • Fig. 7 illustrates an implementation of a set of two cascaded MOSFETs stacked on top of each other in a merged structure .
  • Fig. 8 illustrates another set of two cascaded FETs stacked on top of each other in a merged structure.
  • TBUs transient blocking units
  • FIG. 1 shows a prior art TBU 10 for protecting a load 12 from voltage and/or current transients of one polarity, i.e., positive voltage spikes or surges. For this reason, TBU 10 is called uni-directional.
  • TBU 10 uses a depletion mode n-channel device 14, typically an n-channel metal- oxide-silicon (NMOS) device implemented as a field effect transistor (FET) .
  • NMOS n-channel metal- oxide-silicon
  • FET field effect transistor
  • TBU 10 also uses a depletion mode p- channel device 16, typically a p-channel junction gate field effect-transistor (PJFET) .
  • PJFET junction gate field effect-transistor
  • PMOS, NJFET devices can also be used as devices 14, 16.
  • both NMOS and PJFET 14, 16 are interconnected to take advantage of their n-channel and p-channel biasing and resistance properties to cause mutual switch off to block the transient.
  • NMOS and PJFET 14, 16 have corresponding n- and p-channels 15, 17 as well as gate G, source S and linals. Resistances R n , R p of NMOS and PJFET 14, hen voltage differences or bias voltages V gsn and V gSp between their gate G and source S terminals are zero. Normally, TBU 10 is unblocked and both NMOS and PJFET 14, 16 act as small resistors that allow a load current Ii oad to pass to load 12.
  • TBU 20 has two n- channel devices 22, 24 and one p-channel device 26. Devices 22, 24, 26 are interconnected between their gate G, source S and drain D terminals as shown. Two current limiters 28, 30 are used to ensure appropriate routing of current between
  • TBU 20 causes mutual switch off of devices 22, 24, 26 in response to a negative or positive spike by employing the principles of controlling resistances by biasing in response to transients as explained above .
  • TBUs that use p-channel devices at inputs, a larger number of n-channel or p-channel devices as well as TBUs that employ high-voltage depletion devices. More detailed information about prior art TBUs and associated applications and methods can be found in published literature including, in particular, PCT/AU94 / 00358 , PCT/AUO4 / 00117 ; PCT/AU03/00175; PCT/AU03/00848 and U.S. Pat. No. 5,742,463 that are herein incorporated by reference.
  • Apparatus 100 uses a uni-directional TBU 102 in which the depletion mode n-channel device is no longer a single enhancement mode n-channel FET, but rather a set 104 of two cascaded low-voltage depletion mode n-channel field effect transistors (FETs) 106, 108 connected source-to-drain.
  • FETs field effect transistors
  • Preferably, low-voltage FETs 106, 108 are MOSFETs.
  • TBU 102 also has a depletion mode p-channel device 110, in the form of a PJFET with a p-channel 112.
  • the interconnections between PJFET 110 and set 104 of cascaded MOSFETs 106, 108 are source-to-source and gate-to-drain to retain the switch- off characteristics of standard TBU.
  • Set 104 has an arrangement 114 for providing a bias to gate G terminal of first MOSFET 106.
  • Arrangement 114 has a resistor R and a diode D selected such that a drain-to-source voltage V dsT2 on second MOSFET 108, a diode voltage V dbD across diode D and a current I R flowing through resistor R obey the relationship:
  • V gsT2 is a gate-to-source voltage on second MOSFET 108.
  • the diode is preferably an avalanche diode.
  • MOSFETs 106, 108 have equal pinch-off or switch-off voltages . This may be most practical when MOSFETs 106, 108 come from the same wafer and thus can be made in higher volume. It should be noted, however, that set 104 can just as well us cascaded MOSFETs 106, 108 that have vastly different pinch-off voltages. Such situation only requires adjustment of the breakdown voltage of avalanche diode D.
  • TBU 102 of apparatus 100 achieves high- voltage transient blocking of positive surges (over-current or over-voltage) . That is because set 104 of low-voltage MOSFETs 106, 108 employed as the depletion mode n-channel device behaves like a high-voltage n-channel device sufficiently well for the purposes of TBU 102.
  • TBU 102 current leakage requirements are not stringent, and thus permit cascaded set 104 of low-voltage MOSFETs 106, 108. That is because despite their considerable current leakage, on the order of milliamps in the off state,
  • 5FETs 106, 108 can block large voltages.
  • a 104 of cascaded MOSFETs 106, 108 operates as an effective single cascade transistor with source terminal S of MOSFET 108 acting as the source of entire set 104 and gate terminal G of MOSFET 108 acting as the gate of entire set 104.
  • a critical condition of operation is that the avalanche voltage of diode D be less than the breakdown voltage of MOSFET 108.
  • MOSFET 108 is controlled by bias voltage V gsT2 applied to its gate terminal G. If, during operation the drain-to-source voltage V dsT2 across second MOSFET 108 rises to a point where diode D begins to conduct through resistor R, then a voltage will be generated across R. This voltage will provide a bias voltage to gate terminal G of first MOSFET 106. This bias voltage will effectively hold the voltage at source terminal S of first MOSFET 106 in accordance with the following relationships :
  • VdsT2 -V g sT2 + V d b D + h - R > a S 1 R ⁇ R ⁇ V poT i ⁇ and V gsT2 ⁇ V poT2 , then V 11572 ⁇ -v poT2 + v dbD + v poTl ,
  • the total breakdown strength of the cascade of set 104 is the breakdown strength of first MOSFET 106 plus V dbD of diode D.
  • set 104 operates as a single 3 terminal device with characteristics equivalent to those of second MOSFET 108 except with improved breakdown voltage. In this manner, the advantage of high-voltage transient blocking operation of TBU 102 is secured with inexpensive, low-voltage MOSFETs 106, 108. This is also because the maximum gate voltage that can now be applied to PJFET 110 is higher.
  • set 104 is easy to make, low-cost and highly integrable, since it is placed on the same die and simply replaces the former single depletion mode n-channel device.
  • TBU 120 has first and second depletion mode n-channel devices 122, 124, as well as a depletion mode p-channel device 126.
  • Devices 122, 124, 126 are interconnected as described above to achieve switch-off to either positive or negative transients.
  • TBU 120 also employs two current limiters 128, 138, here in the form of diodes, to ensure proper current flow.
  • first depletion mode n- channel device 122 is replaced by set 104 of cascaded MOSFETs 106, 108 as indicated by the arrow. It should be noted that set 104 can also be used to replace second depletion mode n- channel device 124 if desired.
  • TBU 120 is analogous to a prior art bi-directional TBU, except that it
  • FIG. 5 is a diagram of an alternative set 130 of two cascaded NMOS devices 132, 134 according to the invention that can be employed in the above uni-directional TBU 102 or bi- directional TBU 120, or still other uni- and bi-directional TBUs requiring low-cost, high-voltage operation.
  • a resistor R2 is used in place of the avalanche diode D in a bias arrangement 136.
  • the pinch-off of the second device 132 is raised to a level just below the breakdown voltage of first device 134.
  • set 130 can be used in any of the above TBUs or still other TBUs to replace one or more depletion mode n-channel devices .
  • Fig. 6 is a diagram of still another alternative set 140, which uses first and second NMOS devices 142, 144 and a bias arrangement 146 that is analogous to bias arrangement 114.
  • set 140 can be used in any TBU.
  • the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs can take advantage of various specific types of FETs. This is true for any of the above embodiments.
  • the set can include low-voltage MOSFETs or junction- gate FETs also known as JFETs or still other of FETs, as will be appreciated by those skilled in the art.
  • MOSFETs 106, 108 of set 104 can be stacked on top of each other in a merged structure 150.
  • First MOSFET 106 is the top MOSFET and it is stacked on second MOSFET 108, which becomes the bottom MOSFET.
  • Stacked device or merged structure 150 is obtained through vertical integration of devices 106, 108.
  • a bottom N-epi layer 152 is the outer high-voltage contact with the n+ connected to the input/output of the TBU.
  • the p-channel of the device is the p-layer between the upper and lower N-epi layers.
  • the source of the outer device or bottom device 108 is a N+ thin buried layer 154 which is also the drain contact of the top (inner part of the cascade) device 106.
  • a top surface 156 is the standard source, channel and gate region of device 106.
  • the channel region of outer device 108 can be formed from lateral trenches 158, 160. Lateral doping of the channel can be obtained by partially filling trenches 158, 160 on each side and applying lateral doping techniques such as, for example, tilted implants or vapor phase doping, or diffusion from solid or gas sources.
  • Top MOSFET 106 can have a low pinch-off voltage (V po ) , by using special depletion implant in its gate oxide.
  • the special implant can be Cs, K, Na or other implants familiar to those skilled in the art.
  • the purpose of implantation is je to the oxide.
  • Other techniques involve using /pe dopants to form a conductive channel in the silicon under the gate oxide, which can be depleted as the gate voltage becomes more and more negative (for an NMOS device) .
  • the N-type dopant can be arsenic, phosphorus or antimony.
  • the gate of bottom MOSFET 108 is connected with deep trenches 158, 160 that may have more than one level, and can be connected at different portions.
  • bias arrangement 114 can be integrated in merged structure 150 by using the available doped junctions. Structure 150 can be made by using multiple epi depositions .
  • Stacked devices 106, 108 can be formed by a multiple growth on an N+ substrate 162.
  • the layers and their associated parameters can chosen as follows : 1) N+ substrate; 2) N- epi 1 for outer high-voltage device thickness and doping dependent on breakdown voltage;
  • N+ source of bottom FET 108 between IxIO 17 to IxIO 19 , 0.2 to 2 ⁇ m thick, N-type arsenic or antimony for low diffusion rate; and 5) N- epi 2 for inner high-voltage device.
  • Top processing is a standard VDMOS process, with a self- inel formed by implanting and diffusion of boron >ly gate is patterned.
  • the channel of the outer (lower) FET 108 can be formed by filling to the trench to the top of the bottom epi . Then, the sidewall is doped to form the N- region on the desired side of the P-type channel epi layer.
  • Fig. 8 illustrates another set of two cascaded FETs 172, 174 stacked on top of each other in a merged structure 170.
  • Merged structure 170 has an integrated Schottky diode formed in the trench region surrounding the vertically arranged FETs 172, 174.
  • Fig. 8 also shows that it is possible to terminate the partial fill of the trenches to have access to some of the layers grown in the epi "stack", as may be useful for integrating the various possible biasing arrangements into the set of cascaded FETs 172, 174.
  • a contact to the drain of the top NMOS can be made using a partial trench fill, sidewall etching and poly deposition to contact the desired layer.

Abstract

An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p­channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.

Description

Apparatus and Method for High-Voltage Transient Blocking using Low-Voltage Elements
FIELD OF THE INVENTION
This invention relates generally to apparatus and methods that employ a transient blocking unit (TBU) that uses a set of cascaded low-voltage elements to achieve high-voltage capability and thereby improve performance.
BACKGROUND ART Many circuits, networks, electrical devices and data handling systems are operated in configurations and environments where external factors can impair their performance, cause failure or even result in permanent damage. Among the most common of these factors are over- voltage and over-current. Protection against these factors is important and has been addressed in the prior art in a number of ways, depending on the specific electronics and their application.
Fuses that employ thermal or magnetic elements are one common protection measure. In other cases, protection circuits are available. Some examples are described in U.S.
Pat. Nos. 5,130,262; 5,625,519; 6,157,529; 6,828,842 and
6,898,060. Protection circuits are further specialized depending on conditions and application. For example, in the case of protecting batteries or rechargeable elements arging and over-discharging one can refer to utions described in U.S. Pat. Nos. 5,789,900; 6,313,610; 6,331,763; 6,518,731; 6,914,416; 6,948,078; 6,958,591 and U.S. Published Application 2001/00210192. Still other protection circuits, e.g., ones associated with power converters for IC circuits and devices that need to control device parameters and electric parameters simultaneously also use these elements. Examples can be found in U.S. Pat. Nos. 5,929,665; 6,768,623; 6,855,988; 6,861,828.
When providing protection for very sensitive circuits, such as those encountered in telecommunications the performance parameters of the fuses and protection circuits are frequently insufficient. A prior art solution embodied by transient blocking units (TBUs) that satisfy a number of the constraints is taught in international publications PCT/AU94/00358; PCT/AU04/00117; PCT/AU03/00175; PCT/AU03/00848 as well as U.S. Pat. Nos. 4,533,970; 5,742,463 and related literature cited in these references.
Unfortunately, when high-voltage operation is required, traditional TBUs are frequently not an option because they require expensive, high-performance parts. Thus, it would be an advance in the art to reduce the expense while preserving or improving the high-voltage performance of TBUs.
OBJECTS AND ADVANTAGES
In view of the above prior art limitations, it is an object of the invention to provide an apparatus and method to permit high-voltage transient blocking using inexpensive elements. In particular, it is an object of the invention to allow the use of inexpensive, low-voltage MOSFETs to build high-voltage transient blocking units (TBUs) .
It is another object of the invention to ensure that the apparatus is easy to make, low-cost and highly integrable, e.g., on the same die.
These and other objects and advantages of the invention will become apparent from the ensuing description.
SUMMARY OF THE INVENTION
The objects and advantages of the invention are addressed by an apparatus for high-voltage transient blocking employing a transient blocking unit (TBU) . The TBU has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. In accordance with the invention, at least one of the depletion mode n- channel device and the depletion mode p-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) connected source-to-drain.
Most commonly, it is the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs. Preferably, the set includes two low-voltage
-silicon field effect transistors (MOSFETs) or e FETs also known as JFETs. Other types of FETs can also be used, as will be appreciated by those skilled in the art.
The set also has an arrangement for providing a bias to a gate of a first of the two MOSFETs. The arrangement has a resistor R and diode D selected such that a drain-to-source voltage VdsT2 on the second of the two MOSFETs, a diode voltage VdbD across the diode D and a current IR flowing through the resistor R obey the relationship:
VdsT2 = -VgsT2 + VdbD + IR - R ,
where VgsT2 is a gate-to-source voltage on the second MOSFET. The diode is preferably an avalanche diode.
It is also preferable that the two MOSFETs have equal pinch- off voltages. In one specific embodiment the MOSFETs are stacked. In other words they are implemented in a merged structure with a top MOSFET stacked on a bottom MOSFET.
In accordance with a method of the invention, the TBU is interconnected as described above and it employs a set of cascaded low-voltage depletion mode FETs to achieve high- voltage transient blocking. The set is employed as the depletion mode n-channel device and is preferably made up of two low-voltage MOSFETs that have equal pinch-off or switch- off voltages. Furthermore, the low-voltage MOSFETs are preferably stacked on top of each other.
A bias is provided to the gate of the first MOSFET with the appropriate arrangement. The arrangement has ind diode D chosen such that the drain-to-source voltage VdsT2 on the second MOSFET, diode voltage VdbD across the diode D and current IR flowing through resistor R obey the relationship:
VdsT2 = -V11T2 + VdbD + IR ' R ,
where VgsT2 is a gate-to-source voltage on the second MOSFET.
A detailed description of the preferred embodiments of the invention is presented below in reference to the appended drawing figures .
BRIEF DESCRIPTION OF THE DRAWING FIGURES Fig. 1 is a diagram illustrating the basic principle of operation of a prior art uni-directional transient blocking unit (TBU) . Fig. 2 is a diagram illustrating the basic principle of operation of a prior art bi-directional TBU. Fig. 3 is a diagram of a high-voltage transient blocking apparatus according to the invention employing a uni-directional TBU.
Fig. 4 is a diagram of illustrating a bi-directional TBU employing a set of cascaded MOSFETs according to the invention.
Fig. 5 is a diagram of an alternative set of cascaded low-voltage n-channel devices for use in any TBU in accordance with the invention.
Fig. 6 is a diagram of still another alternative set of cascaded low-voltage NMOS devices for use in any
TBU in accordance with the invention. Fig. 7 illustrates an implementation of a set of two cascaded MOSFETs stacked on top of each other in a merged structure . Fig. 8 illustrates another set of two cascaded FETs stacked on top of each other in a merged structure.
DETAILED DESCRIPTION The present invention and its principles will be best understood by first reviewing prior art uni-directional and bi-directional transient blocking units (TBUs) designed for over-voltage and over-current protection. The diagram in Fig. 1 shows a prior art TBU 10 for protecting a load 12 from voltage and/or current transients of one polarity, i.e., positive voltage spikes or surges. For this reason, TBU 10 is called uni-directional. TBU 10 uses a depletion mode n-channel device 14, typically an n-channel metal- oxide-silicon (NMOS) device implemented as a field effect transistor (FET) . TBU 10 also uses a depletion mode p- channel device 16, typically a p-channel junction gate field effect-transistor (PJFET) . It should be noted that PMOS, NJFET devices can also be used as devices 14, 16. In the example shown, both NMOS and PJFET 14, 16 are interconnected to take advantage of their n-channel and p-channel biasing and resistance properties to cause mutual switch off to block the transient.
More specifically, NMOS and PJFET 14, 16 have corresponding n- and p-channels 15, 17 as well as gate G, source S and linals. Resistances Rn, Rp of NMOS and PJFET 14, hen voltage differences or bias voltages Vgsn and VgSp between their gate G and source S terminals are zero. Normally, TBU 10 is unblocked and both NMOS and PJFET 14, 16 act as small resistors that allow a load current Iioad to pass to load 12. Application of negative bias Vgsn to NMOS 14 and positive bias Vgsp to PJFET 16 increases resistances Rn, Rp, as indicated by the arrows and turns NMOS and PJFET 14, 16 off. The interconnection of NMOS 14 with PJFET 16 source- to-source and gate-to-drain reinforces the biasing off process in response to excessive current from or associated with a transient. Specifically, as load current Iioad increases PJFET 16 develops a larger voltage drop across it, thus increasing negative bias Vgsn applied to NMOS 14 and consequently increasing resistance Rn. Higher resistance Rn increases positive bias Vgsp on PJFET 16 thereby increasing Rp. Thus, the transient alters bias voltages Vgsn and Vgsp in concert such that NMOS and PJFET 14, 16 mutually increase their resistances Rn, Rp and switch off and thus TBU 10 blocks the transient.
The above principle of interconnection of n- and p-channel devices to achieve mutual switch off (sometimes also referred to as mutual pinch-off) is extended to bi¬ directional TBUs by using two uni-directional TBUs with one configured in reverse to block negative spikes. A simpler, bi-directional TBU 20 that protects load 12 from negative and positive spikes, is shown in Fig. 2. TBU 20 has two n- channel devices 22, 24 and one p-channel device 26. Devices 22, 24, 26 are interconnected between their gate G, source S and drain D terminals as shown. Two current limiters 28, 30 are used to ensure appropriate routing of current between
24, 26. It should be noted that current 30 can be implemented by diodes, transistors, current sources or combinations thereof. TBU 20 causes mutual switch off of devices 22, 24, 26 in response to a negative or positive spike by employing the principles of controlling resistances by biasing in response to transients as explained above .
In fact, the prior art teaches a number of variants of TBUs based on the above principles. These include, among other, TBUs that use p-channel devices at inputs, a larger number of n-channel or p-channel devices as well as TBUs that employ high-voltage depletion devices. More detailed information about prior art TBUs and associated applications and methods can be found in published literature including, in particular, PCT/AU94 / 00358 , PCT/AUO4 / 00117 ; PCT/AU03/00175; PCT/AU03/00848 and U.S. Pat. No. 5,742,463 that are herein incorporated by reference.
In accordance with the invention, high-voltage capability in transient blocking is achieved by an apparatus 100, as shown in Fig. 3. Apparatus 100 uses a uni-directional TBU 102 in which the depletion mode n-channel device is no longer a single enhancement mode n-channel FET, but rather a set 104 of two cascaded low-voltage depletion mode n-channel field effect transistors (FETs) 106, 108 connected source-to-drain. Preferably, low-voltage FETs 106, 108 are MOSFETs. TBU 102 also has a depletion mode p-channel device 110, in the form of a PJFET with a p-channel 112. The interconnections between PJFET 110 and set 104 of cascaded MOSFETs 106, 108 are source-to-source and gate-to-drain to retain the switch- off characteristics of standard TBU. Set 104 has an arrangement 114 for providing a bias to gate G terminal of first MOSFET 106. Arrangement 114 has a resistor R and a diode D selected such that a drain-to-source voltage VdsT2 on second MOSFET 108, a diode voltage VdbD across diode D and a current IR flowing through resistor R obey the relationship:
where VgsT2 is a gate-to-source voltage on second MOSFET 108. The diode is preferably an avalanche diode.
In some embodiments MOSFETs 106, 108 have equal pinch-off or switch-off voltages . This may be most practical when MOSFETs 106, 108 come from the same wafer and thus can be made in higher volume. It should be noted, however, that set 104 can just as well us cascaded MOSFETs 106, 108 that have vastly different pinch-off voltages. Such situation only requires adjustment of the breakdown voltage of avalanche diode D.
During operation, TBU 102 of apparatus 100 achieves high- voltage transient blocking of positive surges (over-current or over-voltage) . That is because set 104 of low-voltage MOSFETs 106, 108 employed as the depletion mode n-channel device behaves like a high-voltage n-channel device sufficiently well for the purposes of TBU 102. In particular, TBU 102 current leakage requirements are not stringent, and thus permit cascaded set 104 of low-voltage MOSFETs 106, 108. That is because despite their considerable current leakage, on the order of milliamps in the off state,
5FETs 106, 108 can block large voltages. As a 104 of cascaded MOSFETs 106, 108 operates as an effective single cascade transistor with source terminal S of MOSFET 108 acting as the source of entire set 104 and gate terminal G of MOSFET 108 acting as the gate of entire set 104. A critical condition of operation is that the avalanche voltage of diode D be less than the breakdown voltage of MOSFET 108.
MOSFET 108 is controlled by bias voltage VgsT2 applied to its gate terminal G. If, during operation the drain-to-source voltage VdsT2 across second MOSFET 108 rises to a point where diode D begins to conduct through resistor R, then a voltage will be generated across R. This voltage will provide a bias voltage to gate terminal G of first MOSFET 106. This bias voltage will effectively hold the voltage at source terminal S of first MOSFET 106 in accordance with the following relationships :
VdsT2 = -VgsT2 + VdbD + h - R > aS 1 R ■ R < VpoTi ϊ and VgsT2 < VpoT2 , then V11572 < -vpoT2 + vdbD + vpoTl ,
where the subscript po denotes pinch-off and subscripts Tl, T2 stand for first and second MOSFETs 106, 108, respectively. Now, if both MOSFETs 106, 108 have the same pinch-off voltage, as is reasonable if both FETs are of the same design, then:
VydsT2
Figure imgf000011_0001
Therefore, as long as VdbD of diode D is selected correctly, sment 114 will ensure that VdsT2 across second MOSFET 108 never exceeds the breakdown voltage of second MOSFET 108. Therefore, the total breakdown strength of the cascade of set 104 is the breakdown strength of first MOSFET 106 plus VdbD of diode D. As such, set 104 operates as a single 3 terminal device with characteristics equivalent to those of second MOSFET 108 except with improved breakdown voltage. In this manner, the advantage of high-voltage transient blocking operation of TBU 102 is secured with inexpensive, low-voltage MOSFETs 106, 108. This is also because the maximum gate voltage that can now be applied to PJFET 110 is higher. In addition, set 104 is easy to make, low-cost and highly integrable, since it is placed on the same die and simply replaces the former single depletion mode n-channel device.
Now, set 104 can also be used in a bi-directional TBU 120, as illustrated in Fig. 4. TBU 120 has first and second depletion mode n-channel devices 122, 124, as well as a depletion mode p-channel device 126. Devices 122, 124, 126 are interconnected as described above to achieve switch-off to either positive or negative transients. TBU 120 also employs two current limiters 128, 138, here in the form of diodes, to ensure proper current flow.
In accordance with the invention, first depletion mode n- channel device 122 is replaced by set 104 of cascaded MOSFETs 106, 108 as indicated by the arrow. It should be noted that set 104 can also be used to replace second depletion mode n- channel device 124 if desired. The operation of TBU 120 is analogous to a prior art bi-directional TBU, except that it
Lgh-voltage capability it did not possess before low-cost, low-voltage MOSFETS 106, 108. Fig. 5 is a diagram of an alternative set 130 of two cascaded NMOS devices 132, 134 according to the invention that can be employed in the above uni-directional TBU 102 or bi- directional TBU 120, or still other uni- and bi-directional TBUs requiring low-cost, high-voltage operation. In contrast to the previous embodiment, a resistor R2 is used in place of the avalanche diode D in a bias arrangement 136. Also, the pinch-off of the second device 132 is raised to a level just below the breakdown voltage of first device 134. In this way the action of the avalanche diode D from the last embodiment, i.e., that of offsetting the gate drive of device 132 to a level that permits it to act only when the breakdown voltage of inner device 134 is approached, can be imitated and a cascade of low voltage devices can be used to make a device which performs as a high voltage device. Of course, set 130 can be used in any of the above TBUs or still other TBUs to replace one or more depletion mode n-channel devices .
Fig. 6 is a diagram of still another alternative set 140, which uses first and second NMOS devices 142, 144 and a bias arrangement 146 that is analogous to bias arrangement 114. As before set 140 can be used in any TBU. It should also be understood, that the depletion mode n-channel device that employs a set of at least two cascaded low-voltage depletion mode FETs can take advantage of various specific types of FETs. This is true for any of the above embodiments. For example, the set can include low-voltage MOSFETs or junction- gate FETs also known as JFETs or still other of FETs, as will be appreciated by those skilled in the art. When implementing any of the above embodiments in practice, it is preferred, for reasons of size and efficiency to integrate sets of cascaded FETs. For example, as shown in Fig. 7, two MOSFETs 106, 108 of set 104 can be stacked on top of each other in a merged structure 150. First MOSFET 106 is the top MOSFET and it is stacked on second MOSFET 108, which becomes the bottom MOSFET.
Stacked device or merged structure 150, as shown in Fig. 7, is obtained through vertical integration of devices 106, 108. A bottom N-epi layer 152 is the outer high-voltage contact with the n+ connected to the input/output of the TBU. The p-channel of the device is the p-layer between the upper and lower N-epi layers. The source of the outer device or bottom device 108 is a N+ thin buried layer 154 which is also the drain contact of the top (inner part of the cascade) device 106. A top surface 156 is the standard source, channel and gate region of device 106.
Note that the channel region of outer device 108 can be formed from lateral trenches 158, 160. Lateral doping of the channel can be obtained by partially filling trenches 158, 160 on each side and applying lateral doping techniques such as, for example, tilted implants or vapor phase doping, or diffusion from solid or gas sources.
Top MOSFET 106 can have a low pinch-off voltage (Vpo) , by using special depletion implant in its gate oxide. The special implant can be Cs, K, Na or other implants familiar to those skilled in the art. The purpose of implantation is je to the oxide. Other techniques involve using /pe dopants to form a conductive channel in the silicon under the gate oxide, which can be depleted as the gate voltage becomes more and more negative (for an NMOS device) .
Bottom MOSFET 108 has a very thick gate oxide, and uses an implanted dopant to form the conductive n-channel (at Vgs=0V) . For example, the N-type dopant can be arsenic, phosphorus or antimony. The gate of bottom MOSFET 108 is connected with deep trenches 158, 160 that may have more than one level, and can be connected at different portions. Advantageously, bias arrangement 114 can be integrated in merged structure 150 by using the available doped junctions. Structure 150 can be made by using multiple epi depositions .
Stacked devices 106, 108 can be formed by a multiple growth on an N+ substrate 162. The layers and their associated parameters can chosen as follows : 1) N+ substrate; 2) N- epi 1 for outer high-voltage device thickness and doping dependent on breakdown voltage;
3) p-channel region (1-5 μm, P-type, IxIO16 to IxIO18 depending on pinch-off, punch-through and other requirements) ; 4) N+ source of bottom FET 108, between IxIO17 to IxIO19, 0.2 to 2 μm thick, N-type arsenic or antimony for low diffusion rate; and 5) N- epi 2 for inner high-voltage device.
Top processing is a standard VDMOS process, with a self- inel formed by implanting and diffusion of boron >ly gate is patterned. The channel of the outer (lower) FET 108 can be formed by filling to the trench to the top of the bottom epi . Then, the sidewall is doped to form the N- region on the desired side of the P-type channel epi layer. One then proceeds by: 1) growing or depositing the thick gate oxide of the outer
(bottom) FET;
2) refilling with poly to protect that region;
3) etching the sidewall of the trench to form the gate of the bottom FET; 4) (optional) etchback of the poly up to the N+ buried layer of the top FET;
5) (optional) etch to remove the sidewall N-type doping;
6) oxidation of the trench sidewall again followed by filling of the trench.
Fig. 8 illustrates another set of two cascaded FETs 172, 174 stacked on top of each other in a merged structure 170. Merged structure 170 has an integrated Schottky diode formed in the trench region surrounding the vertically arranged FETs 172, 174. Fig. 8 also shows that it is possible to terminate the partial fill of the trenches to have access to some of the layers grown in the epi "stack", as may be useful for integrating the various possible biasing arrangements into the set of cascaded FETs 172, 174. For example, a contact to the drain of the top NMOS can be made using a partial trench fill, sidewall etching and poly deposition to contact the desired layer.
Many other embodiments of the apparatus as well as the method are possible, as will be evident to those skilled in
~herefore, the scope of the invention should be e appended claims and their legal equivalents.

Claims

We claim :
1 . An apparatus for transient blocking comprising a transient blocking unit having at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of said depletion mode p-channel device and a bias voltage Vn of said depletion mode n- channel device, whereby said depletion mode p-channel device and said depletion mode n-channel device mutually switch off to block said' transient, and wherein at least one of said at least one depletion mode n-channel device and said at least one depletion mode p-channel device comprises a set of cascaded low-voltage depletion mode field effect transistors connected source-to-drain.
2. The apparatus of claim 1, wherein said depletion mode n-channel device comprises said set.
3. The apparatus of claim 2, wherein said set comprises at least two low-voltage depletion mode devices selected from the group consisting of field effect transistors and junction gate field effect transistors .
4. The apparatus of claim 3, wherein said at least two low-voltage depletion mode devices comprise two low-voltage metal-oxide-silicon field effect transistors .
5. The apparatus of claim 4, wherein said set further comprises a means for providing a bias to a gate of a first of said two metal- oxide-silicon field effect transistors.
6. The apparatus of claim 5, wherein said means comprises a resistor R and a diode D selected such that a drain-to-source voltage VdsT2 on a second of said two metal-oxide-si1icon field effect transistors, a diode voltage VdbD across said diode D and a current IR flowing through said resistor R obey the relationship:
where VgST2 is a gate-to-source voltage on said second transistor.
7. The apparatus of claim 5, wherein said means comprises an avalanche diode.
8. The apparatus of claim 4, wherein said two low-voltage metal-oxide-silicon transistors have equal pinch-off voltages.
9. The apparatus of claim 3, wherein said two low- voltage depletion mode devices are stacked.
10. The apparatus of claim 9, further comprising a merged structure integrating said two low- voltage depletion mode devices and a biasing arrangement.
11. The apparatus of claim 10, wherein said biasing arrangement comprises an element selected from the group consisting of resistors and avalanche diodes .
12. A method for transient blocking comprising: a) providing a transient blocking unit having at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of said depletion mode p-channel device and a bias voltage Vn of said depletion mode n-channel device, whereby said depletion mode p-channel device and said depletion mode n-channel device mutually switch off to block said transient; b) employing a set of cascaded low-voltage depletion mode field effect transistors connected source-to-drain as at least one of said at least one depletion mode n- channel device and said at least one depletion mode p- channel device.
13. The method of claim 12, wherein said set is employed as said at least one depletion mode n-channel device.
14. The method of claim 13, wherein said set comprises two low-voltage depletion mode devices selected from the group consisting of field effect transistors and junction gate field effect transistors .
15. The apparatus of claim 14, further comprising stacking said two low-voltage depletion mode devices .
16. The method of claim 14, further comprising providing a bias to a gate of a first transistor of said two low-voltage depletion mode devices.
17. The method of claim 16, further comprising providing a resistor R and a diode D selected such that a drain-to-source voltage VdsT2 on a second device of said two low- voltage depletion mode devices, a diode voltage VdbD across said diode D and a current IR flowing through said resistor R obey the relationship:
VdsT2 = -VgsT2 + VdbD + IR - R ,
where VgST2 is a gate-to-source voltage on said second low-voltage depletion mode device.
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200849404A (en) * 2007-06-12 2008-12-16 Promos Technologies Inc Method for forming semiconductor device
US7902606B2 (en) * 2008-01-11 2011-03-08 International Business Machines Corporation Double gate depletion mode MOSFET
CN101939890B (en) * 2008-02-11 2014-07-09 柏恩氏股份有限公司 Transient blocking unit using normally-off device to detect current trip threshold
GB2471223B (en) * 2008-04-16 2013-01-23 Bourns Inc Current limiting surge protection device.
US8169763B2 (en) * 2008-06-26 2012-05-01 Bourns, Inc. Transient blocking unit having an enhancement mode device in the primary current path
US9972352B2 (en) * 2009-08-19 2018-05-15 Seagate Technology Llc Antiferromagnetic coupling layers
US8455948B2 (en) 2011-01-07 2013-06-04 Infineon Technologies Austria Ag Transistor arrangement with a first transistor and with a plurality of second transistors
US8569842B2 (en) * 2011-01-07 2013-10-29 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices
US8570697B2 (en) 2011-09-12 2013-10-29 Honeywell International Inc. Appartus and method for protecting signal and communication lines from very high voltage and transient pulses
US8866253B2 (en) 2012-01-31 2014-10-21 Infineon Technologies Dresden Gmbh Semiconductor arrangement with active drift zone
US9088256B2 (en) 2012-08-08 2015-07-21 Analog Devices, Inc. Apparatus and methods for amplifier fault protection
US9178507B2 (en) 2012-11-28 2015-11-03 Analog Devices, Inc. Apparatus and methods for ultrasound transmit switching
US9479162B2 (en) 2012-11-28 2016-10-25 Analog Devices, Inc. Apparatus and methods for ultrasound probes
US9400513B2 (en) 2014-06-30 2016-07-26 Infineon Technologies Austria Ag Cascode circuit
US9871510B1 (en) * 2016-08-24 2018-01-16 Power Integrations, Inc. Clamp for a hybrid switch
US10692854B2 (en) 2017-03-28 2020-06-23 Semtech Corporation Method and device for electrical overstress and electrostatic discharge protection

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916220A (en) * 1974-04-02 1975-10-28 Denes Roveti Current control electronic switch
US4053915A (en) * 1976-03-22 1977-10-11 Motorola, Inc. Temperature compensated constant current source device
US4533970A (en) * 1983-06-27 1985-08-06 Motorola, Inc. Series current limiter
US6157529A (en) * 1984-10-24 2000-12-05 Ahuja; Om Basic surge protector
JPS63208324A (en) 1987-02-24 1988-08-29 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH0353613A (en) 1989-07-21 1991-03-07 Masaya Maruo Overcurrent protection circuit and semiconductor device
EP0435541A3 (en) * 1989-12-26 1991-07-31 Motorola Inc. Semiconductor device having internal current limit overvoltage protection
DE4013731C2 (en) 1990-04-28 1995-07-13 Sel Alcatel Ag Circuit arrangement for limiting the inrush current
DE4022253A1 (en) 1990-07-11 1992-01-16 Krone Ag Current limiting circuit for telecommunication installation - couples source electrodes of two FETs via resistance
GB9100283D0 (en) * 1991-01-07 1991-02-20 Raychem Ltd Overcurrent protection device
PT99196B (en) * 1990-10-12 1999-02-26 Raychem Ltd DEVICE FOR CIRCUIT PROTECTION AND PROTECTION UNIT UNDERSTANDING THEM
US5319515A (en) * 1990-10-12 1994-06-07 Raychem Limited Circuit protection arrangement
US5696659A (en) * 1993-02-10 1997-12-09 Maruo; Masaya Overcurrent protective circuit and semiconductor device
US5742463A (en) * 1993-07-01 1998-04-21 The University Of Queensland Protection device using field effect transistors
CA2166418A1 (en) 1993-07-01 1995-01-12 Richard Allen Harris A protection device using field effect transistors
DE4402461A1 (en) 1994-01-28 1995-08-03 Sel Alcatel Ag Protection circuit for a subscriber line circuit and subscriber line circuit with it
US5789900A (en) * 1994-12-05 1998-08-04 Fuji Photo Film Co., Ltd. Device for protecting a secondary battery from overcharge and overdischarge
BE1010412A3 (en) 1996-07-09 1998-07-07 Philips Electronics Nv Shifting.
US5729418A (en) * 1996-08-29 1998-03-17 Supertex, Inc. High voltage current limiting protection circuit and method therefor
AT405114B (en) 1997-02-12 1999-05-25 Felten & Guilleaume Ag Oester ARROW DISCONNECTOR
CA2232199C (en) * 1997-04-22 2000-02-22 Kabushiki Kaisha Toshiba Power converter with voltage drive switching element
JP3096260B2 (en) * 1997-07-22 2000-10-10 エス・オー・シー株式会社 Resettable overcurrent protection circuit element
US6331763B1 (en) * 1998-04-15 2001-12-18 Tyco Electronics Corporation Devices and methods for protection of rechargeable elements
US6266223B1 (en) 1999-06-30 2001-07-24 Tyco Electronics Corporation Line protector for a communications circuit
US6313610B1 (en) * 1999-08-20 2001-11-06 Texas Instruments Incorporated Battery protection circuit employing active regulation of charge and discharge devices
US6351360B1 (en) * 1999-09-20 2002-02-26 National Semiconductor Corporation Apparatus for selective shutdown of devices of an integrated circuit in response to thermal fault detection
US6861828B2 (en) * 2000-02-08 2005-03-01 The Furukawa Electric Co., Ltd. Apparatus and circuit for power supply, and apparatus for controlling large current load
JP4566392B2 (en) * 2000-11-16 2010-10-20 レノボ シンガポール プライヴェート リミテッド Battery, battery pack, computer apparatus, electric device, and battery temperature control method for determining action level associated with temperature control
US6768623B1 (en) * 2000-11-17 2004-07-27 Texas Instruments Incorporated IC excess current detection scheme
US6714393B2 (en) * 2002-01-07 2004-03-30 Simmonds Precision Products, Inc. Transient suppression apparatus for potentially explosive environments
AUPS045702A0 (en) 2002-02-12 2002-03-07 Fultech Pty Ltd A protection device
US6958591B1 (en) * 2002-05-22 2005-10-25 National Semiconductor Corporation Battery charging safety circuit for simultaneous startup and rapid surge current clamping
AUPS333302A0 (en) 2002-07-02 2002-07-25 Fultec Pty Ltd A protection and indication circuit
US6855988B2 (en) * 2002-07-08 2005-02-15 Viciciv Technology Semiconductor switching devices
AU2002951888A0 (en) 2002-10-08 2002-10-24 Fultec Pty Ltd A protection device for preventing the flow of undersirable transients
US6865063B2 (en) * 2002-11-12 2005-03-08 Semiconductor Components Industries, Llc Integrated inrush current limiter circuit and method
US6898060B2 (en) * 2003-05-27 2005-05-24 Hewlett-Packard Development Company, L.P. Gated diode overvoltage protection
US6970337B2 (en) * 2003-06-24 2005-11-29 Linear X Systems Inc. High-voltage low-distortion input protection current limiter
US6954347B1 (en) * 2003-09-25 2005-10-11 Tii Network Technologies, Inc. Overvoltage and overcurrent protection system
US7283406B2 (en) * 2005-07-11 2007-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage wordline driver with a three stage level shifter

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