WO2006057729A2

WO2006057729A2 - Monolithic multi-level module and method

Info

Publication number: WO2006057729A2
Application number: PCT/US2005/037159
Authority: WO
Inventors: John Gregory
Original assignee: Intraglobal Corporation
Priority date: 2004-11-22
Filing date: 2005-10-18
Publication date: 2006-06-01
Also published as: WO2006057729A3

Abstract

An interposer (1) having a substrate (10) composed of a flat flexible thin sheet of plastic dielectric material having a copper film laminated on one side. The substrate defines a component site in the form of a cavity (20) in the substrate. The copper film defines a plurality of separated interconnects, each having a tab (22) extending into the cavity (20) formed in the substrate. An electrical component (18) having contacts is positioned in the cavity and its contacts are bonded to the tabs. At least a plurality of the separate interconnects extend laterally beyond the substrate to define flanges (14). The substrate is profiled to be easily oriented in a PCB (30). A monolithic multi-level micropackage (110) having a plurality of layers of copper foils (112) laminated on flexible thin substrates (116) processed to embed in at least one layer of an interposer according to the above, the layers being bonded together by a bonding material and compressed to form a monolithic structure. Monolithic structure can have geometry to enable registration in a PCB. The geometry can be cylindrical with protrusions. The top layer (103) can define connecting flanges to connect with leads on the PCB. Heat sinks (60) can be incorporated into the structure.

Description

MONOLITHIC MULTI-LEVEL MODULE AND METHOD

BACKGROUND OF THE INVENTION Field of the Invention This invention relates to an interposer and to a monolithic multi-level module and to a multi-stack module, and to a method of making same, and to a method for attaching, interconnecting and embedding an electrical device in any substrate material commonly used for single level, double level, or multi level printed circuit boards. The invention results in a low profile electronic assembly with enhanced signal propagation

Prior Art

Various techniques have been proposed for packaging microelectronics and electrical devices, but none offer a planarized package. Moreover, the prior art does not reflect the capability for making small and flat micropackages that are multi-level or multi-stack modules offering a low profile electronic assembly with enhanced signal propagation.

SUMMARY OF THE INVENTION The invention concerns a novel attachment or mounting device for semiconductor chips and other components and for electro-mechanical components, such as, resistors, capacitors, transformers, switches and other components. The attachment or mounting devices constitute interconnecting devices or interposers for mounting to a substrate, such as a printed circuit board or like substrate. Provision is made for secure mounting without any danger of mounting improperly. Mounting occurs with the correct orientation as the interconnecting device is provided with appropriate indexing features.

The invention further concerns creating a laminated structure of a plurality of substrates, PCBs, with essentially planar properties, including the ability to locate heat sinks in the structure at appropriate points or locations. Further a manufacturing format is shown, and an assembly cassette.

Another purpose of the present invention is to create a monolithic multi-chip module or a multi-stack module for mounting in or on a printed circuit board and for other uses. In a preferred form the module is composed of a plurality of stacked substrates. The novel module is a stack of individual substrates, which can be stacked because of their planar geometry, and then placed into a monolithic condition or state. This is possible using the substrate and chip mounting technology described in US Patent No. 6956182 issued October 18, 2005 to the same inventor, said patent being incorporated herein by reference in its entirety.

Other and further advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the appended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figs 1 A to 1 E show schematically an interposer for making according to the present invention;

Figs. 2A and 2B show schematically the interposer of Fig. 1 mounted in a PCB;

Figs. 3A to 3F show schematically tools and steps in the making of the interposer of

Fig. 1; Figs. 4 to 4C show schematically a multi-stack module and certain details thereof;

Figs. 5 to 17 show schematically one preferred embodiment of a multi-stack module according to the present invention; and

Figs. 18 to 31 show schematically another preferred embodiment of a multi-stack module according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE

INVENTION

Referring now to the drawings, Figs. 1A to 1E show schematically a novel interposer and method for making and tools for making according to the present invention. The interposer is formed which connects an electrical device (i.e. semiconductor, resistor, capacitor) or an electromechanical device (switch, sensor, connector) to copper circuits which are printed and etched into the surface of the interposer. The attachment of the electrical or electromechanical device is accomplished using the substrate and chip mounting technology described in US Patent No. 6956182 issued October 18, 2005 to the same inventor, said patent being incorporated herein by reference in its entirety. The novel interposer is manufactured in a manner which results in an electrical connection which is 18 microns in thickness and unobstructed by dielectric material. The substrate and chip mounting technology described in US Patent No. 6956182 consists of providing an interconnect for a semiconductor die, for example to a flat, flexible plastic dielectric substrate that could serve as an interposer to connect the die mounted on the first flexible substrate to a second substrate, which could be a printed circuit board (PCB). The mounting of the die to a flexible substrate is achieved by ultrasonically bonding a circuit interconnect to the die by employing a method of embedding the die in a substrate as described in US Patent No. 6956182 issued October 18, 2005, the contents of which are herein incorporated by reference in their entirety. This method consists essentially of providing a flat, flexible, dielectric, plastic substrate laminated with a conductive foil, preferably copper, on opposite sides of the substrate. First, an interconnecting conductive circuit is created on the a first side of the laminated dielectric substrate by selectively removing portions of the conductive foil using known photo-imaging techniques to leave remaining an interconnecting conductive circuit projecting in parts (tabs) into the perimeter of a cavity from which a preselected volume of the dielectric substrate material has been removed, such as by laser ablation. Using photo-imaging techniques, the conductive foil from the second side of the laminated dielectric substrate, if there is one present, is photo-imaged and removed within the perimeter of the preselected volume to expose the dielectric substrate material within the said perimeter prior to the laser ablation. If there is no copper film on the second side, the laser ablation can take place directly. Thus, there are tabs on the first side corresponding to contacts on the die to be mounted in the cavity. As noted, the volume of the dielectric substrate material within said perimeter is removed by laser ablation to create the cavity or void in the dielectric substrate material, and this is done without destroying the parts of the interconnecting conductive circuit projecting into the perimeter of the cavity or void. The electronic component (e.g. semiconductor die) is inserted into the void, from the second side, and preferably, has a thickness not greater than the preselected thickness of the laminated dielectric substrate. The contacts on the die correspond in position to the parts or tabs of said interconnecting conductive circuit that project into the perimeter of the void so that when fully inserted, the contacts on the electronic component registers with and contact said projecting parts or tabs of the interconnecting conductive circuit. Finally, the contacts on the electronic component and the projecting parts or tabs of the interconnecting conductive circuit on the substrate are ultrasonically bonded together.

As shown in Figs. 1A to 1E the interposer 1 consists of a substrate 10 having a copper film that has been photoimaged into a connective circuit 12 including extending foil flanges 14. The substrate 10 is circular in cross section and has protrusions 16, two of one size and a third larger. The die, in this case an integrated silicon semiconductor chip 18 is positioned in the cavity 20 ablated in the substrate 10 and its contacts are bonded to the tabs extending into the cavity, as indicated by reference numeral 22. The cavity is complementary in size and geometry to the chip 18 and has small relief recesses 24 at the corners of the chip 18. Solder dots 19 can be put on the flanges 14. The mounting of the interposer 1 to a PCB is shown in Figs. 2A and 2B. Shown in Fig. 2A an interposer 1 is mounted to a PCB 30. Flanges 14 overlie the PCB and mate with circuit leads 32 on the PCB. The flanges 14 are ultrasonically bonded to the circuit leads 32. As the copper circuitry on the interposer 1 is VT. OZ. copper, the foil flanges 14 are only 18 microns thick. The substrate of the interposer 1 is selected from a suitable plastic material, such as, LCP, Aramid, Kapton and the like. Fig. 2A shows the PCB 30 and the opening 34 into which the interposer is positioned, see detail A. The opening 34 is provided with three recesses 36 corresponding to the three protrusions 16. The body of the interposer is fabricated to produce a circular or similar shape which is unique and provides an asymmetrical contour.

The printed circuit board is prepared for the placement of the interposer by drilling a hole pattern, punching a pattern or routing a pattern which is similar to the body of the interposer, see Figs. 3B showing a drill schedule for the printed circuit board and Fig. 3C which shows the hole pattern, size and location.

The printed circuit material is imaged and etched to produce a copper interconnecting pattern where one of the interposers may be connected or several of the devices may be interconnected using the copper pathways created on the surface of the substrate, see for example Fig. 3A which shows a Gerber footprint with pin locations. Figs. 3D and 3E show the assembly cassette for the interposers which employs a mounting substrate 40 having openings 44 into which the interposers 1 can be placed prior to utilization, the cassette having location or indexing holes 42. Fig. 3F shows a sprocket driven manufacturing format using a 35 mm tape 46 with the appropriate sprocket holes on each side of the tape suitable for use with a pick and place apparatus.

The interposer 1 may be connected to the copper pattern of the mounting substrate (e.g. PCB) by any of several different methods, including hand solder with flux core solder, pattern printed solder paste which is heated to eutectic temperature in an oven, ultrasonically bonded, thermally bonded and resistance welded. The result of the invention is an assembled electronic device with reduced surface topography and enhanced signal propagation.

Shown in Figs. 4 to 4C is an attachment method for a multi-level substrate 50. The attachment method is desirable for enabling the placement of components (interposers) within the layers 52 of multi-level substrates. Embedding interposer devices 1 in multi-level substrates 50 is accomplished by preparing a single layer of a copper interconnecting substrate 52 with complementary placement sites at the locations of the embedded devices 1. Any number of single layers 52 may be produced to accomplish the desired interconnecting scheme of the final product. Each layer is populated with the proper interposer 1 by hand or automatic placement. The individual layers 52 are placed in a conventional alignment apparatus. Between each layer is placed a sheet of pre-impregnated fiberglass, aramid or similar material 54 commonly used to amalgamate individual layers into a single contiguous laminated construction. Each layer 52 is aligned so that the orientation of the interposer 1 on one layer 52 is in proper relationship to the interposer 1 on subsequent layers 52. Through holes 56 can be drilled in the assembled multi-level substrate and plated through with copper or coated with a conductive ink. Likewise blind vias 58 can be formed in the multi-level substrate 50 and plated with copper or coated with conductive ink. Heat sinks 60 made of copper can be located in substrates in proximity to the die of an interposer 1 to remove heat. The laminated construction is placed in a press and heated in such a manner that the single layers with the interleaved pre-impregnated material are fused together. The multi level panel 50 is processed with a conventional printed circuit method of drilling interconnecting plated vias through the laminated panel or by laser ablating blind vias into the surface of the panel. The panel is drilled in a manner where the foil flange feature of the interposer is drilled through along with the interconnecting circuit pattern which was etched in the contiguous layer. In the case of the blind via interconnection, a laser aperture is etched on the top surface of the board and the dielectric material is removed by laser to the layer of the panel which contains the interposer.

The panel is cleaned using a permanganate, plasma or similar method and the metal of the interposer and circuit pattern is found to be protruding into the drilled hole. The panel is plated in a conventional printed circuit board method using electroless deposition of copper and then electrolytic plating of copper to establish the interconnect pattern of the layers and the embedded devices on the interposers. Referring now to Figs. 15 to 17, a monolithic stack 110 is shown consisting of seven copper foils 112 and six dielectric substrates 114. The copper foils 112 are described in detail in the following and they are referred to as layers 01 to 07. The dielectric substrates 114 consist of three dielectric polymer substrates 116 and three pre-preg substrates 118. A pre-preg substrate is a term of art and comprises a woven cloth pre-impregnated with semi-cured epoxy resin. The cloth may be aramid, Fiberglas, or a variety of other known materials with specific properties. As shown in the drawings especially as shown in Fig. 17, the layers 01 to 07 are the foils 112, numbered from bottom to top. The substrates 16 are laminated with foils 112 on both sides, so that layer 02 is the bottom laminate of the lowest dielectric polymer substrate 116 in the stack and layer 03 is the top laminate of the lowest dielectric substrate 116. Similarly, foils 112 (layers 04 and 05) are laminated on opposite sides of the middle dielectric substrate 116, and foils 112 (layers 06 and 07 are laminated on opposite sides of the top dielectric substrate 116. The bottom foil 112 (layer 01) is laminated to the bottom pre-preg substrate 118, which is laminated to the lowest dielectric polymer substrate 16 in the stack. Similarly, two pre preg substrates 18 are interposed between the three dielectric polymer substrates 116 and bonded to them, to complete the stack. Prior to stacking the copper foils 112 are processed as shown in the drawings by photo-imaging and etching in conventional ways using appropriate masks to produce the layer 01 to 07. After the layer 02 to 06 are pattern etched, the laminations are put together in a stack, in the order as shown in Fig.17, and the stack is placed in a laminating press at about 365 degrees F. to cure the semi-cured epoxy resin, which is heated to a liquidous state and amalgamates with the epoxy resin which is at least a main component of the dielectric polymer substrates. When the stack cools, it becomes a single monolithic entity or module.

After converting to a monolithic construction, the module is further processed first by drilling holes 130 through the module, which are then filled with copper using conventional circuit board techniques to plate the holes throughout, and then by pattern etching the top and bottom foils 112 (layers 01 and 07) to establish the contact points of the module and to isolate electrically the holes 130 top and bottom. Next, the entire stack is enclosed or shielded with a plating of copper 120, using electroless and/or electrolytic techniques, except for the top foil 112, layer 07, shown in Fig. 12. During this plating, the top and bottom surfaces are protected by a resist, later removed. The plating 120 serves to connect all the grounds in the stack and act as a protection against EMI (electromagnetic interference). The dimensions of individual layers are shown in Fig. 12. The layers (copper foils 112) are numbered from bottom to top, and thus, layer 01 is the bottom layer. However, when the stack is to be mounted on a printed circuit board, it is inverted and layer 07 is mounted to the PCB using solder techniques, or the technology of US Patent No. 6956182 issued October 18, 2005 to the same inventor, said patent being incorporated herein by reference in its entirety, to connect the contacts 100 with appropriate circuits on the PCB. Layer 01 becomes the top layer, and is connected to the plating of copper 120, except for the insulated copper filled holes 130.

The functions and composition of the layers (copper foils 112), starting with layer 01 are as follows:

Layer 01 , see Figs. 5, is a copper foil 112 laminated to the bottom side of pre- preg substrate 118. Layer 01 is provided with an array of holes 130 that are filled with copper 132 and surrounded with rings of substrate 134. The holes 130 are drilled after the stack has been completed, in the manner as described above. Layer 01 is prepared by removing the copper foil using conventional photo-imaging and etching techniques to create the substrate rings 134 through which the holes 130 are drilled.

Layer 02, see Figs. 6, is copper foil 112 laminated on the bottom of the bottom dielectric polymer substrate 116. Using the techniques of US Patent No.

6956182 issued October 18, 2005 to the same inventor, said patent being incorporated herein by reference in its entirety, as noted above, the substrate 116 has been prepared using a laser for ablation of the substrate 116 to create a void 140 according to the teachings of earlier inventions, as noted above. The copper foil 112 has been photo-imaged and etched to create the void 140 and interconnection circuits 142 on the foil 112. Note that in creating the interconnection circuits 142, tabs 144 are left on the foil 112 and they protrude into the void 140. These tabs correspond in position to register exactly with contacts on a chip 150 to be mounted in the void 140. Holes 130 are present on the foil 112 in registration with holes 130 on the first and subsequent foils 112 and substrates 116 and 118. Some of the interconnecting paths of the interconnecting circuits 142 go to the edge of the foil 112 and underlying substrate 116 see reference number 146 for example, while others are set back from the edge of the foil 112 and of the substrate

116, see reference numeral 48 for example. Fig. 7 shows in side view layer 02 and substrate 116 with the chip 150 set into or embedded in the substrate 116 and with the tabs 144 of the foil 112 bonded to contacts on the chip 150. When mounting the chip 150, the substrate is flipped over to receive the chip 150 and its contacts are thermally bonded or ultrasonically bonded with the tabs 144, which register exactly to the contacts on the chip 150.

Layer 03 is composed of a copper foil 12 that has been laminated onto the opposite side of the same dielectric polymer substrate 116 on which foil 112 of layer 02 has been laminated. The layer 03 is mainly used for power distribution, and contains a void 160 as a relief area for chip 150, some isolated interconnects 162, and partitioned ground planes, indicated by the divided areas 164 and 166, which go to the edge of the foil 112 and substrate 116 for purposes of connecting to the plating 120. The layer 03 has holes 130, as previously noted, and has been photo-imaged and etched to remove portions of the copper foil 112 leaving remaining what is shown in Fig. 8.

Layer 04, shown in Fig. 9, is a copper foil 112 laminated to the bottom side of the middle dielectric polymer substrate 116. As can be seen, the copper foil

112 has been photo-imaged to create circuit connections 17O.The substrate contains the holes 130. The layer is used for circuit distribution or circuit routing. Layer 05, shown in Fig. 11 , is a copper foil 112 laminated on the bottom of the middle dielectric polymer substrate 116. Two voids 180 are created in this layer (and the substrate 116 and layer 06) to receive chips 186. The copper foil 112 has been photo-imaged and etched to create circuit connections 182 and the tabs 184 which project into the voids 180 to register with contacts on the chips 186. Layer 05 also contains the holes 130. Fig. 10 shows a side view of the layer with the chips 186 embedded and bonded to the tabs 184. This is accomplished in the manner described above.

Layer 06, shown in Fig. 12, is a copper foil 112 laminated on the top of the middle dielectric polymer substrate 116, and has partitioned ground planes that extend to the edge of the foil 112 and the substrate 116 to connect with the plating 120. Two voids 180 are created in the foil 112 and serve as relief areas for the chips 186. The copper foil 112 is photo-imaged and etched to create the circuit interconnections 194, and the openings around some of the holes 130 through which can be seen substrate rings 192 of substrate 116.

Layer 07, shown in Fig. 14, is a copper foil 112 laminated on top of the top dielectric polymer substrate 116. The copper foil has been photo-imaged and etched to leave remaining the contact pads 100, which are used to mount the module on a PCB. Layer 07 also has the holes 130, which are filled with copper from top to bottom, and which are insulated from the contacts 100 by substrate 116.

Next is shown and described a monolithic module 204, which is a circular version (cylindrical) of the described monolithic module, and uses flanges 214 to connect to a PCB, not shown. Referring to Figs. 29, 31 and 32, it will be seen that seven layers of copper foil 112 are used in the shown construction with four substrates 116 and three pre-preg layers 118. The profile of the structure is cylindrical, rather than rectangular as shown in the previous embodiment. The profiling is accomplished to provide a registration feature in the form of three protrusions 208 (one being larger) for mating and registering with like recesses in the PCB during mounting like the interposer 1. As the formation of each layer shown in Figs. 18 to 28 and 30 is similar to that shown and described in detail in conjunction with the layer shown in Figs. 5 to 17, a detailed description will be omitted for sake of simplicity except as necessary to point out the differences in construction. A person of skill in the art will easily and readily understand the figures of this construction. The top layer is provided with microflanges 214 in the manner of interposer 1. The layers are assembled and processed in the same manner as described with reference to the previous embodiment, resulting in the construction shown in Fig. 29. Although the invention has been shown and described in specific preferred embodiments, nevertheless changes and modifications are possible without departing from the invention as claimed. Such changes and modifications as are evident to one skilled in the art are deemed to fall within the purview of the invention as claimed.

Claims

WHAT IS CLAIMED IS:

1. 1. An interposer comprising a substrate composed of a flat flexible thin sheet of plastic dielectric material having a copper film laminated on one side; said substrate defining a component site in the form of a cavity in the substrate; said copper film defining a plurality of separated interconnects, each having a tab extending into the cavity formed in the substrate, an electrical component having contacts is positioned in the cavity and its contacts are bonded to the tabs; at least a plurality of the separate interconnects extending laterally beyond the substrate to define flanges; and said substrate being profiled to be easily oriented in a PCB.

2. An interposer according to claim 1 wherein the substrate is cylindrical and has protrusions to position the substrate relative to a machine that can easily pick and place the substrate in the PCB.

3. An assembly cassette comprising a supporting substrate on which has been positioned a plurality of interposers according to claim 1.

4. A tape comprising a supporting substrate on which has been positioned a plurality of interposers according to claim 1.

5. The combination of a PCB with an opening having registration elements and an interposer according to claim 1 mounted in the opening in the PCB with the flanges bonded to leads on the PCB.

6. A monolithic multi-level micropackage comprising a plurality of layers comprised of copper foils laminated on flexible thin substrates processed to embed in at least one layer an interposer according to claim 1 , the layers being bonded together by a bonding material and compressed to form a monolithic structure.

7. A monolithic multi-level micropackage according to claim 6 wherein the monolithic structure has geometry to enable easy registration in a PCB.

8. A monolithic multi-level micropackage according to claim 7 wherein the geometry is cylindrical with protrusions.

9. A monolithic multi-level micropackage according to claim 6 wherein heat sinks are incorporated in the package.

10. A monolithic multi-level micropackage according to claim 6 wherein the top layer defines connecting flanges to connect with leads on the PCB.

11. A method for making an ϊnterposer comprising the steps of: providing a substrate composed of a flat flexible thin sheet of plastic dielectric material having a copper film laminated on one side; processing said substrate to define a component site in the form of a cavity in the substrate; processing said copper film to define a plurality of separated interconnects, each having a tab extending into the cavity formed in the substrate; positioning an electrical component having contacts in the cavity; bonding the contacts of the electrical component to the tabs; extending at least a plurality of the separate interconnects laterally beyond the substrate to define flanges; and profiling said substrate to be easily oriented in a PCB.

12. A method for making a monolithic multi-level micropackage comprising the steps of: providing a plurality of layers comprised of copper foils laminated on flexible thin substrates processed to embed in at least one layer an interposer according to claim 1 , bonding the layers together using a bonding material; and compressing to form a monolithic structure.

13. A method for making a monolithic multi-level micropackage according to claim 12 wherein the monolithic structure has geometry to enable easy registration in a PCB.

14. A method for making a monolithic multi-level micropackage according to claim 13 wherein the geometry is cylindrical with protrusions.

15. A method for making a monolithic multi-level micropackage according to claim 12 wherein the top layer defines connecting flanges to connect with leads on the PCB.

16. A method for making a monolithic multi-level micropackage according to claim 12 wherein heat sinks are incorporated into the micropackage.