WO2006057773A1 - Scalable integrated logic and non-volatile memory - Google Patents
Scalable integrated logic and non-volatile memory Download PDFInfo
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- WO2006057773A1 WO2006057773A1 PCT/US2005/039391 US2005039391W WO2006057773A1 WO 2006057773 A1 WO2006057773 A1 WO 2006057773A1 US 2005039391 W US2005039391 W US 2005039391W WO 2006057773 A1 WO2006057773 A1 WO 2006057773A1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Definitions
- the present invention relates generally to memory and logic devices and in particular the present invention relates to scalable non-volatile memory devices in logic technology environment.
- Memory and logic devices are typically provided as internal, semiconductor, integrated circuits in computers and many other electronic devices including handheld devices such as cellular telephones and personal digital assistants.
- memory includes static random-access memory (SRAM), read only memory (ROM), flash memory, dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM) that are functionally integrated with logic devices such as microprocessors, microcontrollers, digital signal processors, programmable logic devices, wireless communication, and networking.
- SRAM static random-access memory
- ROM read only memory
- DRAM dynamic random access memory
- SDRAM synchronous dynamic random access memory
- a basic building block for a logic cell is a CMOS inverter that consists of a pair of PMOS and NMOS transistors integrated to have common input and output nodes between power supply (V DD ) and ground potentials.
- V DD power supply
- Conventional DRAM cells are comprised of a switching transistor and an integrated storage capacitor tied to the storage node of the transistor.
- Charge storage is enhanced by providing appropriate storage capacity in the form of a stacked capacitor or a trench capacitor in parallel with the depletion capacitance of the floating storage node.
- DRAM cells are volatile and therefore lose data when the power is removed. Additionally, due to leakage, the capacitor must be refreshed periodically to maintain the charge. As computers and other devices mentioned above become smaller and their performance increases, the computer memories have also gone through a corresponding size reduction and performance increase.
- DRAM cells typically comprised of silicon IC technology, has been progressively scaled in feature size from the nearly 2000 nm node technology of prior years to the current 100 nm node technology.
- the gate insulator primarily SiO 2
- the gate insulator has had an effective oxide thickness (EOT) that has been scaled from 50 nm to approximately 5 nm at the present time.
- EOT effective oxide thickness
- leakage through the oxide becomes appreciable thus providing constraints and challenges towards further scalability from the standpoint of power, speed, and circuit reliability. This is especially true for dynamic circuits.
- L ⁇ 200nm transistor design for deep sub-micron channel length (i.e., L ⁇ 200nm) requires critical control of thermal budget to achieve control of short channel effect, performance, and reliability. Integration of embedded DRAM below 100 nm node has been a challenge not only due to capacitor scalability concerns of DRAM cells but also because of the requirement for higher thermal budgets to achieve leakage, yield, and density objectives of the embedded DRAM cells.
- NVM embedded non- volatile memory
- DRAM dynamic random access memory
- conventional floating gate flash memory technology has not been scalable in power supply voltage levels, consumes higher than desired power during programming, and also requires high programming voltages (e.g., 10 - 20V for the 100 nm technology node).
- Embedding such a device requires on-chip generation of the high voltages and routing these voltages in an otherwise scaled low voltage logic technology adds considerable process complexity and cost and compromises functionality.
- the present invention encompasses integration of elements of a scalable, logic transistor with elements of non- volatile memory cells to be formed on a substrate comprising a plurality of doped regions.
- the doped regions act as the source/drain areas for a transistor element.
- a gate oxide insulator is formed over the substrate and substantially between the doped regions to form the NFET element of the logic transistor.
- another gate oxide insulator is formed over the n-well region (not shown) to form the PFET element of the logic transistor between the p+ doped regions formed within the n-well.
- a gate stack is formed over the gate oxide insulator to form the appropriate gate for the logic transistor element.
- the gate stack is comprised of a first metal nitride layer, a doped silicon (p+ or n+) gate layer formed over the first metal nitride layer, and a second metal suicide layer formed over the gate layer to lower the resistance of the gate line.
- an additional high-k insulator layer with embedded metal dots near the gate insulator interface is incorporated between the gate insulator and the gate stack.
- a flash memory cell that is compatible and scalable with the logic transistor is created. Both transistors are formed using a low temperature process integration scheme to ensure high performance.
- Figure 1 shows a cross-sectional view of one embodiment of a logic field effect transistor element in accordance with the structure and method of the present invention.
- Figure 2 shows a cross-sectional view of one embodiment of a flash transistor element in accordance with the structure and method of the present invention.
- Figure 3 shows a cross-sectional view of one embodiment of a single gate NOR flash cell in accordance with the structure and method of the present invention.
- Figure 4 shows a cross-sectional view of one embodiment of a split gate NAND flash cell in accordance with the structure and method of the present invention.
- Figure 5 shows a block diagram of one embodiment of an electronic system of the present invention.
- SOS silicon-on-sapphire
- SOI silicon-on-insulator
- TFT thin film transistor
- doped and undoped semiconductors epitaxial layers of a silicon supported by abase semiconductor structure, as well as other semiconductor structures well known to one skilled in the art.
- wafer or substrate when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions.
- the thermal budget of an integrated circuit includes all of the high temperature steps required for junction formation and activation as well as thin film formation (deposition/oxidation) and annealing to reduce stress and defects.
- the thermal processes used to manufacture integrated circuits help define region, film, and layer interfaces. These processes supply the thermal energy required for oxidation, film formation, dopant activation, and defect control. Thermal budget control is important to device and junction performance since the thermal processes can also drive diffusion and defect annealing.
- the structure and method of the present invention employs low thermal budget integration for both the logic transistors and the non-volatile memory transistors. This process scheme and the materials used for the logic and non- volatile memory transistor architecture provide greater scalability and compatibility in operating voltages.
- Figure 1 illustrates a cross-sectional view of one embodiment of a logic field effect transistor (FET) incorporating the low thermal budget structure and method of the present invention.
- FET logic field effect transistor
- the FET is comprised of a substrate 100 with two doped regions 101 and 103 that act as the source and drain regions.
- the doped regions 101 and 103 are separated from other transistors by shallow trench isolation (STI) 120 and 121.
- Metal-silicide contacts 105 and 107 are formed on the doped regions 101 and 103 respectively.
- the doped regions 101 and 103 are n+ regions doped into a p- type substrate 100 to form an NFET transistor element. These diffusion regions can be formed using n+ doped amorphous silicon, followed by rapid thermal anneal to limit thermal budget and subsequent silicidation. Similarly, for a PFET transistor element (not show), p+ diffusion source/drain regions could be formed over an n-well region.
- the source/drain regions and substrate of the present invention are not limited to any one conductivity type or formation technique.
- a gate oxide insulator 109 for the logic FET is formed over the substrate and substantially between the source/drain regions 101 and 103.
- the gate insulator 109 is comprised of an ultra-thin silicon dioxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON) layer with a relative dielectric constant (K) in the range of 5.0 - 7.5.
- the SiON layer has the added benefit of low leakage for longer charge retention.
- Other possibilities include a combination of one or more monolayers of SiO 2 followed by an ultra-thin layer of high-k laminate such as Pr 2 O 3 or PrSiON. This limits the gate insulation leakage current to the desired level.
- the gate insulator 109 can be formed on the substrate 100 by atomic layer deposition (ALD).
- ALD atomic layer deposition
- An ultra-thin layer (e.g., 1 - 2 nm) of conductive metal nitride 111 is formed over the gate oxide insulator 109.
- This layer 111 can be tantalum nitride (TaN), titanium nitride (TiN) or some other metal nitride material.
- This layer 111 acts as an appropriate passivation layer and diffusion barrier for undesirable impurities and dopants.
- a gate layer 113 is then formed over the passivation layer 111.
- the gate layer 113 can be comprised of a doped polysilicon or metal material.
- the polysilicon 113 is an n+ conductivity material that is formed by using phosphorus doped amorphous silicon followed by RTA anneal and silicidation (e.g., nickel silicidation for both gate and diffusion).
- plasma chemical vapor deposition (CVD) or some other low temperature processing of boro-silicate glass (for boron impurity) and phoso- silicate glass (for phosphorous impurity) might be employed for dopant sources.
- a final RTA anneal step can be employed for dopant activation, interface state density control, leakage control, and film stability for the gate stack.
- a top layer 115 of metal suicide, such as nickel suicide, is formed over the silicon gate 113.
- metal gate processing an appropriate ALD process can be employed. In one embodiment, this processing can include a layer 115 of ALD Tungsten or Nickel combined with tungsten-silicide or nickel-silicide respectively.
- the fixed threshold FET of the present invention is designed to have a threshold V t in the range of 0.3 - 0.4 V.
- V dd IV
- L 0.05 ⁇ m
- W 1.0 ⁇ m
- I 0n and I off are expected to be > 300 ⁇ A/ ⁇ m and ⁇ 1 x 10 "9 A/ ⁇ m respectively.
- the gate leakage current is estimated to be « 1 A/cm 2 at V dd -
- the interface state density is expected to be ⁇ 1 x 10 u /cm 2 .
- Figure 2 illustrates a cross-sectional view of one embodiment of a non- volatile memory device that incorporates the low thermal budget structure and method of the present invention.
- the non- volatile memory device shares many of the same components of the logic FET illustrated in Figure 1.
- a tunnel oxide insulator 209 for the memory transistor is formed over the substrate and substantially between the source/drain regions 201 and 203.
- the tunnel insulator 209 is comprised of an ultra-thin silicon dioxide (SiO 2 ), silicon nitride (SiN) or silicon oxynitride (SiON) layer with a relative dielectric constant (K) in the range of 5.0 - 7.5.
- the SiON layer has the added benefit of longer charge retention.
- Other possibilities include a combination of one or more monolayers of SiO 2 followed by an ultra-thin layer of high-k laminate such as praseodymium oxide (Pr 2 O 3 ) or praseodymium silicon oxynitride (PrSiON). This limits the gate insulation leakage current to the desired level.
- the tunnel insulator 209 can be formed on the substrate 200 by atomic layer deposition (ALD).
- ALD atomic layer deposition
- the tunnel insulator 209 can have a total physical thickness in the range of 2 - 2.5 nm for a power supply voltage of V DD - 1 -OV. This thickness can be appropriately scaled for lower power supply voltage generation. This provides an equivalent oxide thickness (EOT) of 1.0 - 1.5 nm.
- EOT equivalent oxide thickness
- the memory transistor's gate stack 202 is comprised of a lower ultra-thin layer (e.g., 1 - 2 nm) of conductive metal nitride 211.
- This layer 211 can be tantalum nitride (TaN), titanium nitride (TiN) or some other metal nitride material.
- This layer 211 acts as an appropriate passivation layer and diffusion barrier for undesirable impurities and dopants.
- a gate layer 213 is formed over the passivation layer 211.
- the gate layer 213 can be comprised of a doped polysilicon or metal material.
- the polysilicon 213 is an n+ conductivity material that is formed by using phosphorus doped amorphous silicon followed by RTA anneal and silicidation (e.g., nickel silicidation for both gate and diffusion).
- plasma chemical vapor deposition (CVD) or some other low temperature processing of boro-silicate glass (for boron impurity) and phoso- silicate glass (for phosphorous impurity) might be employed for dopant sources.
- a final RTA anneal step can be employed for dopant activation, interface state density control, leakage control, and film stability for the gate stack.
- a top layer 215 of metal suicide, such as nickel suicide, is formed over the silicon gate 213.
- an appropriate ALD process can be employed.
- this processing can include a layer 215 of ALD Tungsten or Nickel combined with tungsten-silicide or nickel-silicide respectively.
- the gates for both the logic FET element and the non- volatile memory element are substantially identical. Alternate embodiments might make slight changes such as material differences.
- the gate stack 202 is formed over a layer 210 comprised of extremely high density metal nano-dots embedded into a high dielectric constant (high-K) insulator material.
- the embedded metal nano-dots are used as a charge retention layer for the non- volatile memory transistor.
- Each metal dot acts as an isolated, one-dimensional, small floating gate. Therefore, even if a charge leakage path exists between one small floating gate and the substrate or the control gate, the remaining nano-dots in the film layer retain the charge.
- the density range of the metal nano-dots in the high-K insulator layer 210 is in the range of 1 x 10 13 to 10 x 10 13 with typical dot sizes in the range of 1 - 3 nm and spaced greater than 3 nm apart in the high-K dielectric material. Alternate embodiments can use different densities, dot sizes, and spacing.
- the metal dot elements can include platinum (Pt), gold (Au), Cobalt (Co), Tungsten (W) or some other metal that provides deep energy electron and hole traps.
- the metal dot layer 210 is deposited by sputtering or evaporation at relatively low temperatures.
- the metal dots are embedded in a high-K dielectric medium 210 that could also be co-sputtered or deposited subsequently by an ALD technique.
- the high-K dielectric film 210 might be comprised of Alumina (Al 2 O 3 ), Hafnium (HfO 2 ), Tantalum Oxide (Ta 2 O 5 ), HfTaO, HfAlO, ZrO 2 , LaSiON, or laminated combinations of the above that are deposited by an ALD technique or sputtering.
- the high-K dielectric medium 210 can further be comprised of Zirconium Oxide (ZrO 2 ), Lanthanum Oxide (La 2 O 3 ), Praseodymium Oxide (Pr 2 O 3 ), and high-K oxynitrides such as HfSiON, PrSiON, and mixed high-K oxides of Al and La, Al and Pr, Al and Zr, and suicides.
- ZrO 2 Zirconium Oxide
- La 2 O 3 Lanthanum Oxide
- Pr 2 O 3 Praseodymium Oxide
- high-K oxynitrides such as HfSiON, PrSiON, and mixed high-K oxides of Al and La, Al and Pr, Al and Zr, and suicides.
- a typical thickness for the dielectric film 210 may range from 5 — 10 nm with an
- the overall EOT for the non- volatile FET gate insulator stack may be of 3.5 — 4 nm for a programming voltage of 2 — 4 Volts to produce a sub-microsecond programming time. Alternate embodiments can use different thickness ranges to provide different programming voltages.
- the device could be read at 0.7V (i.e., V dd - V tf i xed )- The device would exhibit retention of 10 6 seconds and an endurance of 10 14 cycles.
- the programming voltage could be achieved by simple boot strapped circuitry on-chip and could be applied to the control gate for V t ( h i) for electron trapping and to the substrate for V t( i 0W ) for electron detrapping and hole trapping.
- the method to manufacture the above-described transistors of the present invention uses standard silicon gate process technology but also includes multiple ALD steps to provide low temperature processing of highly controllable ultra-thin films.
- These steps could include a high pressure, low temperature forming gas anneal or RTA after the nitride or oxynitride gate insulator processing to reduce interface state density at the Si/insulator interface.
- the low temperature anneal also stabilizes Si-H bonds at the interface.
- the thermal budget for impurity doping and activation is controlled by using doped amorphous silicon or doped glass as impurity sources and RTA as stated earlier.
- an oxide e.g., SiO 2
- SiO 2 oxide hard mask
- the flash memory and logic transistors of the present invention can be used in both NOR architecture (including NROM) and NAND architecture memory arrays.
- the flash memory cells can be used to store data in a non- volatile fashion while the logic FETs can be used for control/access purposes in the memory array and to provide a variety of logic functions.
- each metal nano-dot memory cell of the array matrix is connected by rows to wordlines and their drains are connected to column bitlines.
- the source of each metal nano-dot memory cell is typically connected to a common source line.
- a NAND flash memory device is comprised of an array of metal nano-dot cells arranged in series chains in a string. Each of the metal nano-dot cells are coupled drain to source in each series chain. A word line that spans across multiple series chains is coupled to the control gates of each floating gate cell in a row in order to control their operation. The bitlines are eventually coupled to sense amplifiers that detect the state of each cell.
- Figure 3 illustrates a cross-sectional view of one embodiment of single gate NOR flash memory cells in accordance with the present invention.
- the substrate 300 in the illustrated embodiment, is a p-type silicon with n+ doped areas 301 — 303 that act as the source/drain regions for the cells. Alternate embodiments use different conductivity materials for the substrate/doped areas.
- the doped area that acts as the drain region 301 is coupled to a first bitline 'A' 305 through a metallized contact.
- the doped area that acts as the common source region 302 is also coupled through another metallized contact elsewhere (not shown) in the cross- section.
- the doped region 303 for the neighboring bit is coupled to a second bitline 306 'B' through a metallized contact as shown in Figure 3.
- Figure 4 illustrates a cross-sectional view of one embodiment of split-gate NAND flash memory cells in accordance with the present invention. This figure illustrates only a small portion of a serial string of elements.
- a typical memory string is comprised of 32 bits in a string.
- One bit is comprised of a non- volatile memory element and a logic element together (e.g., 401 and 410) as shown in the illustration.
- Other configurations may be comprised of only a non- volatile element as a single bit in a string.
- Each logic element 410 - 412 in the NAND string comprises multiple functions. One function is to select a particular non- volatile memory element. A second function involves protection from over-erasure for that particular non-volatile memory element.
- the p-type substrate 400 is comprised of n+ doped regions 420 and 421 that act as the source/drain regions.
- the first region 420 is the drain region and the second region 421 is the source region.
- Alternate embodiments can use different conductivity materials for the substrate/doped areas.
- Bitlines 425 and 426 are coupled to the source/drain regions 420 and 421 through metallization contacts.
- the array is comprised of a plurality of control/access transistors 401 - 403 that function to control access to one of a plurality of memory cells 410 - 412.
- the non-volatile memory elements are comprised as discussed previously with the same composition as the logic transistors except for the metal nano-dot layer embedded in the high-K dielectric material.
- Figure 5 illustrates a functional block diagram of a memory device 500 that can incorporate the memory cell structure of the present invention.
- the memory device 500 is coupled to a processor 510.
- the processor 510 may be a microprocessor or some other type of controlling circuitry.
- the memory device 500 and the processor 510 form part of an electronic system 520 that may also be a system on chip application.
- the memory device 500 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
- the memory device includes an array of memory cells 530 that can be comprised of the logic and flash memory cells previously illustrated.
- the memory array 530 is arranged in banks of rows and columns.
- the gates of each row of memory cells are coupled with a wordline while the drain and source connections of the memory cells are coupled to bitlines.
- An address buffer circuit 540 is provided to latch address signals provided on address input connections AO-Ax 542. Address signals are received and decoded by a row decoder 544 and a column decoder 546 to access the memory array 530. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 530. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
- the memory device 500 reads data in the memory array 530 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 550.
- the sense/buffer circuitry in one embodiment, is coupled to read and latch a row of data from the memory array 530.
- Data input and output buffer circuitry 560 is included for bi-directional data communication over a plurality of data connections 562 with the controller 510.
- Write circuitry 555 is provided to write data to the memory array.
- Control circuitry 570 decodes signals provided on control connections 572 from the processor 510. These signals are used to control the operations on the memory array 530, including data read, data write (program), and erase operations.
- the control circuitry 570 may be a state machine, a sequencer, or some other type of controller.
- the embodiments of the present invention provide a low thermal budget (e.g., approximately less than 600°C) integration scheme to manufacture both logic and non-volatile memory transistors with minimum added process complexity.
- transistors can be produced that have a compatible gate stack.
- the transistors are scalable in operating voltages such that special and complex process technology (e.g., well and isolation) as well as circuitry (e.g., charge pump and high voltage decoding) are not required for embedded logic and memory operation in a system on chip application.
Abstract
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Families Citing this family (114)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7235501B2 (en) | 2004-12-13 | 2007-06-26 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
US7560395B2 (en) | 2005-01-05 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposited hafnium tantalum oxide dielectrics |
US7244981B2 (en) * | 2005-02-25 | 2007-07-17 | Micron Technology, Inc. | Scalable high performance non-volatile memory cells using multi-mechanism carrier transport |
JP2006295131A (en) * | 2005-03-17 | 2006-10-26 | Renesas Technology Corp | Semiconductor apparatus and method for manufacturing same |
US7612403B2 (en) * | 2005-05-17 | 2009-11-03 | Micron Technology, Inc. | Low power non-volatile memory and gate stack |
US7173304B2 (en) * | 2005-06-06 | 2007-02-06 | Micron Technology, Inc. | Method of manufacturing devices comprising conductive nano-dots, and devices comprising same |
US7368370B2 (en) * | 2005-06-15 | 2008-05-06 | The University Of Connecticut | Site-specific nanoparticle self-assembly |
WO2007025066A2 (en) * | 2005-08-24 | 2007-03-01 | The Trustees Of Boston College | Apparatus and methods for manipulating light using nanoscale cometal structures |
US7623746B2 (en) * | 2005-08-24 | 2009-11-24 | The Trustees Of Boston College | Nanoscale optical microscope |
EP1917557A4 (en) | 2005-08-24 | 2015-07-22 | Trustees Boston College | Apparatus and methods for solar energy conversion using nanoscale cometal structures |
US7754964B2 (en) * | 2005-08-24 | 2010-07-13 | The Trustees Of Boston College | Apparatus and methods for solar energy conversion using nanocoax structures |
US7649665B2 (en) * | 2005-08-24 | 2010-01-19 | The Trustees Of Boston College | Apparatus and methods for optical switching using nanoscale optics |
US7589880B2 (en) * | 2005-08-24 | 2009-09-15 | The Trustees Of Boston College | Apparatus and methods for manipulating light using nanoscale cometal structures |
US7410910B2 (en) * | 2005-08-31 | 2008-08-12 | Micron Technology, Inc. | Lanthanum aluminum oxynitride dielectric films |
US7629641B2 (en) * | 2005-08-31 | 2009-12-08 | Micron Technology, Inc. | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection |
US7615446B2 (en) * | 2005-10-13 | 2009-11-10 | Samsung Electronics Co., Ltd. | Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof |
KR100790861B1 (en) * | 2005-10-21 | 2008-01-03 | 삼성전자주식회사 | Resistive memory device comprising nanodot and manufacturing method for the same |
US7524727B2 (en) * | 2005-12-30 | 2009-04-28 | Intel Corporation | Gate electrode having a capping layer |
US7700438B2 (en) * | 2006-01-30 | 2010-04-20 | Freescale Semiconductor, Inc. | MOS device with nano-crystal gate structure |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
KR101194839B1 (en) * | 2006-02-28 | 2012-10-25 | 삼성전자주식회사 | Memory device comprising nanocrystals and method for producing the same |
US20070202648A1 (en) * | 2006-02-28 | 2007-08-30 | Samsung Electronics Co. Ltd. | Memory device and method of manufacturing the same |
JP4965878B2 (en) * | 2006-03-24 | 2012-07-04 | 株式会社東芝 | Nonvolatile semiconductor memory device |
KR100740613B1 (en) * | 2006-07-03 | 2007-07-18 | 삼성전자주식회사 | Methods of forming non-volatile memory device |
TWI338914B (en) * | 2006-07-12 | 2011-03-11 | Ind Tech Res Inst | Metallic compound dots dielectric piece and method of fabricating the same |
US7955935B2 (en) * | 2006-08-03 | 2011-06-07 | Micron Technology, Inc. | Non-volatile memory cell devices and methods |
US7560769B2 (en) * | 2006-08-03 | 2009-07-14 | Micron Technology, Inc. | Non-volatile memory cell device and methods |
US7667260B2 (en) | 2006-08-09 | 2010-02-23 | Micron Technology, Inc. | Nanoscale floating gate and methods of formation |
US7432548B2 (en) * | 2006-08-31 | 2008-10-07 | Micron Technology, Inc. | Silicon lanthanide oxynitride films |
US7605030B2 (en) | 2006-08-31 | 2009-10-20 | Micron Technology, Inc. | Hafnium tantalum oxynitride high-k dielectric and metal gates |
US7759747B2 (en) | 2006-08-31 | 2010-07-20 | Micron Technology, Inc. | Tantalum aluminum oxynitride high-κ dielectric |
US7776765B2 (en) | 2006-08-31 | 2010-08-17 | Micron Technology, Inc. | Tantalum silicon oxynitride high-k dielectrics and metal gates |
US7544604B2 (en) | 2006-08-31 | 2009-06-09 | Micron Technology, Inc. | Tantalum lanthanide oxynitride films |
US7563730B2 (en) | 2006-08-31 | 2009-07-21 | Micron Technology, Inc. | Hafnium lanthanide oxynitride films |
KR100759845B1 (en) * | 2006-09-11 | 2007-09-18 | 삼성전자주식회사 | Non-volatile memory device and method of manufacturing the same |
US20100090265A1 (en) * | 2006-10-19 | 2010-04-15 | Micron Technology, Inc. | High density nanodot nonvolatile memory |
KR100836426B1 (en) * | 2006-11-24 | 2008-06-09 | 삼성에스디아이 주식회사 | Non-Volatile Memory Device and fabrication method thereof and apparatus of memory including thereof |
JP4825697B2 (en) * | 2007-01-25 | 2011-11-30 | 株式会社ミツトヨ | Digital displacement measuring instrument |
CN101627479B (en) * | 2007-01-30 | 2011-06-15 | 索拉斯特公司 | Photovoltaic cell and method of making thereof |
JP2010518623A (en) * | 2007-02-12 | 2010-05-27 | ソーラスタ インコーポレイテッド | Photocell with reduced hot carrier cooling |
US8687418B1 (en) * | 2007-02-12 | 2014-04-01 | Avalanche Technology, Inc. | Flash memory with nano-pillar charge trap |
US7842977B2 (en) * | 2007-02-15 | 2010-11-30 | Qimonda Ag | Gate electrode structure, MOS field effect transistors and methods of manufacturing the same |
US7790560B2 (en) * | 2007-03-12 | 2010-09-07 | Board Of Regents Of The Nevada System Of Higher Education | Construction of flash memory chips and circuits from ordered nanoparticles |
US20080237694A1 (en) * | 2007-03-27 | 2008-10-02 | Michael Specht | Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module |
US7833914B2 (en) * | 2007-04-27 | 2010-11-16 | Micron Technology, Inc. | Capacitors and methods with praseodymium oxide insulators |
KR101341571B1 (en) * | 2007-04-30 | 2013-12-16 | 삼성전자주식회사 | Non-volatile memory device and method of manufacturing the same |
US8097912B2 (en) * | 2007-06-13 | 2012-01-17 | Macronix International Co. Ltd. | Systems and methods for self convergence during erase of a non-volatile memory device |
KR20100039371A (en) * | 2007-07-03 | 2010-04-15 | 솔라스타, 인코포레이티드 | Distributed coax photovoltaic device |
KR20090005648A (en) * | 2007-07-09 | 2009-01-14 | 삼성전자주식회사 | Flash memory devices and methods of fabricating the same |
KR101338158B1 (en) * | 2007-07-16 | 2013-12-06 | 삼성전자주식회사 | Non-volatile memory devices and methods of forming the same |
US7898850B2 (en) * | 2007-10-12 | 2011-03-01 | Micron Technology, Inc. | Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells |
US7759715B2 (en) * | 2007-10-15 | 2010-07-20 | Micron Technology, Inc. | Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle |
US20090166757A1 (en) * | 2007-12-27 | 2009-07-02 | International Business Machines Corporation | Stress engineering for sram stability |
JP4366449B2 (en) * | 2008-02-19 | 2009-11-18 | パナソニック株式会社 | Resistance variable nonvolatile memory element and method of manufacturing the same |
US7704884B2 (en) | 2008-04-11 | 2010-04-27 | Micron Technology, Inc. | Semiconductor processing methods |
US8122421B2 (en) * | 2008-08-14 | 2012-02-21 | Omnivision Technologies, Inc. | System, and method, and computer readable medium for designing a scalable clustered storage integrated circuit for multi-media processing |
US20100075499A1 (en) * | 2008-09-19 | 2010-03-25 | Olsen Christopher S | Method and apparatus for metal silicide formation |
US8399310B2 (en) | 2010-10-29 | 2013-03-19 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
US8389365B2 (en) | 2011-03-31 | 2013-03-05 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
US8564044B2 (en) | 2011-03-31 | 2013-10-22 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
US8481414B2 (en) | 2011-04-08 | 2013-07-09 | Micron Technology, Inc. | Incorporating impurities using a discontinuous mask |
US20120276730A1 (en) * | 2011-04-27 | 2012-11-01 | Nanya Technology Corporation | Methods for fabricating a gate dielectric layer and for fabricating a gate structure |
CN102800632B (en) * | 2011-05-25 | 2014-07-23 | 中国科学院微电子研究所 | Manufacturing method of charge trapping non-volatile memory |
US8883592B2 (en) * | 2011-08-05 | 2014-11-11 | Silicon Storage Technology, Inc. | Non-volatile memory cell having a high K dielectric and metal gate |
CN102592981A (en) * | 2011-11-17 | 2012-07-18 | 中山大学 | Self-assembly preparation method for floating gate layer of silicon nitride dielectric film with embedded metal tungsten quantum dots |
CN102509701A (en) * | 2011-11-17 | 2012-06-20 | 中山大学 | Method for self-assembly preparing insulating medium film embedded with metal quantum dots |
US8536006B2 (en) | 2011-11-30 | 2013-09-17 | Freescale Semiconductor, Inc. | Logic and non-volatile memory (NVM) integration |
US8669158B2 (en) | 2012-01-04 | 2014-03-11 | Mark D. Hall | Non-volatile memory (NVM) and logic integration |
US8658497B2 (en) | 2012-01-04 | 2014-02-25 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8906764B2 (en) | 2012-01-04 | 2014-12-09 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8536007B2 (en) * | 2012-02-22 | 2013-09-17 | Freescale Semiconductor, Inc. | Non-volatile memory cell and logic transistor integration |
JP2013197269A (en) * | 2012-03-19 | 2013-09-30 | Toshiba Corp | Nonvolatile semiconductor storage device |
US8586436B2 (en) | 2012-03-20 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device |
US8951863B2 (en) | 2012-04-06 | 2015-02-10 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8722493B2 (en) | 2012-04-09 | 2014-05-13 | Freescale Semiconductor, Inc. | Logic transistor and non-volatile memory cell integration |
US9087913B2 (en) | 2012-04-09 | 2015-07-21 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
US8574987B1 (en) | 2012-06-08 | 2013-11-05 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric |
US8728886B2 (en) | 2012-06-08 | 2014-05-20 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric |
US20130328135A1 (en) * | 2012-06-12 | 2013-12-12 | International Business Machines Corporation | Preventing fully silicided formation in high-k metal gate processing |
US9111865B2 (en) | 2012-10-26 | 2015-08-18 | Freescale Semiconductor, Inc. | Method of making a logic transistor and a non-volatile memory (NVM) cell |
US8716089B1 (en) | 2013-03-08 | 2014-05-06 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage |
US8741719B1 (en) | 2013-03-08 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique |
US9006093B2 (en) | 2013-06-27 | 2015-04-14 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high voltage transistor integration |
US9129996B2 (en) | 2013-07-31 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
US8877585B1 (en) | 2013-08-16 | 2014-11-04 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration |
US8871598B1 (en) | 2013-07-31 | 2014-10-28 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
US9082837B2 (en) | 2013-08-08 | 2015-07-14 | Freescale Semiconductor, Inc. | Nonvolatile memory bitcell with inlaid high k metal select gate |
US9082650B2 (en) | 2013-08-21 | 2015-07-14 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic structure |
US9252246B2 (en) | 2013-08-21 | 2016-02-02 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic device |
US9275864B2 (en) | 2013-08-22 | 2016-03-01 | Freescale Semiconductor,Inc. | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates |
US8932925B1 (en) | 2013-08-22 | 2015-01-13 | Freescale Semiconductor, Inc. | Split-gate non-volatile memory (NVM) cell and device structure integration |
US9129855B2 (en) | 2013-09-30 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
US8901632B1 (en) | 2013-09-30 | 2014-12-02 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
US9136129B2 (en) | 2013-09-30 | 2015-09-15 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology |
US9231077B2 (en) | 2014-03-03 | 2016-01-05 | Freescale Semiconductor, Inc. | Method of making a logic transistor and non-volatile memory (NVM) cell |
US9112056B1 (en) | 2014-03-28 | 2015-08-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9472418B2 (en) | 2014-03-28 | 2016-10-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9252152B2 (en) | 2014-03-28 | 2016-02-02 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9379222B2 (en) | 2014-05-30 | 2016-06-28 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell |
US9257445B2 (en) | 2014-05-30 | 2016-02-09 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
US9343314B2 (en) | 2014-05-30 | 2016-05-17 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
KR102592325B1 (en) * | 2016-07-14 | 2023-10-20 | 삼성전자주식회사 | Aluminum compound and methods of forming thin film and integrated circuit device |
US10374101B2 (en) | 2017-07-05 | 2019-08-06 | Micron Technology, Inc. | Memory arrays |
US10176870B1 (en) | 2017-07-05 | 2019-01-08 | Micron Technology, Inc. | Multifunctional memory cells |
US10153381B1 (en) | 2017-07-05 | 2018-12-11 | Micron Technology, Inc. | Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate |
US10297493B2 (en) | 2017-07-05 | 2019-05-21 | Micron Technology, Inc. | Trench isolation interfaces |
US20190013387A1 (en) | 2017-07-05 | 2019-01-10 | Micron Technology, Inc. | Memory cell structures |
US10153348B1 (en) | 2017-07-05 | 2018-12-11 | Micron Technology, Inc. | Memory configurations |
US10411026B2 (en) | 2017-07-05 | 2019-09-10 | Micron Technology, Inc. | Integrated computing structures formed on silicon |
US10153039B1 (en) | 2017-07-05 | 2018-12-11 | Micron Technology, Inc. | Memory cells programmed via multi-mechanism charge transports |
US10276576B2 (en) | 2017-07-05 | 2019-04-30 | Micron Technology, Inc. | Gated diode memory cells |
US10262736B2 (en) | 2017-07-05 | 2019-04-16 | Micron Technology, Inc. | Multifunctional memory cells |
US11195089B2 (en) | 2018-06-28 | 2021-12-07 | International Business Machines Corporation | Multi-terminal cross-point synaptic device using nanocrystal dot structures |
CN111477625B (en) * | 2020-04-27 | 2023-02-07 | 复旦大学 | Semi-floating gate memory based on defect trapping material and preparation method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5783478A (en) * | 1992-12-11 | 1998-07-21 | Intel Corporation | Method of frabricating a MOS transistor having a composite gate electrode |
US6417085B1 (en) * | 1999-07-02 | 2002-07-09 | Micron Technology, Inc. | Methods of forming a field effect transistor gate construction |
US20020109142A1 (en) * | 1999-12-30 | 2002-08-15 | Joo Kwang Chul | Non-volatile memory device and manufacturing method thereof |
US20040178470A1 (en) * | 2003-03-14 | 2004-09-16 | Katsuhiko Hieda | Semiconductor memory device and method of manufacturing the same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328859A (en) * | 1993-01-04 | 1994-07-12 | Xerox Corporation | Method of making high voltage PNP bipolar transistor in CMOS |
US6020024A (en) * | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US6291868B1 (en) * | 1998-02-26 | 2001-09-18 | Micron Technology, Inc. | Forming a conductive structure in a semiconductor device |
JP2000068270A (en) * | 1998-08-18 | 2000-03-03 | Sanyo Electric Co Ltd | Semiconductor device |
KR100313943B1 (en) * | 1999-04-22 | 2001-11-15 | 김영환 | Method for forming gate of semiconductor device |
JP2001298193A (en) * | 2000-04-13 | 2001-10-26 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
US6897514B2 (en) * | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
US6706594B2 (en) * | 2001-07-13 | 2004-03-16 | Micron Technology, Inc. | Optimized flash memory cell |
US6743681B2 (en) * | 2001-11-09 | 2004-06-01 | Micron Technology, Inc. | Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US6881622B2 (en) * | 2002-05-30 | 2005-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Aqueous ammonium hydroxide amorphous silicon etch method for forming microelectronic capacitor structure |
US7005697B2 (en) * | 2002-06-21 | 2006-02-28 | Micron Technology, Inc. | Method of forming a non-volatile electron storage memory and the resulting device |
JP4056817B2 (en) * | 2002-07-23 | 2008-03-05 | 光正 小柳 | Method for manufacturing nonvolatile semiconductor memory element |
TW200408323A (en) * | 2002-08-18 | 2004-05-16 | Asml Us Inc | Atomic layer deposition of high k metal oxides |
KR100763897B1 (en) * | 2002-12-23 | 2007-10-05 | 삼성전자주식회사 | Method for fabricating memory with nano dot |
-
2004
- 2004-11-23 US US10/995,839 patent/US7208793B2/en active Active
-
2005
- 2005-11-01 CN CN2005800397015A patent/CN101061585B/en active Active
- 2005-11-01 WO PCT/US2005/039391 patent/WO2006057773A1/en active Application Filing
- 2005-11-01 JP JP2007543084A patent/JP2008521249A/en active Pending
- 2005-11-01 KR KR1020077014247A patent/KR20070086562A/en active Search and Examination
-
2006
- 2006-05-09 US US11/430,793 patent/US20060205132A1/en not_active Abandoned
-
2007
- 2007-03-09 US US11/684,138 patent/US7544990B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5783478A (en) * | 1992-12-11 | 1998-07-21 | Intel Corporation | Method of frabricating a MOS transistor having a composite gate electrode |
US6417085B1 (en) * | 1999-07-02 | 2002-07-09 | Micron Technology, Inc. | Methods of forming a field effect transistor gate construction |
US20020109142A1 (en) * | 1999-12-30 | 2002-08-15 | Joo Kwang Chul | Non-volatile memory device and manufacturing method thereof |
US20040178470A1 (en) * | 2003-03-14 | 2004-09-16 | Katsuhiko Hieda | Semiconductor memory device and method of manufacturing the same |
Non-Patent Citations (1)
Title |
---|
TAKATA M ET AL: "New non-volatile memory with extremely high density metal nano-dots", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 553 - 556, XP010684073, ISBN: 0-7803-7872-5 * |
Also Published As
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US7208793B2 (en) | 2007-04-24 |
CN101061585A (en) | 2007-10-24 |
US20070145454A1 (en) | 2007-06-28 |
KR20070086562A (en) | 2007-08-27 |
CN101061585B (en) | 2012-04-18 |
US20060205132A1 (en) | 2006-09-14 |
US7544990B2 (en) | 2009-06-09 |
JP2008521249A (en) | 2008-06-19 |
US20060110870A1 (en) | 2006-05-25 |
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