WO2006057949A3 - Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor - Google Patents

Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor Download PDF

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Publication number
WO2006057949A3
WO2006057949A3 PCT/US2005/042107 US2005042107W WO2006057949A3 WO 2006057949 A3 WO2006057949 A3 WO 2006057949A3 US 2005042107 W US2005042107 W US 2005042107W WO 2006057949 A3 WO2006057949 A3 WO 2006057949A3
Authority
WO
WIPO (PCT)
Prior art keywords
addressing
memory banks
therefor
memory
interleaved
Prior art date
Application number
PCT/US2005/042107
Other languages
French (fr)
Other versions
WO2006057949A2 (en
Inventor
Maurice L Hutson
Original Assignee
Efficient Memory Technology
Maurice L Hutson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Efficient Memory Technology, Maurice L Hutson filed Critical Efficient Memory Technology
Priority to US11/719,926 priority Critical patent/US7779198B2/en
Priority to EP05849711A priority patent/EP1825433A4/en
Publication of WO2006057949A2 publication Critical patent/WO2006057949A2/en
Publication of WO2006057949A3 publication Critical patent/WO2006057949A3/en
Priority to US12/698,719 priority patent/US8190809B2/en
Priority to US12/831,400 priority patent/US8074010B2/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Error Detection And Correction (AREA)
  • Memory System (AREA)

Abstract

An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses, a plurality of abbreviated interleaves (O I, each ...2B-I), each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally. An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C +V +NMsK) and spacing data (D) for each, vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
PCT/US2005/042107 2004-11-23 2005-11-21 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor WO2006057949A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/719,926 US7779198B2 (en) 2004-11-23 2005-11-21 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories
EP05849711A EP1825433A4 (en) 2004-11-23 2005-11-21 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor
US12/698,719 US8190809B2 (en) 2004-11-23 2010-02-02 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
US12/831,400 US8074010B2 (en) 2004-11-23 2010-07-07 Intelligent memory banks for storing vectors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63055104P 2004-11-23 2004-11-23
US60/630,551 2004-11-23

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US11/719,926 A-371-Of-International US7779198B2 (en) 2004-11-23 2005-11-21 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories
US12/698,719 Continuation-In-Part US8190809B2 (en) 2004-11-23 2010-02-02 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
US12/831,400 Division US8074010B2 (en) 2004-11-23 2010-07-07 Intelligent memory banks for storing vectors

Publications (2)

Publication Number Publication Date
WO2006057949A2 WO2006057949A2 (en) 2006-06-01
WO2006057949A3 true WO2006057949A3 (en) 2007-04-19

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PCT/US2005/042107 WO2006057949A2 (en) 2004-11-23 2005-11-21 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor

Country Status (4)

Country Link
US (2) US7779198B2 (en)
EP (1) EP1825433A4 (en)
CN (1) CN101069211A (en)
WO (1) WO2006057949A2 (en)

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Also Published As

Publication number Publication date
WO2006057949A2 (en) 2006-06-01
US20100312945A1 (en) 2010-12-09
US7779198B2 (en) 2010-08-17
US20090043943A1 (en) 2009-02-12
EP1825433A4 (en) 2010-01-06
US8074010B2 (en) 2011-12-06
CN101069211A (en) 2007-11-07
EP1825433A2 (en) 2007-08-29

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