WO2006073477A2 - Method of fabricating a tunneling nanotube field effect transistor - Google Patents
Method of fabricating a tunneling nanotube field effect transistor Download PDFInfo
- Publication number
- WO2006073477A2 WO2006073477A2 PCT/US2005/018201 US2005018201W WO2006073477A2 WO 2006073477 A2 WO2006073477 A2 WO 2006073477A2 US 2005018201 W US2005018201 W US 2005018201W WO 2006073477 A2 WO2006073477 A2 WO 2006073477A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor
- nanotube
- drain
- source
- source region
- Prior art date
Links
- 239000002071 nanotube Substances 0.000 title claims abstract description 65
- 230000005641 tunneling Effects 0.000 title claims abstract description 23
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims description 30
- 239000002019 doping agent Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 6
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims description 6
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 claims description 6
- UJXZVRRCKFUQKG-UHFFFAOYSA-K indium(3+);phosphate Chemical compound [In+3].[O-]P([O-])([O-])=O UJXZVRRCKFUQKG-UHFFFAOYSA-K 0.000 claims description 6
- 239000011734 sodium Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 239000002800 charge carrier Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000001771 vacuum deposition Methods 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 claims description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 claims description 3
- 229920002873 Polyethylenimine Polymers 0.000 claims description 3
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052794 bromium Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052700 potassium Inorganic materials 0.000 claims description 3
- 239000011591 potassium Substances 0.000 claims description 3
- 229910052708 sodium Inorganic materials 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 239000002041 carbon nanotube Substances 0.000 description 3
- 229910021393 carbon nanotube Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
- Y10S977/745—Carbon nanotubes, CNTs having a modified surface
- Y10S977/749—Modified with dissimilar atoms or molecules substituted for carbon atoms of the cnt, e.g. impurity doping or compositional substitution
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/755—Nanosheet or quantum barrier/well, i.e. layer structure having one dimension or thickness of 100 nm or less
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/813—Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
- Y10S977/815—Group III-V based compounds, e.g. AlaGabIncNxPyAsz
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/849—Manufacture, treatment, or detection of nanostructure with scanning probe
- Y10S977/855—Manufacture, treatment, or detection of nanostructure with scanning probe for manufacture of nanostructure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Definitions
- the present invention generally relates to methods of fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method of fabricating a tunneling nanotube field effect transistor on a semiconductor substrate.
- Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits.
- a complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits.
- CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
- the threshold voltage Vt h i.e., voltage that is necessary to turn a transistor ON is reduced in such transistors.
- Switching characteristics of a CMOS transistor may be described by a parameter known in the art as an inverse sub-threshold slope that measures the gate voltage required to change the current through the device by one order of magnitude.
- the inverse sub-threshold slope is about 60 mV/decade and for decreasing threshold voltages V ⁇ the difference between output currents in the ON and OFF state of the transistor decreases. Too small ON/OFF current ratios prevent proper operation of digital circuits that comprise such transistors and are considered one of the major challenges in ultimately scaled devices.
- the present invention discloses a method of fabricating a tunneling nanotube field effect transistor.
- the method comprises forming in a nanotube (or nanowire, i.e., nanotube without axial opening) an n- doped region and a p-doped region that are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer is deposited on the channel region of the transistor.
- Another aspect of the invention is a tunneling nanotube field effect transistor fabricated using the inventive method.
- a transistor may be utilized as an n-type transistor device or a p-type transistor device.
- FIG. 1 depicts a flow diagram of a method for fabricating a tunneling nanotube field effect transistor in accordance with one embodiment of the present invention
- FIG. 2 depicts a schematic diagram of an exemplary tunneling nanotube field effect transistor fabricated using the method of FIG. 1 ;
- FIG. 3 depicts an exemplary circuit configuration for using the transistor of FIG. 2 as a p-type transistor device
- FIG. 4 depicts an exemplary circuit configuration for using the transistor of FIG. 2 as an n-type transistor device
- FIG. 5 depicts exemplary graphs illustrating profiles of conduction and valence bands in a nanotube material of the transistor of FIG. 2; and [0013] FIGS. 6-8 depict exemplary graphs illustrating characteristics of the transistor of FIG. 2.
- the present invention is a method of fabricating a tunneling nanotube field effect transistor using selective doping portions of a nanotube.
- nanotube is interchangeably used for both a nanotube and a nanowire (i.e., nanotube without axial opening).
- the method may be used in fabrication of ultra-large-scale integrated (ULSI) circuits and devices.
- ULSI ultra-large-scale integrated
- FIG. 1 depicts a flow diagram for one embodiment of the inventive method of fabricating a tunneling nanotube field effect transistor as a method 100.
- the method 100 includes processing steps that are performed upon a substrate where at least one tunneling nanotube field effect transistor is being fabricating. In one illustrative embodiment, such processing steps are sequentially performed in the depicted order. In alternate embodiments, at least two processing steps may be performed contemporaneously or in a different order.
- Conventional sub-processes such as application and removal of lithographic masks or sacrificial and protective layers, cleaning processes, and the like, are well known in the art and are not shown in FIG. 1.
- FIG. 2 depicts a schematic diagram of an exemplary tunneling nanotube field effect transistor 200 fabricated using the method of FIG. 1.
- the images in FIG. 2 are not depicted to scale and are simplified for illustrative purposes. To best understand the invention, the reader should simultaneously refer to FIG. 1 and FIG. 2.
- the method 100 starts at step 101 and proceeds to step 102.
- a nanotube 202 having semiconducting properties is formed on a substrate (not shown), such as a silicon (Si) or glass wafer, and the like.
- a substrate such as a silicon (Si) or glass wafer, and the like.
- charge carriers i.e., electrons and holes
- m 0 is the free electron mass
- Methods suitable for forming such nanotubes are disclosed, e.g., in commonly assigned United States patent applications serial No. 10/102,365 filed March 20, 2002, which is herein incorporated by reference.
- the nanotube 202 is a carbon (C) nanotube having an outer diameter 214 of not greater than about 5 nm (preferably, from about 1 to 3 nm or less) and a length 216 of about 25 to 1000 nm.
- semiconducting nanotubes from other materials e.g., silicon or compound semiconductors, such as gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), and the like
- GaAs gallium arsenide
- InP indium phosphate
- InGaAs indium gallium arsenide
- a gate dielectric layer 204 is formed over a central region 222 of the nanotube 202.
- the region 222 may have a length 218 in a range from 5 to 200 nm and represents an intrinsic channel region of the transistor 200 being fabricated.
- the gate dielectric layer 204 comprises silicon dioxide (SiO 2 ) and formed to a thickness of about 1 to 5 nm.
- the gate dielectric layer 204 may be formed from a high dielectric constant (high-k) material, such as aluminum oxide (AI 2 O 3 ), hafnium dioxide (HfO 2 ), and the like.
- high-k high dielectric constant
- the gate dielectric layer 204 is formed over the entire channel region 222 and wraps the nanotube 202.
- a gate electrode 206 is formed upon the gate dielectric layer 204.
- the gate electrode 206 generally has a thickness from 5 to 50 nm and may comprise at least one of a metal, metal alloy, or a conductive compound. Suitable materials for the gate electrode 206 have high electrical conductivity, as well as compatible with materials of the gate dielectric layer 204 and materials used in electrical wiring (e.g., copper (Cu) wiring) interconnecting the transistor 200 being fabricated to external integrated circuits and devices (discussed below in reference to FIGS. 3-4).
- the gate electrode 206 is formed from titanium (Ti).
- the gate dielectric layer 204 and gate electrode 206 may be formed using conventional vacuum deposition techniques, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), evaporation, and the like.
- ALD atomic layer deposition
- PVD physical vapor deposition
- CVD chemical vapor deposition
- PECVD plasma enhanced CVD
- evaporation evaporation, and the like.
- a first drain/source region 220 is formed in the nanotube 202 adjacent to the channel region 222 by selectively doping the region 220 using at least one n-type dopant.
- a length 230 of the first drain/source region 220 is about 10 to 400 nm.
- the first drain/source region 220 extends from the channel region 222 to a first end 234 of the nanotube 202.
- a distal portion 236 of the nanotube 202 may be not doped.
- Suitable n-type dopants include electron donors, such as potassium (K), sodium (Na), molecules of polyethylenimine which is a polymer and in that sense a long chain of molecules, and the like. While segment 220 of the nanotube is being n-doped, other portions of the nanotube can be protected e.g., through the use of a resist layer, a masking layer or alike to prevent doping of other regions of the nanotube.
- a second drain/source region 224 is formed in the nanotube 202 adjacent to the channel region 222 by selectively doping the region 224 using at least one p-type dopant.
- a length 232 of the second drain/source region 224 is about 10 to 400 nm.
- the second drain/source region 224 extends from the channel region 222 to a second end 238 of the nanotube 202.
- a distal portion 240 of the nanotube 202 may be not doped.
- Suitable p-type dopants include hole donors, such as chlorine (Cl 2 ), bromine (Br 2 ), and the like.
- Selective doping of the first drain/source region 220 and second drain/source region 224 may be performed using a metal/molecule deposition process.
- the dopants generally are materials with a different electron or hole affinity.
- the nanotube 202 may be doped, in the regions 220 and 224, using a charge transfer from the respective dopant to the nanotube.
- electrical contacts 208, 210, and 212 are formed upon the first drain/source region 220, gate electrode 206, and second drain/source region 224, respectively.
- the contacts 208, 210, and 212 are used as terminals for connecting the transistor 200 to external integrated circuits and devices.
- the gate electrode 206 may be used as a contact, and, as such, the contact 210 is optional.
- the contacts 208, 210, and 212 may be formed from at least one conductive material (e.g., a metal, an alloy of the metal, or a conductive compound) that is compatible with respective underlying and overlying material layers.
- the contacts 208 and 212 are formed from aluminum (Al) and palladium (Pd), respectively, and the contact 210 is formed from titanium (Ti).
- step 112 fabrication of the tunneling nanotube field effect transistor 200 is completed.
- step 114 the method 100 ends.
- the tunneling nanotube field effect transistor 200 may be used as either an n-type transistor device or a p-type transistor device.
- FIG. 3 depicts an exemplary circuit configuration 300 for using the transistor 200 as the p-type transistor device.
- the circuit configuration 300 comprises the transistor 200, a source 302 of a ground, or common, potential (i.e., ground terminal) coupled to the contact 208, a source 304 of a drain voltage V dS coupled to the contact 212, and a source 306 of a gate voltage V gs coupled to the contact 210.
- the sources 304 and 306 apply controlled positive potentials (i.e., negative voltages) to the contacts 212 and 210, respectively, while the voltages Vd S and V gs are equal to or less (i.e., negative voltages) than the ground potential.
- FIG. 4 depicts an exemplary circuit configuration 400 for using the transistor 200 as the n-type transistor device.
- the circuit configuration 400 comprises the transistor 200, a source 302 of the ground potential coupled to the contact 212, a source 404 of the drain voltage V dS coupled to the contact 208, and a source 406 of the gate voltage V gs coupled to the contact 210.
- the sources 404 and 406 apply controlled negative potentials (i.e. positive voltages) to the contacts 208 and 210, respectively, while the voltages V d s and V gs are equal to or greater (i.e., positive voltages) than the ground potential.
- FIG. 5 depicts a series of exemplary graphs illustrating dependence of profiles of conduction and valence bands (y-axis 502) in the carbon nanotube material (x-axis 504) of the transistor 200 from a distance along the carbon nanotube 202.
- the transistor 200 comprises the first and second drain/source regions 220 and 224 having the respective lengths 230 and 232 of about 10 nm and the channel region 222 having the length 218 of about 30 nm.
- Effective quantum mechanical tunneling of charge carriers in the transistor 200 i.e. flow of charge carriers through the transistor
- a lower boundary 508 of the conduction band in the first drain/source region 220 is located below an upper boundary 510 of the valence band in the channel region 222 of the transistor, thus forming a potential, or vertical, gap 512 between the conduction and valence bands.
- FIG. 6 depicts a series of exemplary graphs illustrating dependence of an output current l d (y-axis 602) from the gate voltage V gs (x-axis 604) of the exemplary p-type transistor 200 having a thickness t ox of the SiO 2 gate dielectric layer 204 in a range from 3 to 30 nm. These graphs may be used to calculate an inverse sub-threshold slope S ⁇ dV gs /dlog(l d ) of the transistor 200.
- the inverse sub-threshold slope S is a measure of the switching characteristic of a transistor and determines a difference in the gate voltage V gs that causes an order of magnitude (i.e., decade) change of the output current I d of the transistor.
- the inverse sub-threshold slope S is about 16 mV/decade for the output currents I d in a range between 0.1 pA and 0.1 nA and about 27 mV/decade for the output currents in a range from 1 pA to 1 nA, respectively.
- the transistor 200 significantly outperforms conventional complimentary metal-oxide-semiconductor (CMOS) field effect transistors having the inverse sub-threshold slope S ⁇ 60 mV/decade, while operating at the same gate voltages V gs as the CMOS transistors.
- CMOS complimentary metal-oxide-semiconductor
- characteristics of the transistor 200 remain unchanged and do not show a drain induced barrier lowering-like (DIBL-like) effect at the negative gate voltages V gs .
- DIBL-like drain induced barrier lowering-like
- FIG. 8 depicts a series of exemplary graphs illustrating output characteristics of the exemplary p-type transistor 200 of FIG. 2. More specifically, the graphs in FIG. 8 show dependence of the output current I d (y- axis 802) from the drain voltage V dS (x-axis 804) at the gate voltages V gs in a range from -0.4 to -OJV.
- the transistor 200 has output characteristics with a linear region 806 at small drain voltages V ds and a saturation region 808 at large drain voltages.
- the inventive tunneling nanotube field effect transistors have a favorable combination of characteristics for use in the integrated circuits: small footprint and minimal power consumption in combination with the low inverse subthreshold slope S that, in a broad range of drain voltages, is independent from drain voltage, as well as attainable at low threshold voltage and low gate and drain voltages. Furthermore, the tunneling nanotube field effect transistors have output characteristics that are compatible with ones of the CMOS transistors and, as such, may be used in integrated circuits together with the CMOS transistors or as a replacement for the CMOS transistors.
Abstract
A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube (202) an n-doped region (220) an a p-doped region (224) which are separated by an undoped channel region (222) of the transistor. Electrical contacts (208), (210) an (212) are provided for the doped regions and a gate electrode (206) that is formed upon a gate dielectric layer (204) deposited on at least a portion of the channel region of the transistor.
Description
METHOD OF FABRICATING A TUNNELING NANOTUBE FIELD EFFECT TRANSISTOR
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention generally relates to methods of fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method of fabricating a tunneling nanotube field effect transistor on a semiconductor substrate.
Description of the Related Art
[0002J Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits. In particular, the threshold voltage Vth (i.e., voltage that is necessary to turn a transistor ON) is reduced in such transistors.
[0003] Switching characteristics of a CMOS transistor may be described by a parameter known in the art as an inverse sub-threshold slope that measures the gate voltage required to change the current through the device by one order of magnitude. In conventional CMOS transistors, the inverse sub-threshold slope is about 60 mV/decade and for decreasing threshold voltages V^ the difference between output currents in the ON and OFF state of the transistor decreases. Too small ON/OFF current ratios prevent proper operation of digital circuits that comprise such transistors and are considered one of the major challenges in ultimately scaled devices.
[0004] Therefore, there is a need in the art for an improved method of fabricating a field effect transistor.
SUMMARY OF THE INVENTION
[0005] In one embodiment, the present invention discloses a method of fabricating a tunneling nanotube field effect transistor. The method comprises forming in a nanotube (or nanowire, i.e., nanotube without axial opening) an n- doped region and a p-doped region that are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer is deposited on the channel region of the transistor.
[0006] Another aspect of the invention is a tunneling nanotube field effect transistor fabricated using the inventive method. Such a transistor may be utilized as an n-type transistor device or a p-type transistor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
[0008] FIG. 1 depicts a flow diagram of a method for fabricating a tunneling nanotube field effect transistor in accordance with one embodiment of the present invention;
[0009] FIG. 2 depicts a schematic diagram of an exemplary tunneling nanotube field effect transistor fabricated using the method of FIG. 1 ;
[0010] FIG. 3 depicts an exemplary circuit configuration for using the transistor of FIG. 2 as a p-type transistor device;
[0011] FIG. 4 depicts an exemplary circuit configuration for using the transistor of FIG. 2 as an n-type transistor device;
[0012] FIG. 5 depicts exemplary graphs illustrating profiles of conduction and valence bands in a nanotube material of the transistor of FIG. 2; and
[0013] FIGS. 6-8 depict exemplary graphs illustrating characteristics of the transistor of FIG. 2.
[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
[0015] It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
DETAILED DESCRIPTION
[0016] The present invention is a method of fabricating a tunneling nanotube field effect transistor using selective doping portions of a nanotube. Herein, the term "nanotube" is interchangeably used for both a nanotube and a nanowire (i.e., nanotube without axial opening). The method may be used in fabrication of ultra-large-scale integrated (ULSI) circuits and devices.
[0017] FIG. 1 depicts a flow diagram for one embodiment of the inventive method of fabricating a tunneling nanotube field effect transistor as a method 100. The method 100 includes processing steps that are performed upon a substrate where at least one tunneling nanotube field effect transistor is being fabricating. In one illustrative embodiment, such processing steps are sequentially performed in the depicted order. In alternate embodiments, at least two processing steps may be performed contemporaneously or in a different order. Conventional sub-processes, such as application and removal of lithographic masks or sacrificial and protective layers, cleaning processes, and the like, are well known in the art and are not shown in FIG. 1.
[0018] FIG. 2 depicts a schematic diagram of an exemplary tunneling nanotube field effect transistor 200 fabricated using the method of FIG. 1. The images in FIG. 2 are not depicted to scale and are simplified for illustrative purposes. To
best understand the invention, the reader should simultaneously refer to FIG. 1 and FIG. 2.
[0019] The method 100 starts at step 101 and proceeds to step 102. At step 102, a nanotube 202 having semiconducting properties is formed on a substrate (not shown), such as a silicon (Si) or glass wafer, and the like. Best results may be achieved using nanotubes where charge carriers (i.e., electrons and holes) have minimal and similar effective masses (e.g., less than about 0.1m0, where m0 is the free electron mass), as well as minimal cross-sectional dimensions and facilitate a ballistic mechanism of charge transfer. Methods suitable for forming such nanotubes are disclosed, e.g., in commonly assigned United States patent applications serial No. 10/102,365 filed March 20, 2002, which is herein incorporated by reference. In one exemplary embodiment, the nanotube 202 is a carbon (C) nanotube having an outer diameter 214 of not greater than about 5 nm (preferably, from about 1 to 3 nm or less) and a length 216 of about 25 to 1000 nm. In alternate embodiments, semiconducting nanotubes from other materials (e.g., silicon or compound semiconductors, such as gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), and the like) may be used to fabricate the transistor 200.
[0020] At step 104, a gate dielectric layer 204 is formed over a central region 222 of the nanotube 202. The region 222 may have a length 218 in a range from 5 to 200 nm and represents an intrinsic channel region of the transistor 200 being fabricated. In one exemplary embodiment, the gate dielectric layer 204 comprises silicon dioxide (SiO2) and formed to a thickness of about 1 to 5 nm. Alternatively, the gate dielectric layer 204 may be formed from a high dielectric constant (high-k) material, such as aluminum oxide (AI2O3), hafnium dioxide (HfO2), and the like. In the depicted embodiment, the gate dielectric layer 204 is formed over the entire channel region 222 and wraps the nanotube 202.
[0021] At step 106, a gate electrode 206 is formed upon the gate dielectric layer 204. The gate electrode 206 generally has a thickness from 5 to 50 nm
and may comprise at least one of a metal, metal alloy, or a conductive compound. Suitable materials for the gate electrode 206 have high electrical conductivity, as well as compatible with materials of the gate dielectric layer 204 and materials used in electrical wiring (e.g., copper (Cu) wiring) interconnecting the transistor 200 being fabricated to external integrated circuits and devices (discussed below in reference to FIGS. 3-4). In one exemplary embodiment, the gate electrode 206 is formed from titanium (Ti).
[0022] The gate dielectric layer 204 and gate electrode 206 may be formed using conventional vacuum deposition techniques, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), evaporation, and the like.
[0023] At step 108, a first drain/source region 220 is formed in the nanotube 202 adjacent to the channel region 222 by selectively doping the region 220 using at least one n-type dopant. In one exemplary embodiment, a length 230 of the first drain/source region 220 is about 10 to 400 nm. In the depicted embodiment, the first drain/source region 220 extends from the channel region 222 to a first end 234 of the nanotube 202. In an alternative embodiment, a distal portion 236 of the nanotube 202 may be not doped. Suitable n-type dopants include electron donors, such as potassium (K), sodium (Na), molecules of polyethylenimine which is a polymer and in that sense a long chain of molecules, and the like. While segment 220 of the nanotube is being n-doped, other portions of the nanotube can be protected e.g., through the use of a resist layer, a masking layer or alike to prevent doping of other regions of the nanotube.
[0024] At step 110, a second drain/source region 224 is formed in the nanotube 202 adjacent to the channel region 222 by selectively doping the region 224 using at least one p-type dopant. In one exemplary embodiment, a length 232 of the second drain/source region 224 is about 10 to 400 nm. In the depicted embodiment, the second drain/source region 224 extends from the channel region 222 to a second end 238 of the nanotube 202. In an alternative
embodiment, a distal portion 240 of the nanotube 202 may be not doped. Suitable p-type dopants include hole donors, such as chlorine (Cl2), bromine (Br2), and the like. Again, while segment 224 of the nanotube is being p-doped, other portions of the nanotube can be protected e.g., through the use of a resist layer, a masking layer or alike to prevent doping of other regions of the nanotube.
[0025] Selective doping of the first drain/source region 220 and second drain/source region 224 may be performed using a metal/molecule deposition process. The dopants generally are materials with a different electron or hole affinity. In both the p and n types of the deposition process, the nanotube 202 may be doped, in the regions 220 and 224, using a charge transfer from the respective dopant to the nanotube.
[0026] At step 112, electrical contacts 208, 210, and 212 are formed upon the first drain/source region 220, gate electrode 206, and second drain/source region 224, respectively. The contacts 208, 210, and 212 are used as terminals for connecting the transistor 200 to external integrated circuits and devices. In an alternate embodiment, the gate electrode 206 may be used as a contact, and, as such, the contact 210 is optional. The contacts 208, 210, and 212 may be formed from at least one conductive material (e.g., a metal, an alloy of the metal, or a conductive compound) that is compatible with respective underlying and overlying material layers. Material of the n-contact (contact 208) should have a smaller work function, than the material of the p-contact (contact 212). In one exemplary embodiment, using a conventional vacuum deposition technique, the contacts 208 and 212 are formed from aluminum (Al) and palladium (Pd), respectively, and the contact 210 is formed from titanium (Ti).
[0027] Upon completion of step 112, fabrication of the tunneling nanotube field effect transistor 200 is completed. At step 114, the method 100 ends.
[0028] In integrated circuits, the tunneling nanotube field effect transistor 200 may be used as either an n-type transistor device or a p-type transistor device.
[0029] FIG. 3 depicts an exemplary circuit configuration 300 for using the transistor 200 as the p-type transistor device. In one embodiment, the circuit configuration 300 comprises the transistor 200, a source 302 of a ground, or common, potential (i.e., ground terminal) coupled to the contact 208, a source 304 of a drain voltage VdS coupled to the contact 212, and a source 306 of a gate voltage Vgs coupled to the contact 210. In operation, the sources 304 and 306 apply controlled positive potentials (i.e., negative voltages) to the contacts 212 and 210, respectively, while the voltages VdS and Vgs are equal to or less (i.e., negative voltages) than the ground potential.
[0030] FIG. 4 depicts an exemplary circuit configuration 400 for using the transistor 200 as the n-type transistor device. In one embodiment, the circuit configuration 400 comprises the transistor 200, a source 302 of the ground potential coupled to the contact 212, a source 404 of the drain voltage VdS coupled to the contact 208, and a source 406 of the gate voltage Vgs coupled to the contact 210. In operation, the sources 404 and 406 apply controlled negative potentials (i.e. positive voltages) to the contacts 208 and 210, respectively, while the voltages Vds and Vgs are equal to or greater (i.e., positive voltages) than the ground potential.
[0031] FIG. 5 depicts a series of exemplary graphs illustrating dependence of profiles of conduction and valence bands (y-axis 502) in the carbon nanotube material (x-axis 504) of the transistor 200 from a distance along the carbon nanotube 202. In the depicted embodiment, the transistor 200 comprises the first and second drain/source regions 220 and 224 having the respective lengths 230 and 232 of about 10 nm and the channel region 222 having the length 218 of about 30 nm. Depicted graphs of the conduction and valence bands relate to the circuit configuration 300 where the transistor 200 performs as a p-type device, at the drain voltage VdS = -0.1V applied to the contact 212, and at the gate voltages Vgs in a range from -0.2 to -0.5V. Effective quantum mechanical tunneling of charge carriers in the transistor 200 (i.e. flow of charge carriers through the transistor) is possible when a lower boundary 508 of the conduction band in the first drain/source region 220 is located below an upper
boundary 510 of the valence band in the channel region 222 of the transistor, thus forming a potential, or vertical, gap 512 between the conduction and valence bands. As illustrated using an arrow 506, in the carbon nanotube 202, such effective tunneling between the valence band and the conduction band exists at the gate voltages Vgs < -0.3V (e.g., at Vgs = -0.5V). Correspondingly, at Vgs > -0.3V (e.g., at Vgs = -0.2V), there is no such a gap and effective tunneling between the valence and conduction bands. In operation, at Vgs ≤ - 0.3V, the p-type transistor 200 asserts an ON (conducting) state and, correspondingly, at Vgs > -0.3V, the transistor asserts an OFF (non-conducting) state.
[0032] FIG. 6 depicts a series of exemplary graphs illustrating dependence of an output current ld (y-axis 602) from the gate voltage Vgs (x-axis 604) of the exemplary p-type transistor 200 having a thickness tox of the SiO2 gate dielectric layer 204 in a range from 3 to 30 nm. These graphs may be used to calculate an inverse sub-threshold slope S ~ dVgs/dlog(ld) of the transistor 200. The inverse sub-threshold slope S is a measure of the switching characteristic of a transistor and determines a difference in the gate voltage Vgs that causes an order of magnitude (i.e., decade) change of the output current Id of the transistor. In the transistor 200 having the thickness of the SiO2 gate dielectric layer 204 tox = 3 nm, the inverse sub-threshold slope S is about 16 mV/decade for the output currents Id in a range between 0.1 pA and 0.1 nA and about 27 mV/decade for the output currents in a range from 1 pA to 1 nA, respectively. As such, the transistor 200 significantly outperforms conventional complimentary metal-oxide-semiconductor (CMOS) field effect transistors having the inverse sub-threshold slope S ~ 60 mV/decade, while operating at the same gate voltages Vgs as the CMOS transistors.
[0033] FIG. 7 depicts a series of exemplary graphs illustrating the dependence of the output current ld (y-axis 702) from the gate voltage Vgs (x-axis 704) of the exemplary p-type transistor 200 of FIG. 6 having the thickness tox = 3 nm at the drain voltages VdS in a range from -0.1 to -0.4V. In common with other p-type transistor devices, characteristics of the transistor 200 remain unchanged and
do not show a drain induced barrier lowering-like (DIBL-like) effect at the negative gate voltages Vgs.
[0034] FIG. 8 depicts a series of exemplary graphs illustrating output characteristics of the exemplary p-type transistor 200 of FIG. 2. More specifically, the graphs in FIG. 8 show dependence of the output current Id (y- axis 802) from the drain voltage VdS (x-axis 804) at the gate voltages Vgs in a range from -0.4 to -OJV. The transistor 200 has output characteristics with a linear region 806 at small drain voltages Vds and a saturation region 808 at large drain voltages.
[0035] The inventive tunneling nanotube field effect transistors have a favorable combination of characteristics for use in the integrated circuits: small footprint and minimal power consumption in combination with the low inverse subthreshold slope S that, in a broad range of drain voltages, is independent from drain voltage, as well as attainable at low threshold voltage and low gate and drain voltages. Furthermore, the tunneling nanotube field effect transistors have output characteristics that are compatible with ones of the CMOS transistors and, as such, may be used in integrated circuits together with the CMOS transistors or as a replacement for the CMOS transistors.
[0036] While the foregoing is directed to the illustrative embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A method of fabricating a tunneling nanotube field effect transistor, comprising: providing a nanotube having semiconducting properties; defining in the nanotube a channel region, a first drain/source region, and a second drain/source region of the transistor, the first drain/source region adjacent a first end of the channel region and the second drain/source region adjacent a second end of the channel region; forming a gate dielectric layer on the channel region; forming a gate electrode on the gate dielectric layer; selectively doping the first drain/source region using an n-type dopant; selectively doping the second drain/source region using a p-type dopant; and forming at least one electrical contact on each of the gate electrode and said drain/source regions.
2. The method of claim 1 wherein the nanotube has no axial opening.
3. The method of claim 1 wherein the nanotube is one of a carbon (C) nanotube, a silicon (Si) nanotube, and a nanotube comprising a compound semiconductor.
4. The method of claim 3 wherein the compound semiconductor is one of gallium arsenide (GaAs), indium phosphate (InP), and indium gallium arsenide (InGaAs).
5. The method of claim 1 wherein an outer diameter of the nanotube is less than about 5 nm.
6. The method of claim 1 wherein doping facilitates in the channel region effective quantum mechanical tunneling of charge carriers.
7. The method of claim 1 wherein the n-type dopant comprises at least one of potassium (K), sodium (Na), and molecules of polyethylenimine.
8. The method of claim 1 wherein the p-type dopant comprises at least one of chlorine (Cl2) and bromine (Br2).
9. The method of claim 1 wherein doping is performed using a metal/molecule deposition process.
10. The method of claim 1 wherein the gate dielectric layer is formed from at least one of SiO2, HfO2, and Al2θ3 to a thickness of about 1 to 10 nm.
11. The method of claim 1 wherein the gate electrode is formed from at least one of a metal, an alloy of the metal, or a conductive compound.
12. The method of claim 1 wherein at least one electrical contact is formed from at least one of a metal, an alloy of the metal, or a conductive compound.
13. The method of claim 1 wherein the gate dielectric layer, gate electrode, and at least one electrical contact are formed using vacuum deposition processes.
14. A tunneling nanotube field effect transistor, comprising: a channel region defined in a nanotube, the channel region having semiconducting properties; a gate dielectric layer formed on the channel region; a gate electrode formed on the gate dielectric layer; a first drain/source region formed in the nanotube adjacent a first end of the channel region, the first drain/source region selectively doped using an n- type dopant; a second drain/source region formed in the nanotube adjacent a second end of the channel region, the second drain/source region selectively doped using a p-type dopant; and at least one electrical contact on each of the gate electrode and said drain/source regions.
15. The transistor of claim 14 wherein the first drain/source region is coupled to a source of a ground potential, the second drain/source region is coupled to a source of a drain voltage, and the gate electrode is coupled to a source of a gate voltage thereby forming a p-type transistor device.
16. The transistor of claim 15 wherein voltages at the second drain/source region and gate electrode are equal to or less than the ground potential.
17. The transistor of claim 14 wherein the second drain/source region is coupled to a source of a ground potential, the first drain/source region is coupled to a source of drain voltage, and the gate electrode is coupled to a source of a gate voltage thereby forming an n-type transistor device.
18. The transistor of claim 17 wherein voltages at the first drain/source region and gate electrode are equal to or greater than the ground potential.
19. The transistor of claim 14 wherein the nanotube has no axial opening.
20. The transistor of claim 14 wherein the nanotube is one of a carbon (C) nanotube, a silicon (Si) nanotube, and a nanotube comprising a compound semiconductor.
21. The transistor of claim 20 wherein the compound semiconductor is one of gallium arsenide (GaAs), indium phosphate (InP), and indium gallium arsenide (InGaAs).
22. The transistor of claim 14 wherein an outer diameter of the nanotube is less than 5 nm.
23. The transistor of claim 14 wherein doping facilitates in the channel region effective quantum mechanical tunneling of charge carriers.
24. The transistor of claim 14 wherein the n-type dopant comprises at least one of potassium (K), sodium (Na), and molecules of polyethylenimine.
25. The transistor of claim 14 wherein the p-type dopant comprises at least one of chlorine (CI2) and bromine (Br2).
26. The transistor of claim 14 wherein doping is performed using a metal/molecule deposition process.
27. The transistor of claim 14 wherein the gate dielectric layer is formed from at least one of Siθ2, HfO2, and AI2O3 to a thickness of about 1 to 10 nm.
28. The transistor of claim 14 wherein the gate electrode is formed from at least one of a metal, an alloy of the metal, or a conductive compound.
29. The transistor of claim 14 wherein the at least one electrical contact is formed from at least one of a metal, an alloy of the metal, or a conductive compound.
30. The transistor of claim 14 wherein the gate dielectric layer, gate electrode, and the at least one electrical contact are formed using vacuum deposition processes.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05856753.8A EP1754262B1 (en) | 2004-05-25 | 2005-05-24 | Tunneling nanotube field effect transistor and method of fabricating the same |
JP2007515262A JP5263755B2 (en) | 2004-05-25 | 2005-05-24 | Tunnel nanotube field effect transistor and method of fabricating the same |
CN2005800165130A CN101065811B (en) | 2004-05-25 | 2005-05-24 | Method of fabricating a tunneling nanotube field effect transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/852,891 | 2004-05-25 | ||
US10/852,891 US7180107B2 (en) | 2004-05-25 | 2004-05-25 | Method of fabricating a tunneling nanotube field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006073477A2 true WO2006073477A2 (en) | 2006-07-13 |
WO2006073477A3 WO2006073477A3 (en) | 2007-01-25 |
Family
ID=35459605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/018201 WO2006073477A2 (en) | 2004-05-25 | 2005-05-24 | Method of fabricating a tunneling nanotube field effect transistor |
Country Status (6)
Country | Link |
---|---|
US (1) | US7180107B2 (en) |
EP (1) | EP1754262B1 (en) |
JP (1) | JP5263755B2 (en) |
CN (1) | CN101065811B (en) |
TW (1) | TWI339852B (en) |
WO (1) | WO2006073477A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1901355A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | Tunnel effect transistors based on elongate monocrystalline nanostructures having a heterostructure |
EP1900681A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | Tunnel effect transistors based on silicon nanowires |
EP1901354A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | A tunnel field-effect transistor with gated tunnel barrier |
JP2008072104A (en) * | 2006-09-15 | 2008-03-27 | Interuniv Micro Electronica Centrum Vzw | Tunnel effect transistor based on silicon nanowire |
WO2011076245A1 (en) * | 2009-12-21 | 2011-06-30 | Imec | Double gate nanostructure fet |
US8120115B2 (en) | 2007-03-12 | 2012-02-21 | Imec | Tunnel field-effect transistor with gated tunnel barrier |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB0415891D0 (en) * | 2004-07-16 | 2004-08-18 | Koninkl Philips Electronics Nv | Nanoscale fet |
KR101025846B1 (en) * | 2004-09-13 | 2011-03-30 | 삼성전자주식회사 | Transistor of semiconductor device comprising carbon nano-tube channel |
WO2006077585A2 (en) * | 2005-01-18 | 2006-07-27 | Shye Shapira | Apparatus and method for control of tunneling in a small-scale electronic structure |
KR100682925B1 (en) * | 2005-01-26 | 2007-02-15 | 삼성전자주식회사 | Multi-bit non-volatile memory device, and method of operating the same |
DE102005046427B4 (en) * | 2005-09-28 | 2010-09-23 | Infineon Technologies Ag | Power transistor with parallel nanowires |
US7492015B2 (en) * | 2005-11-10 | 2009-02-17 | International Business Machines Corporation | Complementary carbon nanotube triple gate technology |
EP1979946B1 (en) * | 2006-01-25 | 2011-10-19 | Nxp B.V. | Nanowire tunneling transistor |
WO2007099642A1 (en) * | 2006-03-03 | 2007-09-07 | Fujitsu Limited | Field effect transistor employing carbon nanotube, method for fabricating the same and sensor |
CN100435351C (en) * | 2006-04-28 | 2008-11-19 | 北京芯技佳易微电子科技有限公司 | Method for modulating carrying-performance nano-grade field effect transistor using dipale effect |
US7893476B2 (en) * | 2006-09-15 | 2011-02-22 | Imec | Tunnel effect transistors based on silicon nanowires |
WO2008157509A2 (en) * | 2007-06-14 | 2008-12-24 | University Of Florida Research Foundation, Inc. | Room temperature carbon nanotubes integrated on cmos |
WO2009042218A1 (en) * | 2007-09-27 | 2009-04-02 | University Of Maryland | Lateral two-terminal nanotube devices and method for their formation |
US8043978B2 (en) * | 2007-10-11 | 2011-10-25 | Riken | Electronic device and method for producing electronic device |
EP2161755A1 (en) * | 2008-09-05 | 2010-03-10 | University College Cork-National University of Ireland, Cork | Junctionless Metal-Oxide-Semiconductor Transistor |
US8912522B2 (en) * | 2009-08-26 | 2014-12-16 | University Of Maryland | Nanodevice arrays for electrical energy storage, capture and management and method for their formation |
US10032569B2 (en) * | 2009-08-26 | 2018-07-24 | University Of Maryland, College Park | Nanodevice arrays for electrical energy storage, capture and management and method for their formation |
US8288803B2 (en) * | 2009-08-31 | 2012-10-16 | International Business Machines Corporation | Tunnel field effect devices |
JP5652827B2 (en) | 2009-09-30 | 2015-01-14 | 国立大学法人北海道大学 | Tunnel field effect transistor and manufacturing method thereof |
US8384065B2 (en) * | 2009-12-04 | 2013-02-26 | International Business Machines Corporation | Gate-all-around nanowire field effect transistors |
US8173993B2 (en) * | 2009-12-04 | 2012-05-08 | International Business Machines Corporation | Gate-all-around nanowire tunnel field effect transistors |
US8129247B2 (en) * | 2009-12-04 | 2012-03-06 | International Business Machines Corporation | Omega shaped nanowire field effect transistors |
US8143113B2 (en) | 2009-12-04 | 2012-03-27 | International Business Machines Corporation | Omega shaped nanowire tunnel field effect transistors fabrication |
US8097515B2 (en) * | 2009-12-04 | 2012-01-17 | International Business Machines Corporation | Self-aligned contacts for nanowire field effect transistors |
US8455334B2 (en) * | 2009-12-04 | 2013-06-04 | International Business Machines Corporation | Planar and nanowire field effect transistors |
US8722492B2 (en) * | 2010-01-08 | 2014-05-13 | International Business Machines Corporation | Nanowire pin tunnel field effect devices |
CN101777499B (en) | 2010-01-22 | 2011-08-24 | 北京大学 | Method for self-aligned preparation of tunneling field-effect transistors (TFETs) on basis of planar technology |
US8324940B2 (en) | 2010-04-13 | 2012-12-04 | International Business Machines Corporation | Nanowire circuits in matched devices |
US8361907B2 (en) | 2010-05-10 | 2013-01-29 | International Business Machines Corporation | Directionally etched nanowire field effect transistors |
US8324030B2 (en) | 2010-05-12 | 2012-12-04 | International Business Machines Corporation | Nanowire tunnel field effect transistors |
US8445320B2 (en) * | 2010-05-20 | 2013-05-21 | International Business Machines Corporation | Graphene channel-based devices and methods for fabrication thereof |
US8835231B2 (en) | 2010-08-16 | 2014-09-16 | International Business Machines Corporation | Methods of forming contacts for nanowire field effect transistors |
US8536563B2 (en) | 2010-09-17 | 2013-09-17 | International Business Machines Corporation | Nanowire field effect transistors |
KR101733050B1 (en) * | 2010-11-22 | 2017-05-08 | 삼성전자주식회사 | 3-Terminal Resonator and the Method thereof |
CN102683209B (en) * | 2011-03-18 | 2015-01-21 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
CN103094347B (en) * | 2013-01-11 | 2015-09-02 | 南京邮电大学 | A kind of bi-material layers owes the carbon nanotube field-effect pipe of folded dual material gate structure |
CN103247688B (en) * | 2013-04-22 | 2016-08-17 | 南京邮电大学 | A kind of graphene field effect pipe of bi-material layers grid linear doping |
US8975123B2 (en) | 2013-07-09 | 2015-03-10 | International Business Machines Corporation | Tunnel field-effect transistors with a gate-swing broken-gap heterostructure |
US9203041B2 (en) * | 2014-01-31 | 2015-12-01 | International Business Machines Corporation | Carbon nanotube transistor having extended contacts |
CN105097904B (en) * | 2014-05-05 | 2019-01-25 | 中芯国际集成电路制造(上海)有限公司 | Tunnelling carbon nanotube field-effect transistor and its manufacturing method |
CN105097913B (en) * | 2014-05-05 | 2018-12-04 | 中芯国际集成电路制造(上海)有限公司 | Field effect transistor and its manufacturing method |
KR102154185B1 (en) | 2014-09-19 | 2020-09-09 | 삼성전자 주식회사 | Semiconductor device |
CN105990147B (en) * | 2015-02-27 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
CN106601738B (en) * | 2015-10-15 | 2018-08-24 | 上海新昇半导体科技有限公司 | Complementary field-effect transist and preparation method thereof |
JP6730598B2 (en) * | 2016-07-19 | 2020-07-29 | 富士通株式会社 | Semiconductor device |
US10170702B2 (en) | 2017-01-12 | 2019-01-01 | International Business Machines Corporation | Intermetallic contact for carbon nanotube FETs |
JP6773615B2 (en) * | 2017-08-21 | 2020-10-21 | 日本電信電話株式会社 | Manufacturing method of nanowire transistor |
US10818785B2 (en) * | 2017-12-04 | 2020-10-27 | Ecole Polytechnique Federale De Lausanne (Epfl) | Sensing device for sensing minor charge variations |
CN108598170B (en) * | 2018-05-24 | 2022-07-08 | 厦门半导体工业技术研发有限公司 | Nanowire transistor and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003083949A1 (en) | 2002-03-28 | 2003-10-09 | Koninklijke Philips Electronics N.V. | Nanowire and electronic device |
US20040061422A1 (en) | 2002-09-26 | 2004-04-01 | International Business Machines Corporation | System and method for molecular optical emission |
EP1411554A1 (en) | 2001-07-05 | 2004-04-21 | NEC Corporation | Field-effect transistor constituting channel by carbon nano tubes |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US130333A (en) * | 1872-08-06 | Improvement in machines for glazing and polishing saw-blades | ||
JPS5754370A (en) * | 1980-09-19 | 1982-03-31 | Nippon Telegr & Teleph Corp <Ntt> | Insulating gate type transistor |
JP2773474B2 (en) * | 1991-08-06 | 1998-07-09 | 日本電気株式会社 | Semiconductor device |
JP3393237B2 (en) | 1994-10-04 | 2003-04-07 | ソニー株式会社 | Method for manufacturing semiconductor device |
US6331262B1 (en) * | 1998-10-02 | 2001-12-18 | University Of Kentucky Research Foundation | Method of solubilizing shortened single-walled carbon nanotubes in organic solutions |
WO2002003482A1 (en) * | 2000-07-04 | 2002-01-10 | Infineon Technologies Ag | Field effect transistor |
JP2002026154A (en) * | 2000-07-11 | 2002-01-25 | Sanyo Electric Co Ltd | Semiconductor memory and semiconductor device |
US6515339B2 (en) * | 2000-07-18 | 2003-02-04 | Lg Electronics Inc. | Method of horizontally growing carbon nanotubes and field effect transistor using the carbon nanotubes grown by the method |
US6524920B1 (en) * | 2001-02-09 | 2003-02-25 | Advanced Micro Devices, Inc. | Low temperature process for a transistor with elevated source and drain |
JP3731486B2 (en) | 2001-03-16 | 2006-01-05 | 富士ゼロックス株式会社 | Transistor |
JP4974263B2 (en) * | 2002-05-20 | 2012-07-11 | 富士通株式会社 | Manufacturing method of semiconductor device |
CN1176499C (en) * | 2002-06-13 | 2004-11-17 | 上海交通大学 | Single-electron transistor with nano metal oxide wire |
JP2004055649A (en) * | 2002-07-17 | 2004-02-19 | Konica Minolta Holdings Inc | Organic thin-film transistor and method of manufacturing the same |
CA2499950A1 (en) * | 2002-09-30 | 2004-04-15 | Nanosys, Inc. | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
US6933222B2 (en) * | 2003-01-02 | 2005-08-23 | Intel Corporation | Microcircuit fabrication and interconnection |
-
2004
- 2004-05-25 US US10/852,891 patent/US7180107B2/en active Active
-
2005
- 2005-05-20 TW TW094116452A patent/TWI339852B/en not_active IP Right Cessation
- 2005-05-24 WO PCT/US2005/018201 patent/WO2006073477A2/en not_active Application Discontinuation
- 2005-05-24 JP JP2007515262A patent/JP5263755B2/en not_active Expired - Fee Related
- 2005-05-24 EP EP05856753.8A patent/EP1754262B1/en active Active
- 2005-05-24 CN CN2005800165130A patent/CN101065811B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1411554A1 (en) | 2001-07-05 | 2004-04-21 | NEC Corporation | Field-effect transistor constituting channel by carbon nano tubes |
WO2003083949A1 (en) | 2002-03-28 | 2003-10-09 | Koninklijke Philips Electronics N.V. | Nanowire and electronic device |
US20040061422A1 (en) | 2002-09-26 | 2004-04-01 | International Business Machines Corporation | System and method for molecular optical emission |
Non-Patent Citations (1)
Title |
---|
See also references of EP1754262A4 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1901355A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | Tunnel effect transistors based on elongate monocrystalline nanostructures having a heterostructure |
EP1900681A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | Tunnel effect transistors based on silicon nanowires |
EP1901354A1 (en) * | 2006-09-15 | 2008-03-19 | Interuniversitair Microelektronica Centrum | A tunnel field-effect transistor with gated tunnel barrier |
JP2008072104A (en) * | 2006-09-15 | 2008-03-27 | Interuniv Micro Electronica Centrum Vzw | Tunnel effect transistor based on silicon nanowire |
US8120115B2 (en) | 2007-03-12 | 2012-02-21 | Imec | Tunnel field-effect transistor with gated tunnel barrier |
US8404545B2 (en) | 2007-03-12 | 2013-03-26 | Imec | Tunnel field-effect transistor with gated tunnel barrier |
WO2011076245A1 (en) * | 2009-12-21 | 2011-06-30 | Imec | Double gate nanostructure fet |
Also Published As
Publication number | Publication date |
---|---|
WO2006073477A3 (en) | 2007-01-25 |
JP5263755B2 (en) | 2013-08-14 |
EP1754262A4 (en) | 2012-03-14 |
CN101065811B (en) | 2011-03-30 |
TWI339852B (en) | 2011-04-01 |
EP1754262A2 (en) | 2007-02-21 |
US7180107B2 (en) | 2007-02-20 |
CN101065811A (en) | 2007-10-31 |
TW200603228A (en) | 2006-01-16 |
JP2008500735A (en) | 2008-01-10 |
EP1754262B1 (en) | 2015-04-08 |
US20050274992A1 (en) | 2005-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7180107B2 (en) | Method of fabricating a tunneling nanotube field effect transistor | |
US8148220B2 (en) | Tunnel effect transistors based on elongate monocrystalline nanostructures having a heterostructure | |
US8120115B2 (en) | Tunnel field-effect transistor with gated tunnel barrier | |
US9564514B2 (en) | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | |
CN104362176B (en) | Self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and manufacturing method thereof | |
US10381586B2 (en) | Carbon nanotube field-effect transistor with sidewall-protected metal contacts | |
US7511344B2 (en) | Field effect transistor | |
JP2008072104A (en) | Tunnel effect transistor based on silicon nanowire | |
WO2021227345A1 (en) | Transistor and method for fabricating the same | |
US8815669B2 (en) | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | |
US20100237410A1 (en) | Ultra-thin semiconductor on insulator metal gate complementary field effect transistor with metal gate and method of forming thereof | |
US7312510B2 (en) | Device using ambipolar transport in SB-MOSFET and method for operating the same | |
EP1901355B1 (en) | Tunnel effect transistors based on monocrystalline nanowires having a heterostructure | |
WO2021227344A1 (en) | Transistor and method for fabricating the same | |
US10141529B1 (en) | Enhancing drive current and increasing device yield in N-type carbon nanotube field effect transistors | |
Liu et al. | Vertical heterojunction Ge0. 92Sn0. 08/Ge gate-all-around nanowire pMOSFETs |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 200580016513.0 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007515262 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2005856753 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: DE |
|
WWP | Wipo information: published in national office |
Ref document number: 2005856753 Country of ref document: EP |