WO2006074024A3 - A mechanism for instruction set based thread execution on a plurality of instruction sequencers - Google Patents

A mechanism for instruction set based thread execution on a plurality of instruction sequencers Download PDF

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Publication number
WO2006074024A3
WO2006074024A3 PCT/US2005/047328 US2005047328W WO2006074024A3 WO 2006074024 A3 WO2006074024 A3 WO 2006074024A3 US 2005047328 W US2005047328 W US 2005047328W WO 2006074024 A3 WO2006074024 A3 WO 2006074024A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
level
user
sequencers
set based
Prior art date
Application number
PCT/US2005/047328
Other languages
French (fr)
Other versions
WO2006074024A2 (en
Inventor
Hong Wang
John Shen
Ed Grochowski
James Paul Held
Bryant Bigbee
Shivnandan D Kaushik
Gautham Chinya
Xiang Zou
Per Hammarlund
Xinmin Tien
Anil Aggarwal
Scott Dion Rodgers
Baiju V Patel
Richard Hankins
Original Assignee
Intel Corp
Hong Wang
John Shen
Ed Grochowski
James Paul Held
Bryant Bigbee
Shivnandan D Kaushik
Gautham Chinya
Xiang Zou
Per Hammarlund
Xinmin Tien
Anil Aggarwal
Scott Dion Rodgers
Baiju V Patel
Richard Hankins
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/173,326 external-priority patent/US8719819B2/en
Application filed by Intel Corp, Hong Wang, John Shen, Ed Grochowski, James Paul Held, Bryant Bigbee, Shivnandan D Kaushik, Gautham Chinya, Xiang Zou, Per Hammarlund, Xinmin Tien, Anil Aggarwal, Scott Dion Rodgers, Baiju V Patel, Richard Hankins filed Critical Intel Corp
Priority to DE112005003343T priority Critical patent/DE112005003343B4/en
Priority to JP2007549602A priority patent/JP5260962B2/en
Priority to CN2005800448962A priority patent/CN101116057B/en
Publication of WO2006074024A2 publication Critical patent/WO2006074024A2/en
Publication of WO2006074024A3 publication Critical patent/WO2006074024A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Abstract

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
PCT/US2005/047328 2004-12-30 2005-12-28 A mechanism for instruction set based thread execution on a plurality of instruction sequencers WO2006074024A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112005003343T DE112005003343B4 (en) 2004-12-30 2005-12-28 Mechanism for instruction set-based thread execution on multiple command schedules
JP2007549602A JP5260962B2 (en) 2004-12-30 2005-12-28 A mechanism for instruction set based on thread execution in multiple instruction sequencers
CN2005800448962A CN101116057B (en) 2004-12-30 2005-12-28 A mechanism for instruction set based thread execution on a plurality of instruction sequencers

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US64042504P 2004-12-30 2004-12-30
US60/640,425 2004-12-30
US11/173,326 2005-06-30
US11/173,326 US8719819B2 (en) 2005-06-30 2005-06-30 Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Publications (2)

Publication Number Publication Date
WO2006074024A2 WO2006074024A2 (en) 2006-07-13
WO2006074024A3 true WO2006074024A3 (en) 2006-10-26

Family

ID=36579277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/047328 WO2006074024A2 (en) 2004-12-30 2005-12-28 A mechanism for instruction set based thread execution on a plurality of instruction sequencers

Country Status (4)

Country Link
JP (2) JP5260962B2 (en)
CN (1) CN101116057B (en)
DE (1) DE112005003343B4 (en)
WO (1) WO2006074024A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0408164D0 (en) 2004-04-13 2004-05-19 Immune Targeting Systems Ltd Antigen delivery vectors and constructs
GB0716992D0 (en) 2007-08-31 2007-10-10 Immune Targeting Systems Its L Influenza antigen delivery vectors and constructs
WO2007067562A2 (en) * 2005-12-06 2007-06-14 Boston Circuits, Inc. Methods and apparatus for multi-core processing with dedicated thread management
JP4978914B2 (en) * 2007-10-19 2012-07-18 インテル・コーポレーション Method and system enabling expansion of multiple instruction streams / multiple data streams on a microprocessor
FR2950714B1 (en) * 2009-09-25 2011-11-18 Bull Sas SYSTEM AND METHOD FOR MANAGING THE INTERLEAVED EXECUTION OF INSTRUCTION WIRES
US8487909B2 (en) * 2011-07-27 2013-07-16 Cypress Semiconductor Corporation Method and apparatus for parallel scanning and data processing for touch sense arrays
US9569278B2 (en) * 2011-12-22 2017-02-14 Intel Corporation Asymmetric performance multicore architecture with same instruction set architecture
CN108241504A (en) * 2011-12-23 2018-07-03 英特尔公司 The device and method of improved extraction instruction
US10102028B2 (en) 2013-03-12 2018-10-16 Sas Institute Inc. Delivery acknowledgment in event stream processing
US20150127927A1 (en) * 2013-11-01 2015-05-07 Qualcomm Incorporated Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media
US9122651B1 (en) * 2014-06-06 2015-09-01 Sas Institute Inc. Computer system to support failover in an event stream processing system
WO2022040877A1 (en) * 2020-08-24 2022-03-03 华为技术有限公司 Graph instruction processing method and device

Citations (4)

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US6389446B1 (en) * 1996-07-12 2002-05-14 Nec Corporation Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
US20020199179A1 (en) * 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
US6651163B1 (en) * 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system
US20040163083A1 (en) * 2003-02-19 2004-08-19 Hong Wang Programmable event driven yield mechanism which may activate other threads

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JP4651790B2 (en) * 2000-08-29 2011-03-16 株式会社ガイア・システム・ソリューション Data processing device

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US6389446B1 (en) * 1996-07-12 2002-05-14 Nec Corporation Multi-processor system executing a plurality of threads simultaneously and an execution method therefor
US6651163B1 (en) * 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system
US20020199179A1 (en) * 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
US20040163083A1 (en) * 2003-02-19 2004-08-19 Hong Wang Programmable event driven yield mechanism which may activate other threads

Non-Patent Citations (2)

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Title
KUMAR R ET AL: "Single-ISA heterogeneous multi-core architectures for multithreaded workload performance", COMPUTER ARCHITECTURE, 2004. PROCEEDINGS. 31ST ANNUAL INTERNATIONAL SYMPOSIUM ON MUNCHEN, GERMANY JUNE 19-23, 2004, PISCATAWAY, NJ, USA,IEEE, 19 June 2004 (2004-06-19), pages 64 - 75, XP010769392, ISBN: 0-7695-2143-6 *
TU J-F ET AL: "SMTA: next-generation high-performance multi-threaded processor", IEE PROCEEDINGS E. COMPUTERS & DIGITAL TECHNIQUES, INSTITUTION OF ELECTRICAL ENGINEERS. STEVENAGE, GB, vol. 149, no. 5, 27 September 2002 (2002-09-27), pages 213 - 218, XP006018769, ISSN: 0143-7062 *

Also Published As

Publication number Publication date
CN101116057A (en) 2008-01-30
JP5260962B2 (en) 2013-08-14
DE112005003343B4 (en) 2011-05-19
CN101116057B (en) 2011-10-05
WO2006074024A2 (en) 2006-07-13
JP5244160B2 (en) 2013-07-24
DE112005003343T5 (en) 2007-11-29
JP2008527501A (en) 2008-07-24
JP2011023032A (en) 2011-02-03

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