WO2006085373A1

WO2006085373A1 - Non-volatile semiconductor memory and semiconductor device

Info

Publication number: WO2006085373A1
Application number: PCT/JP2005/002006
Authority: WO
Inventors: Takashi Yamaki; Jiro Ishikawa; Toshihiro Tanaka; Akira Kato
Original assignee: Renesas Technology Corp.
Priority date: 2005-02-10
Filing date: 2005-02-10
Publication date: 2006-08-17
Also published as: JPWO2006085373A1; JP4683494B2

Abstract

A non-volatile semiconductor memory (20) includes a plurality of non-volatile memory cells (1) having a threshold voltage which is increased by electron injection into a charge accumulation region and lowered by hot hole injection into the charge accumulation region. The non-volatile semiconductor memory (20) further includes control circuits (25, 36) capable of repeating the process for applying high voltage pulses for hot hole injection to a plurality of non-volatile memory cells selected as hot hole injection objects while shifting the timing by some of the cells until a desired threshold voltage is obtained. The control circuit can select non-overlap or partial overlap of the high voltage pulses for which the timing is shifted. If the non-overlap is selected firstly, it is possible to minimize the peak value of the current consumption accompanying the application of the high voltage pulse. When overlap mode is selected later, the peak value of the current consumption is not increased so much but it is possible to reduce the entire processing time required for lowering the threshold voltage.

Description

Specification

Nonvolatile semiconductor memory and semiconductor device

Technical field

The present invention relates to a nonvolatile semiconductor memory that employs a method of injecting hot holes into a charge storage region to lower the threshold voltage of a nonvolatile memory cell, and a semiconductor device equipped with the nonvolatile semiconductor memory, and is applied to, for example, a flash memory. Related to effective technology.

Background art

[0002] As a technique for injecting (for example, writing) and discharging or neutralizing (for example, erasing) electrons into a charge storage region of a non-volatile memory cell, electrons are generated using a tunnel current all over the gate electrode. There are a method using F—N tunnel current and a method using hot carriers. In the former, it is necessary to increase the operation voltage for the write operation and the erase operation. However, since the operation current can be reduced, the number of memory cells to be subjected to the write operation or the erase operation is large. Often used for sex memory. In the latter case, the write and erase operation voltages can be lowered and the operation can be performed at a high speed. Therefore, a high-speed operation requiring relatively few memory cells for the write or erase operation is required. Often used in non-volatile memory!

[0003] For example, in a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory cell in which a nitride film and a memory gate insulated from each other are formed on a channel formation region, one of the erasures using the hot carrier method is A high electric field is generated from the source / drain electrode end to the memory gate, and the one source / drain electrode force also causes a current to flow through the substrate. As a result, an ionizing collision occurs in the vicinity of the one end of the source and drain electrodes, and electron and hole pairs are generated. Of the generated holes, holes with sufficient energy to exceed the potential barrier of the gate oxide film become hot holes and are injected into the nitride film. When hot holes are injected into the nitride film, they are already injected there and act to neutralize the electrons, thereby lowering the threshold voltage of the memory cell and changing it in the direction. . In this erase by hot hole injection, on the one hand, a current must flow from the source / drain region to the channel formation region. Nonvolatile as a unit of erasure If the number of memory cells increases, a large current must be drawn as a whole, and a power supply circuit or a booster circuit having a large current capacity is required.

[0004] Patent Document 1 describes a general technique in which the write timing is shifted for each memory cell to be written in order to reduce the peak value of current consumption. Patent Document 2 describes a technique for injecting hot holes in an erase operation of a memory cell.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-109894

Patent Document 2: Pamphlet of International Publication No. 02Z19342

Disclosure of the invention

Problems to be solved by the invention

[0006] The inventor studied the nonvolatile semiconductor memory described in Patent Document 1. In the nonvolatile memory described in Patent Document 1, one write operation target is a word line unit, and one erase operation target is a block unit including a plurality of word lines. In terms of the number of memory cells to be written and the number of memory cells to be erased during the erase operation, it can be considered that there are more memory cells to be erased. When the erase operation is performed by hot hole injection, the current that flows in the channel formation region of the memory cell and the current that flows in the channel formation region of the memory cell to perform hot electron injection in the write operation In comparison, it has become clear that the amount of current required for the erase operation is greater than the amount of current required for the write operation.

[0007] On the other hand, the nonvolatile memory described in Patent Document 2 has a constant voltage boost rate change applied to the well region depending on the number of memory cells to be erased during the erase operation. The power that is being considered for devising It has become clear that the amount of current flowing in the channel formation region of the memory cell to be erased has been studied.

[0008] Based on the above examination, the present inventor further divides a block, which is an erasing unit that can be specified by an external force, and performs erasing in units of sectors in units of memory cells connected to one word line. We studied a method to reduce the maximum erase current. In short, the high-voltage erase pulse applied to the one source / drain region is shifted sector by sector. However, the present inventor has revealed that there is a problem that the erase processing time becomes longer by the amount of application of the erase pulse. [0009] An object of the present invention is to provide a nonvolatile semiconductor memory capable of suppressing an increase in the overall processing time as much as possible even when hot hole injection is performed by shifting the application timing of a high voltage pulse to a nonvolatile memory cell. It is to provide.

[0010] The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Means for solving the problem

[0011] The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

[1] In a typical nonvolatile semiconductor memory according to the present invention, the threshold voltage is increased by injection of electrons into the charge storage region, and the threshold voltage is increased by injection of hot holes into the charge storage region. A plurality of non-volatile memory cells (1) to be lowered are provided, and a plurality of non-volatile memory cells selected as hot hole injection targets are shifted in timing one by one to generate a high voltage pulse for hot hole injection. A control circuit (25, 36) capable of repeating the process to be applied in a plurality of times until a desired threshold voltage is reached, and the control circuit performs non-high-speed application of a plurality of high-voltage pulses shifted in timing; A choice between burlap or partial overlap is possible.

[0013] If a plurality of high voltage pulses are non-overlapping, the peak value of the consumption current accompanying the application of the high voltage pulse can be minimized, and if a plurality of high voltage pulses are overlapped, the overlap is achieved. As the degree of! Increases, the peak value of the current consumption increases and the overall processing time for lowering the threshold voltage is shortened.

[0014] The force that the current flowing through one source / drain end of the nonvolatile memory cell contributes to the generation of hot holes. The current decreases as hot holes are injected into the charge storage region. Focusing on this property, when the process of applying a high voltage pulse for hot hole injection is repeated several times until the desired threshold voltage is reached, the latter flows to one source 'drain end compared to the first The current becomes smaller. Therefore, since a large current flows at the end of one source 'drain at first, it is convenient to suppress the current peak by making the high voltage pulse non-overlapping. In the latter case, the current force S flowing through one of the source and drain ends is decreasing, so it is better to partially overlap the high voltage pulse during processing. It is convenient for shortening the interval, and it does not cause the current peak to be excessive.

[0015] From the above, even if hot hole injection is performed by shifting the application timing of the high voltage pulse to the nonvolatile memory cell, it is possible to suppress the increase in the overall processing time as much as possible.

[0016] As a specific form of the present invention, the control circuit can select a degree of partial overlap of the high voltage pulse. In the latter high-voltage pulse application process, the current flowing to one of the source and drain ends becomes smaller. In some cases, it may be desirable to set the pulse application time longer than the first. Become.

[0017] As another specific form of the present invention, the control circuit performs non-overlapping application of a high-voltage pulse that is shifted in timing in the first hot hole injection that is repeated in a plurality of times. In the later hot hole injection, which is repeated several times, the application of high voltage pulses with different timings is partially overlapped. This method is suitable when a control method that focuses on the above properties is adopted in the control circuit.

[0018] As another specific form of the present invention, when the control circuit reduces the threshold voltage of the nonvolatile memory cell, the electric field directed from the channel region to the storage region of the nonvolatile memory cell. Then, hot holes generated at the end of one source / drain electrode (3) are injected into the storage region (6).

[2] A typical semiconductor device (60) according to the present invention includes a nonvolatile semiconductor memory (20), and the nonvolatile semiconductor memory is provided in the source and drain regions (3, 4). An array (21) of nonvolatile memory cells (1) having a charge storage region (6) and a memory gate region (8), which are insulated on the sandwiched channel forming region (2), respectively, and the nonvolatile memory A first wiring (SL) to which one source / drain region (3) of the cell is coupled and a second wiring (BL) to which the other source / drain region (4) of the nonvolatile memory cell is coupled. And a third wiring (MG) to which the memory gate region of the nonvolatile memory cell is coupled, and a control for increasing the threshold voltage by injecting electrons into the charge storage region of the nonvolatile memory cell, and the charge A control circuit (25, 36) that controls the threshold voltage to be lowered by injecting hot holes into the storage region; The control circuit preferably performs a process of applying a high voltage pulse for hot hole injection to a plurality of nonvolatile memory cells selected as hot hole injection targets while shifting the timing thereof part by part. Can be repeated multiple times until the threshold voltage is reached It is possible to select whether a plurality of high voltage pulses with different timings are non-overlapping or partially overlapping.

[0020] In the same manner as described above, it is preferable that the control circuit has a configuration capable of selecting the degree of partial overlap of the high voltage pulse. In the control circuit, in the first hot hole injection that is repeated in a plurality of times, the application of a high voltage pulse with a shifted timing is made non-overlapping, and the latter one that is repeated in a plurality of times is repeated. In hot hole injection, it is recommended to adopt a configuration in which the application of high-voltage pulses with different timing is partially overlapped.

[0021] As one specific form of the present invention, when the threshold voltage of the non-volatile memory cell is lowered, the control circuit generates a force field from the channel region of the non-volatile memory cell to the storage region. In the formed state, hot holes generated at one end of the source / drain electrodes are injected into the storage region.

[0022] At this time, a plurality of nonvolatile memory cells are arranged in a matrix in the array, and the plurality of nonvolatile memory cells arranged in a matrix share the first wiring (SL) in units of rows and are arranged in column units. Share the second wiring (BL) and the third wiring (MG) in units of multiple rows, and the control circuit includes a first high voltage pulse (-5V) on the selected third wiring. Is applied to the first wiring connected to the plurality of nonvolatile memory cells sharing the selected third wiring, and the second high voltage pulse (5 V) is shifted in timing between the first wiring. A configuration in which the voltage is applied may be adopted.

[0023] At this time, the control circuit forms a plurality of selection signals for selecting a plurality of first wirings related to a plurality of rows of nonvolatile memory cells sharing the third wiring. Circuit (50) and a counter control circuit (51) for controlling change timings of the plurality of selection signals, and the counter circuit performs a shift operation in synchronization with a change of a shift clock (SCLK). Storage stages (50A-50D) in series, and the outputs of the plurality of storage stages are the plurality of selection signals,

The counter control circuit includes a pulse generation circuit (56) for generating a pulse (EPLS) to be supplied to the first stage of the counter circuit, and a pulse width selection circuit for selecting a width of a pulse generated by the pulse generation circuit. (55) and the pulse by selecting the shift clock cycle. And a shift amount selection circuit (58) that makes the shift amount of the shift variable. The pulse width and overlap amount of the high voltage pulse can be varied with a relatively simple configuration.

As a more specific form of the present invention, the non-volatile memory cell includes a select gate via an insulating film on the channel formation region on the source / drain region side to which the second wiring is connected. A region (10) is formed and has a split gate structure in which the select gate region and the memory gate region are separated. At this time, the gate breakdown voltage seen from the selection gate region is preferably lower than the gate breakdown voltage seen from the memory gate region. Due to the split gate structure, even if electrons or hot holes are injected into the charge storage region, even if the high voltage is applied to the one source 'drain end!', The channel on the other source 'drain end on the select gate region side This is because it is not necessary to make the select gate region high withstand voltage since a high voltage is not applied through the region. This facilitates increasing the mutual conductance (gm) on the side of the selection gate region when the storage information of the nonvolatile memory cell is also read out.

[0025] As a more specific form of the present invention, a controller (61) for controlling access to the nonvolatile semiconductor memory is further provided, and a gate breakdown voltage viewed from the selection gate region is a gate constituting the controller. It may be the same as the gate breakdown voltage of the insulating field effect transistor.

The invention's effect

[0026] The effects obtained by the representative inventions disclosed in the present application will be briefly described as follows.

That is, even if hot hole injection is performed by shifting the application timing of the high voltage pulse to the nonvolatile memory cell, an increase in the overall processing time can be suppressed as much as possible. Brief Description of Drawings

FIG. 1 is a block diagram illustrating a configuration of a flash memory.

FIG. 2 is a longitudinal sectional view illustrating a longitudinal sectional structure of a split gate type nonvolatile memory cell as a state where many electrons are accumulated in a charge accumulation region.

[Figure 3] Non-volatile as the number of trapped electrons in the charge storage region is smaller than in Figure 2 It is the longitudinal cross-sectional view which illustrated the longitudinal cross-section structure of the memory cell.

[Fig. 4] A characteristic diagram showing the relationship between the time and erase current when hot holes are gradually injected into the nonvolatile memory cell in which many electrons are injected as shown in FIG. It is.

[Fig. 5] Relationship between erase current and time when erasing is started from the state where the threshold voltage of the nonvolatile memory cell has decreased to some extent (the state where the number of electrons accumulated in the charge storage region is small). FIG.

FIG. 6 is a circuit diagram showing a detailed example of a memory array and a write / erase decoder.

FIG. 7 is a logic circuit diagram showing a specific example of a selection timing control circuit (TCNT).

FIG. 8 is a timing chart showing the waveform of the selection signal countO-count3 when the pulse width PW1 of the erase pulse EPLS is set to one cycle of the shift clock SCLK.

FIG. 9 is a timing chart showing the waveform of the selection signal countO-count3 when the pulse width PW2 of the erase pulse EPLS is set to four periods of the shift clock SCLK.

10 is a timing chart of the erase operation when the erase pulse width and the erase pulse shift amount are made equal in the erase block EBLK0 having the circuit configuration of FIG.

FIG. 11 is a timing chart of the erase operation when the erase pulse width is longer than the erase pulse shift amount in the erase block EBLK0 having the circuit configuration of FIG.

FIG. 12 is a flowchart showing an example of an erasing flow.

FIG. 13 is a block diagram showing the overall configuration of a microcomputer with on-chip flash memory.

Explanation of symbols

1 Nonvolatile memory cell

2 channel formation region

3 One source 'drain region (source)

4 The other source 'drain region (drain)

6 Charge storage area

8 Memory gate

10 selection gate 20 Flash memory

21 Memory array

CG selection gate line

MG memory gate line

SL source line

BL bit line

24 selection gate driver

25 Program / erase decoder

27 Driver circuit

MMOO— MMxy nonvolatile memory sensing

CGO-CGy selection gate line

SLO—SLy source line

BLO— BL PI Line

47 Selection timing control circuit (TCNT) countO— count3 selection signal

50 Counter circuit (COUNT)

51 Counter control circuit (CUCNT)

SCLK shift clock

50A—50D. Open flip-flop (FF)

52 Oscillator (OSC)

53 Divider (DIV)

54 Erase pulse width selector signal

55 Erase Nose Width Selector (EPWS)

EPLS Erase Panores

56 Pulse generation circuit (PGEN)

57 Erase pulse shift amount selector signal

58 Erase No-less Shift Amount Selector (EPSS)

60 Microcomputer 61 CPU

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2 illustrates a vertical cross-sectional structure of a split gate nonvolatile memory cell. The nonvolatile memory cell 1 has a channel formation region 2 in a p-type well region 16 provided on a silicon substrate, and a pair of source and drain regions 3 and 4 are formed with the channel formation region 2 interposed therebetween. For convenience, one is referred to as source 3 and the other as drain 4. The source / drain regions 3 and 4 are constituted by n-type diffusion layers (n-type impurity regions). A charge storage region (for example, a silicon nitride film) 6, an insulating film 7 and a memory gate (for example, an n-type polysilicon layer) 8 are arranged on the channel forming region 2 via a gate oxide film 5 near the source 3. Is done. A selection gate (for example, an n-type polysilicon layer) 10 is formed on the channel formation region 2 near the drain 4 via a gate oxide film 9. The charge storage region 6, the memory gate 8 and the selection gate 10 are insulated from each other by an insulating film 11. For convenience, the vicinity of the channel formation region 2 near the source 3, the charge storage region 6 and the memory gate 8 is referred to as a memory transistor portion, and the vicinity of the channel formation region 2 near the drain 4 and the selection gate 10 is referred to as a selection transistor portion.

[0031] A layer that combines the charge storage region 6 and the insulating film 5 and the insulating film 7 disposed on the front and back sides thereof.

The thickness of the insulating film 11 (referred to as the memory gate insulating layer) is tm, the thickness of the gate insulating film 9 of the selection gate 10 is tc, and the thickness of the insulating film 11 between the selection gate 10 and the memory gate 8 is ti. The relationship tc <tm≤ti is realized. Due to the difference in film thickness (layer thickness), the gate withstand voltage of the select transistor portion is made lower than the gate withstand voltage of the memory transistor portion. Note that drain 4 assigned for convenience in the source / drain region means that it functions as the drain electrode of the MOS transistor in the data read operation, and source 3 means that it functions as the source electrode of the MOS transistor in the data read operation. To do. In the erase / write operation, drain 4 and source 3 do not always function exactly as they are named, and vice versa.

[0032] The threshold voltage of the nonvolatile memory cell is increased by injection of electrons into the charge storage region 6 (for example, referred to as writing), and threshold voltage is increased by injection of hot holes into the charge storage region 6 (for example, referred to as erasing). Is lowered. In the write operation, for example, the memory gate 8 voltage (Vmg) is 8V, the source 3 voltage (Vs) is 5V, and the selection gate 10 The voltage (Vcg) of the memory cell is 1.8 V, the voltage (Vd) of the drain 4 of the write selected memory cell is OV (the ground potential of the circuit), and the voltage (Vd) of the drain 4 of the memory cell not selected is 1.8 V As a result, a current flows from the source 3 to the drain 4, and a high electric field is formed in a portion of the channel region 2 immediately below the insulating layer 11. Hot electrons generated thereby are injected into the charge storage region 6.

[0033] In the erase operation, as shown in FIG. 2, Vmg = —5V, Vs = 5V, the substrate is set to OV, an end force of the source 3 and a high electric field is formed on the memory gate 8, and the source Current is passed from 3 to the substrate. As a result, an ionizing collision occurs near the end of the source 3 to generate electron and hole pairs. Of the generated holes, holes with sufficient energy to exceed the potential barrier of the gate oxide film 5 become hot holes and are injected into the charge storage region 6. When hot holes are injected into the charge storage region 6, they act in the direction of neutralizing the electrons that have already been injected therein, and this causes the threshold voltage of the nonvolatile memory cell 1 to decrease and change in the direction. It is.

In the above write and erase operations on the nonvolatile memory cell 1, it is not necessary to apply a high voltage to the selection gate 10 and the drain. This means that the gate voltage of the select transistor is relatively low!ヽ Guarantee that.

In FIG. 2, 12-14 are equipotential lines near the source at the time of erasing. The equipotential line 12 is, for example, 3V, the equipotential line 13 is, for example, IV, and the equipotential line 14 is, for example, OV. The state shown in FIG. 2 is a state in which a large amount of electrons are accumulated in the charge accumulation region 6 and is a state immediately after the start of the erasing operation. Since the electrons are captured, it acts to strengthen the electric field between the source end portion 15 and the potential of the portion 15 is lowered, so that the equipotential lines become dense, in other words, the voltage of the portion 15 The slope of the descent is relatively large, as indicated by the large arrow, from the source 3 to the p-type wel region 16.

[0036] FIG. 3 shows that erasing has progressed from a state where the threshold voltage of the nonvolatile memory cell 1 has decreased to some extent (that is, a state in which the number of trapped electrons in the charge storage region 6 has decreased to some extent). Indicates when to do. The influence of the electrons accumulated in the charge accumulation region 6 is small, and the potential of the substrate immediately below the charge accumulation region 6 is higher than that in FIG. Therefore, close to the source end 15 In the vicinity, the interval between equipotential lines 12-14 is wider than in Fig. 2. In other words, in the vicinity of the source end portion 15, the slope of the voltage drop becomes small, and the current flowing from the source 3 to the p-type well region 16 is less than J / J from FIG.

[0037] FIG. 4 shows the relationship between time and erase current when hot holes are gradually injected into the nonvolatile memory cell 1 in which many electrons are injected as shown in FIG. Indicates. In this case, the peak current is large. In addition, as the erasing progresses with time, the erasing current gradually decreases. On the other hand, FIG. 5 shows the case where erasing has progressed and the threshold voltage of the nonvolatile memory cell 1 is low to some extent, and erasing is started from the state (that is, the state where the electrons accumulated in the charge storage region 6 are few). The relationship between time and erase current is shown. Since the effect of electrons stored in the charge storage region 6 is small, the peak current is smaller than in FIG. As the erasure progresses over time, the erase current gradually decreases as in Fig. 4.

FIG. 1 illustrates the configuration of the flash memory. The flash memory 20 has a memory array (ARY) 21 in which a plurality of nonvolatile memory cells 1 of FIG. Figure 2 shows two representatives. Multiple non-volatile memory cells 1 arranged in a matrix have selection gate 10 connected to selection gate line CG, memory gate 8 connected to memory gate line MG, source 3 connected to source line SL, and drain 4 connected to bit line BL. Is done. The X address decoder (XDEC) 22 decodes the X address signal input to the address buffer (ADB) 23. The selection gate driver circuit (CGDRV) 24 selectively drives the selection gate line CG according to the decoding result. In the read operation and the verify operation, the nonvolatile memory cell 1 is selected by selective driving with respect to the selection gate line CG. A write / erase decoder (PEDEC) 25 selects a memory gate line MG and a source line SL in writing and erasing. For the selection during the write operation, the decoding result by the X address decoder 22 is used via the selection gate line CG. The selection at the time of erase operation is performed based on the instruction information of the erase block to be erased. The driver circuit (PEDRV) 27 drives the memory gate line MG and the source line SL based on the selection signal output from the write / erase decoder 25.

A sense latch (SL) and a data register circuit (DREG) 30 are connected to the bit line BL. The sense latch (SL) detects and holds the storage information read from the nonvolatile memory cell 1 to the bit line BL. Data register (DREG) is externally supplied write data Is used for holding memory cell memory information to be saved before erasing and erasing, and the held data is used for controlling the bit line BL level in the write operation. The sense latch and data register circuit 30 is connected to a data input / output buffer (DTB) 32 via a Y selection circuit (YG) 31, and can interface with a data bus 33D included in an external bus 33. In the read operation, the Y selection circuit 31 selects the read data latched in the sense latch (SL) according to the address decode signal output from the Y address decoder (YDEC) 34. The selected read data can be output to the outside via the data input / output buffer 32. In the write operation, the Y address decoder 34 controls which bit line BL the write data supplied from the data input / output buffer 32 is to be latched in the data register (DREG).

The address signal is supplied from the address bus 33 A of the external bus to the address buffer 23, and is supplied from the address buffer 23 to the X address decoder 22 and the Y address decoder 34. The booster circuit (VPG) 35 generates the high voltages VPP1, VPP2,..., VPPi such as 5V, −5V, 8V, etc. necessary for reading, erasing and writing based on the external power sources Vdd and Vss.

A control circuit (CONT) 36 performs a control sequence of a read operation, an erase operation, a write operation, and a switching control of an operation power source according to control information set in a control register (CREG) 37. The operation power supply switching control is control that appropriately switches the operation power supply of the driver circuits 24 and 27 according to the operation mode in accordance with the read operation, the erase operation, and the write operation.

FIG. 6 shows a detailed example of the memory array and the write / erase decoder. In the figure, the memory array includes a plurality of nonvolatile memory cells MMOO-MMxy arranged in a matrix. Nonvolatile memory cell MMOO—MMxy has the same device structure as the nonvolatile memory cell 1 described above. Non-volatile memory cell MMOO— MMxy selection gate 1 0 is connected to the corresponding selection gate line CGO—CGy in row units, and nonvolatile memory cell M MOO—MMxy source 3 is the source line corresponding to row units SLO—SLy The drain 4 of the nonvolatile memory cell MMOO—MMxy is connected to the corresponding bit line BLO—B Lx in a column unit. One row of nonvolatile memory cells is called a sector. Non-volatile memory cell MMOO — For MMxy, erasing with non-volatile memory cells of 4 sectors as the erasing unit A block and an erase block having a non-volatile memory cell for one sector as an erasing unit are allocated, and the memory gate 8 of the non-volatile memory cell is commonly connected to the memory gate line MG in an erasing block unit. The erase block EBLKO for four sectors, which is representatively shown in FIG. 6, is commonly connected to the memory gate line MGO, and the erase block EBLKm for one sector is commonly connected to the memory gate line MGm.

The driver circuit (PEDRV) 27 has an output inverter 40 and a level conversion circuit (LVSFT) 41 corresponding to each source line SLO—SLy and memory gate line MGO—MGm. The output power of the output inverter 40 is switched according to the operation mode of erasing, writing, and reading. The level conversion circuit (LVSFT) 41 converts the input signal having the preceding stage power into a signal level corresponding to the operating power supply of the output inverter 40. The driver circuit (PEDRV) 27 uses a high voltage MOS transistor in relation to its operating power supply.

The write / erase decoder (PEDEC) 25 includes an output inverter 42 whose output is coupled to the level conversion circuit 41, a selector 46 that also includes three NAND gates (NAND) 43-45, and a selection timing control circuit. (TCNT) 47 and decode logic (DECLCG) 48. mgselO—mgselm is a selection signal for the memory gate line MGO—MGm, and the corresponding one is set to the selection level based on the selection signal transmitted via the selection gate line CGO—CGy. prog is the instruction signal for the write operation, and slselO— slsely is the source line SL0—SLy selection signal for the write operation. In the write operation, the corresponding source line is set to the selection level based on the selection signal transmitted through the selection gate lines CG0-CGy, and the write operation can be performed on a sector basis.

“Erase” is an erase operation instruction signal, and “eraseblockO—eraseblockm” is a selection signal for the erase block EBL K0—EBLKm. Erase block selection signal eraseblockO—erasebloc km is set to the selection level according to the erase block designation information supplied from CREG37 to DECLCG48. countO—count3 is a selection signal for source lines SL4i, SL4i + 1, SL4i + 2, and SL4i + 3 (i = 0–n) in the erase block during the erase operation.

[0046] For example, in the erase operation, the memory gate control line selection signal mgselO is set to high level (H), the memory gate line MG0 is set to -5V, the erase block selection signal eraseblockO is set to high level (H), and the erase operation instruction signal When erase is at high level (H), the source line selection signal in the erase block When the signal countO is set to the high level (H), the memory gate line MG0 of the memory array 21 is set to −5V and the source line SLO is set to 5V as illustrated in FIG. Memory cell MMOO—Erasing pulse is applied to MMxO. The sector to which the erase pulse is applied is sequentially switched to SCT0, SCT1, SCT2, and SCT3 as the selection signal power ^s countO, count 1, count2, and count3 are sequentially activated. In this way, it is possible to apply the high voltage noise for hot hole injection by shifting the timing in units of sectors in the erase block.

FIG. 7 shows a specific example of the selection timing control circuit (TCNT) 47. The selection timing control circuit 47 includes a counter circuit (COUNT) 50 that forms the selection signal countO-count3, and a counter control circuit (CUCNT) 51 that controls change timings of the plurality of selection signals countO-count3. The counter circuit 50 includes a plurality of storage stages, for example, D-type flip-flops (FF) 50A and 50D, which perform a shift operation in synchronization with the change of the shift clock SCLK, and outputs the plurality of flip-flops 50A-50D. Is the plurality of selection signals countO-count3.

[0048] The counter control circuit 51 is output from an oscillator (OSC) 52, a frequency divider (DIV) 53 that divides the output of the oscillator 52 to form a plurality of frequency-divided clock signals, and a frequency divider circuit. An erase pulse width selector (EPWS) 55 that selects one of a plurality of divided clock signals by an erase pulse width selector signal 54 and a divided clock signal selected by the erase pulse width selector 55 Erase one of the pulse generator circuit (PGEN) 56 for generating the erase pulse EPLS supplied to the first stage flip-flop 50A of the counter circuit 50 and the plurality of divided clock signals output from the divider circuit 53 It comprises an erase pulse shift amount selector (EPSS) 58 that is selected by a pulse shift amount selector signal 57 and selects the period of the shift clock SCLK.

FIGS. 8 and 9 illustrate waveforms of the selection signal countO-count3 formed according to the period of the shift clock SCLK and the pulse width of the erase pulse EPLS. In each figure, the erase pulse shift amount SFT is one cycle of the shift clock SCLK. To change the shift amount SFT, the shift clock cycle can be changed. In FIG. 8, the pulse width PW1 of the erase pulse EPLS is one period of the shift clock SCLK. As a result, the selection signal countO One count3 is sequentially pulse-changed with non-overlap. In Fig. 9, the pulse width PW2 of the erase pulse EPL S is four periods of the shift clock SCLK. As a result, the selection signal count0-count3 is sequentially pulse-changed by four periods of the shift clock SCLK with an overlap shifted by one period of the shift clock SCLK.

[0050] As described above, depending on the erase pulse width selected by the erase pulse width selector 55 and the erase pulse shift amount selected by the erase pulse shift amount selector 58, the selection signal countO and count3 are set to non-overlap or overlap. Along with the selection of whether or not, the overlap amount can be variably selected.

FIGS. 10 and 11 show timing charts of the erase operation in the erase block EBLK0 having the circuit configuration of FIG. In order to erase the non-volatile memory cells MM00, MMxO, MM01, MMxl, MM02, MMx2, MM03, MMx3 in the erase block EBLK0, for example, OV is applied to the selection gate lines CG0, CG1, CG2, CG3, and bit lines BL0, Set BLx to open, for example. Next, the erase signal erase is set to high level (H), and then the selection signal eraseblockO is set to high level (H) to select the erase block EBLK0. Next, the selection signal mgselO is set to high level (H), and 5 V, for example, is applied to the memory gate line MG0. After that, the signal countO is set to high level (H) and 5V is applied to the source line SL0 to erase the nonvolatile memory cell in the erase sector SCT0. After a certain time, the signal countO is set to the low level (and the voltage of the source line SL0 is set to 0V. Next, the signal countl is set to the noise level (H), for example, 5V is applied to the source line SL1, and the non-volatile memory of the erase sector SCT1 Erasing the cells, similarly, changing the pulses of the signals count2 and count3, and sequentially erasing the non-volatile memory cells in the erase sector SCT2 and erase sector SCT3, the time of the signal countO-count3's noise level (H) period The erase pulse width, the time difference between the rise of the signal counti and the rise of the next signal counti + 1 signal, for example, the time difference between the rise time of countO and the rise time of counti is defined as the erase pulse shift amount. The sum of the erase currents flowing through SL1, SL2, SL 3, and Sly is defined as the total source current.

FIG. 10 shows a timing chart when the erase pulse width is equal to the erase pulse shift amount. In this case, the period during which the source lines SL0, SL1, SL2, and SL3 are 5V, that is, the selection periods do not overlap. Therefore, as shown in the figure, the peak current of the total source current and each The peak current of the source line is U, etc.

FIG. 11 shows a timing chart in the case where the erase pulse width is longer than the erase nors shift amount. In this case, there are overlapping periods among the selection periods of the source lines SLO, SL1, SL2, and SL3. Therefore, the peak current of the total source current becomes the largest during the period when all the source lines SLO, SL1, SL2, and SL3 are selected. However, since the selection period of the source lines SLO, SL1, SL2, and SL3 is overlapped, the erase time can be shortened. In FIG. 11, the force in which the ratio between the erase pulse width and the erase pulse shift amount is 4: 1 is not limited to this.

FIG. 12 shows an example of the erasing flow. In this erase flow, the first erase is performed using the timing chart of FIG. 10, that is, the erase pulse width and erase pulse shift amount are set equal (SI, S2). Next, it is verified whether all the areas to be erased have been erased (S3). If the erasure has not been completed, the second erasure is performed according to the timing chart of FIG. 11, that is, the erase pulse width is set longer than the erase pulse shift amount (S4, S5). Next, the power that erased all the areas to be erased is verified (S6). The third and subsequent times are the same as the second time.

[0055] In the first erasing of steps SI and S2, many electrons are injected into the charge storage region 6 as shown in FIG. Therefore, since a large current flows from the source 3 to the substrate 16 in the erase operation, the timing chart of FIG. 10 is applied to suppress the peak current of the total source current. By suppressing the peak current of the total source current, the current supply capability of the power supply circuit 35 that supplies the source current can be suppressed. Since the current supply capability of the power supply circuit that supplies the source current can be suppressed, the area of the power supply circuit can be reduced, contributing to the miniaturization of the chip.

In the second and subsequent erasures, the number of electrons held in the charge storage region 6 is decreasing as shown in FIG. Therefore, since the current flowing from the source 3 to the substrate 16 is small, the peak current of the total source current can be suppressed even when the timing chart of FIG. 11 is applied. Furthermore, since the source line selection timing (erase pulse application timing) is overlapped, the erase time can be shortened.

FIG. 13 shows the overall configuration of a microcomputer on-chip of the flash memory 20. The microcomputer 60 is not particularly limited, but is made of single crystal silicon. It is formed on such a single semiconductor substrate (semiconductor chip) by CMOS integrated circuit manufacturing technology. The microcomputer 60 includes a central processing unit (CPU) 61, a RAM 62 as a volatile memory, a flash memory (FLASH) 20 as a non-volatile memory, a nos state controller (BSC) 63, and an input / output port circuit. An input / output circuit (IZO) 64 is provided, and these circuit modules are connected to an internal bus 66. The internal bus 66 includes address, data, and control signal lines. The CPU 61 includes an instruction control unit and an execution unit, decodes the footed instruction, and performs arithmetic processing according to the decoding result. The flash memory 20 stores the CPU 61 operation program and data. The RAM 62 is used as a work area or a data storage area for the CPU 61. The operation of the flash memory 20 is controlled based on the control data set in the control register 37 by the CPU 61. The bus state controller 63 controls access via the internal bus 66, the number of access cycles for external node access, wait state insertion, bus width, and the like.

In FIG. 13, a circuit other than the region 69 surrounded by a two-dot chain line means a circuit portion constituted by a MOS transistor having a relatively thin gate oxide film. The circuit in region 69 is a circuit portion constituted by a high-voltage MOS transistor having a comparatively thick gate oxide film. For example, in the flash memory 20, the area where PEDRV27 etc. is formed is the high voltage MOS transistor circuit part, and in the flash memory 20, the area where CGDRV24 etc. is formed is the MOS transistor circuit part where the gate oxide film is thin It is said.

[0059] While the invention made by the present inventor has been specifically described based on the embodiments, it goes without saying that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. .

For example, in FIG. 7, the erase panoramic shift amount is set to one cycle of the shift clock SCLK, but is not limited to one cycle. In this case, add a flip-flop in front of flip-flop 50Α in Figure 7, or insert another flip-flop between each of flip-flops 50 において -50D.

In the erase flow of FIG. 12, the erase panorace width and the erase panorace shift amount are set equal only for the first erase, but such setting is not limited to the first. Erasing is performed several times with the erase pulse width and erase norse shift amount set equal to each other. The remaining pulse width may be set longer than the erase pulse shift amount. Further, the erase pulse width, erase pulse shift amount, memory gate voltage, and source voltage may be arbitrarily changed according to the number of times of erasure.

[0062] Further, the nonvolatile memory cell is not limited to the split gate structure. In addition, the charge storage region is not limited to an insulating trap region such as silicon nitride, but may be a floating nonvolatile memory cell having a conductive charge storage region such as polysilicon. .

Industrial applicability

[0063] The present invention can be widely applied to a flash memory and a microcomputer equipped with the flash memory.

Claims

The scope of the claims

[1] comprising a plurality of nonvolatile memory cells whose threshold voltage is increased by injection of electrons into the charge storage region and whose threshold voltage is decreased by injection of hot holes into the charge storage region;

The process of applying a high voltage pulse for hot hole injection to a plurality of nonvolatile memory cells selected as the hot hole injection target is shifted several times until a desired threshold voltage is reached. Has a control circuit that can be divided into

The control circuit is a non-volatile semiconductor memory capable of selecting whether the plurality of high voltage pulses with shifted timings are non-overlapping or partially overlapping.

2. The nonvolatile semiconductor memory according to claim 1, wherein the control circuit is capable of selecting a degree of partial overlap of the high voltage pulse.

[3] In the first hot hole injection that is repeated in a plurality of times, the control circuit sets a non-overlapping application of a high-voltage pulse that is shifted in timing, and is repeated after a plurality of times. 2. The nonvolatile semiconductor memory according to claim 1, wherein in the hot hole injection, the application of a high voltage pulse with a shifted timing is partially overlapped.

[4] When the threshold voltage of the non-volatile memory cell is lowered, the control circuit forms an electric field that is directed from the channel region of the non-volatile memory cell to the storage region, and at one end of the source drain electrode. 2. The nonvolatile semiconductor memory according to claim 1, wherein hot holes generated are injected into the storage region.

[5] A semiconductor device having a nonvolatile semiconductor memory,

The nonvolatile semiconductor memory includes an array of nonvolatile memory cells each having a charge storage region and a memory gate region insulated on a channel formation region sandwiched between source / drain regions, and

A first wiring coupled to one source / drain region of the nonvolatile memory cell; a second wiring coupled to the other source / drain region of the nonvolatile memory cell; and a memory gate of the nonvolatile memory cell. A third wire with a combined region; A control circuit that performs control to inject electrons into the charge storage region of the nonvolatile memory cell to increase the threshold voltage, and controls to inject hot holes into the charge storage region to lower the threshold voltage; With

The control circuit performs a process of applying a high voltage pulse for hot hole injection to a plurality of nonvolatile memory cells selected as the hot hole injection target by shifting a timing at a desired threshold voltage. It is possible to repeat a plurality of times until it reaches the end, and it is possible to select whether the plurality of high-voltage pulses with shifted timings are non-overlapping or partially overlapping Semiconductor device.

6. The semiconductor device according to claim 5, wherein the control circuit is capable of selecting a degree of partial overlap of the high voltage pulse.

[7] In the first hot hole injection that is repeated in a plurality of times, the control circuit sets a non-overlapping application of a high voltage pulse with a shifted timing, and then repeats a plurality of times. 6. The semiconductor device according to claim 5, wherein in the hot hole injection, the application of a high voltage pulse with a shifted timing is partially overlapped.

[8] When the threshold voltage of the non-volatile memory cell is lowered, the control circuit forms an electric field that is directed from the channel region of the non-volatile memory cell to the storage region, and at one end of the source drain electrode. 6. The semiconductor device according to claim 5, wherein hot holes that are generated are injected into the storage region.

[9] A plurality of nonvolatile memory cells are arranged in a matrix in the array,

Multiple non-volatile memory cells arranged in a matrix share the first wiring in rows, share the second wiring in columns, share the third wiring in rows,

The control circuit applies a first high voltage pulse to the selected third wiring, and the first wiring is connected to the first wiring connected to the plurality of nonvolatile memory cells sharing the selected third wiring. 6. The semiconductor device according to claim 5, wherein the second high voltage pulse is applied while shifting the timing between the wirings.

[10] The control circuit includes: a counter circuit that forms a plurality of selection signals for selecting a plurality of first wirings related to a plurality of rows of nonvolatile memory cells sharing the third wiring; And a counter control circuit for controlling the change timing of the selection signal of The counter circuit includes a plurality of storage stages that perform a shift operation in synchronization with a change of a shift clock in series, and outputs of the plurality of storage stages serve as the plurality of selection signals. The counter control circuit includes: A pulse generation circuit that generates a pulse to be supplied to the first stage of the counter circuit; a pulse width selection circuit that enables selection of a pulse width generated by the pulse generation circuit; and a shift amount of the pulse by selecting a period of the shift clock. 10. A semiconductor device according to claim 9, further comprising a shift amount selection circuit that makes the variable variable.

[11] In the nonvolatile memory cell, a selection gate region is formed on the channel formation region on the source / drain region side to which the second wiring is connected via an insulating film, and the selection gate region and the memory gate 10. The semiconductor device according to claim 9, wherein the semiconductor device has a split gate structure in which regions are separated.

12. The semiconductor device according to claim 11, wherein the gate breakdown voltage seen from the selection gate region force is lower than the gate breakdown voltage seen from the memory gate region force.

[13] The apparatus further includes a controller that controls access to the nonvolatile semiconductor memory, and the gate breakdown voltage in terms of the selective gate region force is the same as the gate breakdown voltage of the gate insulating field effect transistor that constitutes the controller. Item 13. A semiconductor device according to Item 12.