WO2006097858A3 - Low-dielectric constant cryptocrystal layers and nanostructures - Google Patents

Low-dielectric constant cryptocrystal layers and nanostructures Download PDF

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Publication number
WO2006097858A3
WO2006097858A3 PCT/IB2006/050406 IB2006050406W WO2006097858A3 WO 2006097858 A3 WO2006097858 A3 WO 2006097858A3 IB 2006050406 W IB2006050406 W IB 2006050406W WO 2006097858 A3 WO2006097858 A3 WO 2006097858A3
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WO
WIPO (PCT)
Prior art keywords
producing
cryptocrystal
cryptocrystals
nano
low
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PCT/IB2006/050406
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French (fr)
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WO2006097858A2 (en
Inventor
Seref Kalem
Original Assignee
Tubitak
Seref Kalem
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tubitak, Seref Kalem filed Critical Tubitak
Priority to US11/908,778 priority Critical patent/US20080191218A1/en
Priority to KR1020077023517A priority patent/KR20070112410A/en
Priority to CN2006800170631A priority patent/CN101176189B/en
Priority to CA2602365A priority patent/CA2602365C/en
Priority to EA200701725A priority patent/EA013649B1/en
Priority to EP06710851.4A priority patent/EP1878043B1/en
Priority to JP2008501454A priority patent/JP5112289B2/en
Publication of WO2006097858A2 publication Critical patent/WO2006097858A2/en
Publication of WO2006097858A3 publication Critical patent/WO2006097858A3/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Abstract

This invention provides a method for producing application quality low-dielectric constant (low-k) cryptocrystal layers on state-of-the-art semiconductor wafers and for producing organized Nanostructures from cryptocrystals and relates to optical and electronic devices that can be obtained from these materials. The results disclosed here indicate that modification of structure and chemical composition of single crystal matrix using chemical vapor processing (CVP) results in high quality cryptocrystal layers that are homogeneous and form a smooth interface with semiconductor wafer. With this method, growth rates as high as 1 μm/hour can be realized for the dielectric cryptocrystal layer formation. The present invention also provides a method for producing Micro- and Nano-wires by transforming cryptocrystals to organized systems. With this method, Nano wires having dimensions ranging from few nanometers up to 1000 nanometer and lengths up to 50 micrometer can be produced. The cryptocrystals, nanowires and organized structures may be used in future interconnections as interlevel and intermetal di- electrics, in producing ultra high density memory cells, in information security as key generators, in producing photonic componenst, in fabrication of cooling channnels in advanced micro- and nano-electronics packaging and sensors.
PCT/IB2006/050406 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures WO2006097858A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US11/908,778 US20080191218A1 (en) 2005-03-16 2006-02-08 Low-Dielectric Constant Cryptocrystal Layers And Nanostructures
KR1020077023517A KR20070112410A (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures
CN2006800170631A CN101176189B (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures
CA2602365A CA2602365C (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures
EA200701725A EA013649B1 (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures for use in high tech technologies
EP06710851.4A EP1878043B1 (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures
JP2008501454A JP5112289B2 (en) 2005-03-16 2006-02-08 Wafer bonding method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TR2005/00923A TR200500923A2 (en) 2005-03-16 2005-03-16 Small Dielectric Constant K for Advanced Technology Applications
TR2005/00923 2005-03-16

Publications (2)

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WO2006097858A2 WO2006097858A2 (en) 2006-09-21
WO2006097858A3 true WO2006097858A3 (en) 2007-07-19

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PCT/IB2006/050406 WO2006097858A2 (en) 2005-03-16 2006-02-08 Low-dielectric constant cryptocrystal layers and nanostructures

Country Status (9)

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US (1) US20080191218A1 (en)
EP (1) EP1878043B1 (en)
JP (1) JP5112289B2 (en)
KR (1) KR20070112410A (en)
CN (1) CN101176189B (en)
CA (1) CA2602365C (en)
EA (1) EA013649B1 (en)
TR (1) TR200500923A2 (en)
WO (1) WO2006097858A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007197302A (en) * 2005-12-28 2007-08-09 Sumitomo Electric Ind Ltd Fabrication method and fabrication apparatus of group iii nitride crystal
WO2011123115A1 (en) * 2010-03-31 2011-10-06 Hewlett-Packard Development Company, L.P. Nanoscale switching device
CN102184873B (en) * 2011-04-21 2012-10-10 北京科技大学 Method for quickly preparing diamond-silicon carbide electronic packaging material
EP2845273B1 (en) 2012-04-30 2016-06-08 Tubitak Methods for producing new silicon light source and devices
DE102017109423A1 (en) * 2017-05-03 2018-11-08 Osram Gmbh Encryption of beacons
US11605760B2 (en) * 2018-05-21 2023-03-14 Intel Corporation Micro light-emitting diode displays having nanophosphors
US11605668B2 (en) * 2018-05-21 2023-03-14 Intel Corporation Pixel architectures for low power micro light-emitting diode displays
CN109813760A (en) * 2019-02-28 2019-05-28 江苏理工学院 A kind of zinc oxide nanowire gas sensor and preparation method thereof
KR102581119B1 (en) 2020-06-16 2023-09-20 고려대학교 세종산학협력단 Germanium-Phosphide Nanosheets and Preparation Method Thereof
KR102602180B1 (en) 2020-08-07 2023-11-13 고려대학교 세종산학협력단 Silicon-Arsenide Nanosheets and Preparation Method Thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410614A (en) * 1987-07-03 1989-01-13 Fujitsu Ltd Bonding of flat boards

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1955821A (en) * 1929-06-14 1934-04-24 Ac Spark Plug Co Ceramic process
JP2766992B2 (en) * 1989-07-14 1998-06-18 富士通株式会社 Method for manufacturing semiconductor device
EP0473509A3 (en) * 1990-08-29 1992-03-18 Rhone-Poulenc Chimie Method for preparation of zeolites based on silica and, possibly, oxides of tetravalent elements
JPH07283381A (en) * 1994-04-08 1995-10-27 Canon Inc Manufacture of pasted semiconductor base body
US5470802A (en) * 1994-05-20 1995-11-28 Texas Instruments Incorporated Method of making a semiconductor device using a low dielectric constant material
JP3753805B2 (en) * 1996-09-19 2006-03-08 株式会社東芝 Semiconductor sample decomposition apparatus and sample decomposition method
JPH10158010A (en) * 1996-11-26 1998-06-16 Matsushita Electric Works Ltd Production of silicon dioxide coating film
US6468927B1 (en) * 2000-05-19 2002-10-22 Applied Materials, Inc. Method of depositing a nitrogen-doped FSG layer
JP2002039927A (en) * 2000-07-19 2002-02-06 Toshiba Ceramics Co Ltd Partial analysis method for surface layer of silicon wafer
JP2004123484A (en) * 2002-10-04 2004-04-22 Crystal System:Kk Metal oxide film and its use
JP4310415B2 (en) * 2003-04-28 2009-08-12 財団法人新産業創造研究機構 Micro patterning method by liquid phase deposition
US7279369B2 (en) * 2003-08-21 2007-10-09 Intel Corporation Germanium on insulator fabrication via epitaxial germanium bonding

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410614A (en) * 1987-07-03 1989-01-13 Fujitsu Ltd Bonding of flat boards

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
ASTROVA E V ET AL: "EFFECT OF CHEMICAL SURFACE TREATMENT ON P-LAYER FORMATION IN THE INTERFACE REGION OF DIRECTLY BONDED SI WAFERS", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, IOP, BRISTOL, GB, vol. 8, no. 9, 1 September 1993 (1993-09-01), pages 1700 - 1705, XP000417397, ISSN: 0268-1242 *
FUJIMO S ET AL: "SILICON WAFER DIRECT BONDING THROUGH THE AMORPHOUS LAYER", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO, JP, vol. 34, no. 10B, PART 2, 15 October 1995 (1995-10-15), pages L1322 - L1324, XP000702224, ISSN: 0021-4922 *
M. SAADOUN: "Vapour-etching-based porous silicon: a new approach.", THIN SOLID FILMS, vol. 405, no. 1-2, 22 February 2002 (2002-02-22), pages 29 - 34, XP002409942 *
R. W. FATHAUER ET AL.: "Visible luminescence from silicon wafers subjected to stain etches", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 60, no. 8, 24 February 1992 (1992-02-24), pages 995 - 997, XP000292204, ISSN: 0003-6951 *
S. KALEM ET AL.: "Possibility of fabricating light-emitting porous silicon from gas phase etchants", OPTICS EXPRESS, vol. 6, no. 1, 3 January 2000 (2000-01-03), pages 7 - 11, XP002409773 *
S. KALEM: "Possible low-k solution and other potential applications", 12 August 2004 (2004-08-12), XP002409771, Retrieved from the Internet <URL:http://www.eurosemi.eu.com/eurosemi2004/front-end/printer-friendly.php?newsid=5492> [retrieved on 20061127] *
S. KALEM: "Synthesis of ammonium silicon fluoride cryptocrystals on silicon by dry etching", APPLIED SURFACE SCIENCE, vol. 236, no. 1-4, 15 September 2004 (2004-09-15), NL, pages 336 - 341, XP002409772 *

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Publication number Publication date
JP2008537844A (en) 2008-09-25
CN101176189A (en) 2008-05-07
CA2602365C (en) 2017-05-09
EP1878043B1 (en) 2021-11-03
CN101176189B (en) 2011-05-11
EP1878043A2 (en) 2008-01-16
US20080191218A1 (en) 2008-08-14
CA2602365A1 (en) 2006-09-21
EA200701725A1 (en) 2008-08-29
EA013649B1 (en) 2010-06-30
TR200500923A2 (en) 2010-02-22
WO2006097858A2 (en) 2006-09-21
KR20070112410A (en) 2007-11-23
JP5112289B2 (en) 2013-01-09

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