WO2006107412A3 - Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface - Google Patents

Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface Download PDF

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Publication number
WO2006107412A3
WO2006107412A3 PCT/US2006/005368 US2006005368W WO2006107412A3 WO 2006107412 A3 WO2006107412 A3 WO 2006107412A3 US 2006005368 W US2006005368 W US 2006005368W WO 2006107412 A3 WO2006107412 A3 WO 2006107412A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
methods
framing
stored
serial
Prior art date
Application number
PCT/US2006/005368
Other languages
French (fr)
Other versions
WO2006107412A2 (en
Inventor
Emilio J Quiroga
Mahibur Rahman
Original Assignee
Freescale Semiconductor Inc
Emilio J Quiroga
Mahibur Rahman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Emilio J Quiroga, Mahibur Rahman filed Critical Freescale Semiconductor Inc
Priority to JP2008504041A priority Critical patent/JP4808769B2/en
Priority to KR1020077022317A priority patent/KR101183297B1/en
Publication of WO2006107412A2 publication Critical patent/WO2006107412A2/en
Publication of WO2006107412A3 publication Critical patent/WO2006107412A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Abstract

Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams (106) with a serial framing signal (106A). Offset values (420) are determined (512) from the relative locations of predetermined data correlation values (107) stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (402), and the framing signal (106A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.
PCT/US2006/005368 2005-04-01 2006-02-16 Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface WO2006107412A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008504041A JP4808769B2 (en) 2005-04-01 2006-02-16 Method and apparatus for synchronizing data transferred over a multi-pin asynchronous serial interface
KR1020077022317A KR101183297B1 (en) 2005-04-01 2006-02-16 Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/097,579 2005-04-01
US11/097,579 US7936793B2 (en) 2005-04-01 2005-04-01 Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface

Publications (2)

Publication Number Publication Date
WO2006107412A2 WO2006107412A2 (en) 2006-10-12
WO2006107412A3 true WO2006107412A3 (en) 2007-05-31

Family

ID=37070410

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/005368 WO2006107412A2 (en) 2005-04-01 2006-02-16 Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface

Country Status (4)

Country Link
US (1) US7936793B2 (en)
JP (1) JP4808769B2 (en)
KR (1) KR101183297B1 (en)
WO (1) WO2006107412A2 (en)

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US9749253B2 (en) * 2013-03-14 2017-08-29 Silver Spring Networks, Inc. Technique for implementing a latency sensitive communication protocol in a wireless mesh network
US9378174B2 (en) * 2013-11-04 2016-06-28 Xilinx, Inc. SERDES receiver oversampling rate
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CN111431533B (en) * 2020-04-26 2023-06-16 杭州电子科技大学富阳电子信息研究院有限公司 Method for synchronizing ADC data and clock of high-speed LVDS interface
KR102604266B1 (en) 2021-03-19 2023-11-21 주식회사 토닥 Device and method for data synchronization

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US20060159055A1 (en) * 2005-01-14 2006-07-20 Nokia Corporation Transmission systems

Also Published As

Publication number Publication date
US20060222017A1 (en) 2006-10-05
KR101183297B1 (en) 2012-09-14
KR20080002792A (en) 2008-01-04
WO2006107412A2 (en) 2006-10-12
US7936793B2 (en) 2011-05-03
JP2008535085A (en) 2008-08-28
JP4808769B2 (en) 2011-11-02

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