WO2006137653A1 - Electrodes for dry etching of wafer and dry etching chamber - Google Patents

Electrodes for dry etching of wafer and dry etching chamber Download PDF

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Publication number
WO2006137653A1
WO2006137653A1 PCT/KR2006/002284 KR2006002284W WO2006137653A1 WO 2006137653 A1 WO2006137653 A1 WO 2006137653A1 KR 2006002284 W KR2006002284 W KR 2006002284W WO 2006137653 A1 WO2006137653 A1 WO 2006137653A1
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WIPO (PCT)
Prior art keywords
wafer
protrusion portion
electrode
plasma
dry etching
Prior art date
Application number
PCT/KR2006/002284
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French (fr)
Inventor
Youngyul Kim
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Ci Science, Inc.
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Publication date
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Publication of WO2006137653A1 publication Critical patent/WO2006137653A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32623—Mechanical discharge control means
    • H01J37/32642—Focus rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32541—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching

Definitions

  • the present invention relates to a dry etching device used in the manufacturing process of a semiconductor integrated circuit element, and more specifically, electrodes for dry etching of a wafer and a dry etching chamber for removing foreign materials in the upper surface, side and lower surface of the edge of the wafer without damaging a minute pattern with a single process.
  • the foreign materials remaining in the edge portion of the wafer can be flown into the part in which a minute pattern is formed, and the minute pattern can be damaged. To prevent this, it is requested to remove the foreign materials remaining in the edge of the wafer.
  • the gate electrode of the semiconductor device is changed from tungsten suicide to a tungsten gate electrode, and the capacitor insulating film is changed from ONO structure to a tantalum oxide.
  • An organic bottom ARC, SiON which is an inorganic ARC layer, and Ti and TiN layer which are barrier metals are used to form photomask minute pattern.
  • lifting phenomenon occurs in the film of the polymer or stopper in the edge of the wafer after the etching or chemical deposition process. By the lifting phenomenon, the particle source in the edge is flown into the minute pattern portion during pre/post process, which becomes the direct cause of lowering of the yield.
  • the particle pollution source increases due to the increase of the area of the edge portion. Since the management of minute particles according to the constitution of the high integrated circuit makes direct effects on the yield and the reliability of a chip, it is requested to remove foreign materials (particle source) in the edge of the wafer completely.
  • wet etching method is used to remove foreign materials in the edge of the wafer conventionally.
  • the steps of the wet etching process are complicated, and various devices for deposition of an oxide film, coating of a photo- sensitizer, dry removing of a photosensitizer, removing of an oxide film, wet etching, removing of a photosensitizer, cleansing, wet etching of a nitride film, etc. are needed to perform the wet etching process. Disclosure of Invention
  • the problem of such a wet etching method is that the costs for the devices for the wet etching increase, a single process for a multilayer film cannot be performed, and the process cycle time (TAT: Turn Around Time) increases.
  • TAT Turn Around Time
  • the other problem of the wet etching method is that new particle source is generated according to the application of the wet process, and consumptive costs increase due to the use of chemical solutions.
  • the other problem of the wet etching process is that the solution after the process is a pollutional material which has a strong reactivity and is harmful to the environment, and thus separate treatment expenses are required.
  • the present invention has been made taking the foregoing problems into consideration, an object of which is to provide electrodes for dry etching of a wafer and a dry etching chamber for removing foreign materials formed in the upper surface, the side and the lower surface of the edge portion of the wafer without damaging a wafer minute pattern in a semiconductor manufacturing process.
  • the other object of the present invention is to provide electrodes for dry etching of a wafer and a dry etching chamber for removing the foreign materials effectively with a single process wherein dry etching is used.
  • electrodes for dry etching of a wafer comprising: a first electrode, in which ring- shaped first protrusion portion and first non-protrusion portion are formed to be opposed to one side among the upper surface and the lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion portion; and a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and
  • the outer diameter of the second protrusion portion can be smaller than the diameter of the wafer put on the second protrusion portion, and the outer diameter of the first protrusion portion can be larger than the diameter of the wafer.
  • the insulating material can be selected among ceramic, quartz and polymide.
  • an electrode chamber for dry etching of a wafer constituted by including a couple of a first electrode and a second electrode to form plasma by process gas provided at inside of a vacuum chamber and RF power and remove foreign materials in the edge of the wafer, comprising: a first electrode in which ring-shaped first protrusion portion and first non- protrusion portion are formed to be opposed to one side among the upper surface and lower surface of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer and; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion; a lifting plate made of an insulating material, positioned in the center
  • the upper focus ring and the lower focus ring can be selected among ceramic, quartz and polymide.
  • the distance between the lower surface of the upper insulator installed in the center portion of the first electrode and the upper surface of the wafer put on the lifting plate can be maintained to be 0.3-0.5mm.
  • the present invention can reduce the process cycle time, reduce the process ratio, and contribute to the improvement of the yield, quality and productivity.
  • Fig. 1 shows a partial sectional view illustrating electrodes for dry etching of a wafer according to one embodiment of the present invention
  • FIG. 2 shows a sketch illustrating plasma area and plasma limitation area formed in the dry etching chamber according to one embodiment of the present invention
  • FIG. 3 shows a sectional view illustrating a dry etching chamber according to one embodiment of the present invention
  • FIG. 4 shows a sectional view illustrating the constitution of a dry etching chamber in which a hooping ring is installed to prevent the secession of a wafer according to one embodiment of the present invention
  • Fig. 5 shows a functional state diagram illustrating a hooping ring which operates to make a wafer rest on a protrusion portion of a second electrode without sliding according to one embodiment of the present invention
  • FIG. 6 shows a partial magnification illustrating a detailed hooping ring according to one embodiment of the present invention
  • Fig. 7 shows a sectional view illustrating etching area of a wafer applied to a dry etching chamber according to one embodiment of the present invention.
  • Fig. 8 shows a state diagram illustrating the laminated state of foreign materials in the edge portion of a wafer. Best Mode for Carrying Out the Invention
  • Fig. 1 shows a partial sectional view illustrating electrodes for dry etching of a wafer according to one embodiment of the present invention
  • Fig. 2 shows a sketch illustrating plasma area and plasma limitation area formed in a dry etching chamber according to one embodiment of the present invention.
  • the electrodes for dry etching of a wafer have a circular flat board structure that is a general electrode form, and include a first electrode (10) and a second electrode (20) which are opposed to each other in the upper and lower directions.
  • the first electrode (10) includes ring-shaped first protrusion portion (10a) and first non-protrusion portion (10b).
  • the upper insulator (11) is made of an insulating material, and is provided in the inner side of the first protrusion portion (10a).
  • the second electrode (20) includes ring-shaped second protrusion portion (20a) and second non-protrusion portion (20b).
  • the diameter of the second protrusion portion (20a), on which a wafer is put, is smaller than that of the wafer.
  • An opening portion (20c) is formed in the inner side of the second protrusion (20a), and a lifting plate (40, please refer to Fig. T) made of an insulating material is positioned in the opening portion (20c).
  • RF power (50) is connected to the second electrode (20), and the wafer (30) is put on the second protrusion portion (20a).
  • the first electrode is grounded, and electric field is formed between the first protrusion portion (10a) and the second protrusion portion (20a).
  • Process gas is jetted between the upper insulator (11) and the first electrode (10), and plasma is formed in area B limitedly.
  • the electric field in areas A and C are offset by an insulating material. Strong electric field is formed in the area B between two protrusion portions (10a, 10b) opposed to each other, and the plasma limited to the area B is formed in the shape of a donut along the edge of the wafer (30).
  • the distance between the upper insulator (11) and the wafer (30) (area d in Fig.
  • the upper insulator (11) can be formed to have sufficient thickness with an insulating material like ceramic, quartz and polymide.
  • an insulator having sufficient thickness is provided in the outer diameter portion of the two protrusion portions (10a,20a). Therefore, as the electric field in the area C is offset, plasma is limited, and the damage of the inner wall of the vacuum chamber due to the plasma can be prevented.
  • FIG. 3 shows a sectional view illustrating a dry etching chamber according to one embodiment of the present invention.
  • the process gas is injected into a process gas inlet (80) positioned in the upper part of the first electrode (10), and is uniformly jetted to the edge of the wafer through the space between the first electrode (10) and the upper insulator (11).
  • the jetting gap of the process gas can be more than 0.3mm to be diffused sufficiently in a short moving distance.
  • an upper focus ring (90) is provided in the outer side of the first protrusion portion (10a).
  • An insulator is used as the material of the upper focus ring (90) to offset electric field/electromagnetic field.
  • the lifting slate (40) is provided in the opening portion (20c).
  • the lifting plate (40) is used to make the wafer (30) received from a transport device (Robot) put on the second protrusion portion (20a).
  • An outer ring (100) and a lower focus ring (110) are provided in the outer side of the second protrusion portion (20a).
  • the outer ring (100) and the lower focus ring (110) can be made of an insulating material like ceramic, quartz and polymide. Therefore, the electric field in area C in Fig. 2 is offset, and the plasma is limited to the area B in Fig. 2.
  • the outer ring (100) and the lower focus ring (110) have sufficient thickness to offset electric field, and are made of insulating materials having low permittivity.
  • the RF electric power (50) is applied within the dry etching chamber, stray capacitance is lowered and RF efficiency can be increased. The thickness of the insulator can be changed according to the used electric power.
  • FIG. 4 shows a sectional view illustrating the constitution of a dry etching chamber in which a hooping ring is installed to prevent the secession of a wafer according to one embodiment of the present invention.
  • the wafer (30) is transported to the dry etching chamber, the wafer (30) is put on the second protrusion portion (20a).
  • the hooping ring (120) is installed in the outer side of the outer ring (100).
  • the hooping ring (120) compensates the position of the wafer (30) by the inclination formed in the inner side of the hooping ring, when the wafer minutely secedes out of position.
  • Fig. 6 shows a partial magnification illustrating a detailed hooping ring according to one embodiment of the present invention.
  • the inner upper surface of the hooping ring (120) is formed as a flat surface (121a), and an inclination (121b) is formed in the outer side of the flat surface (121b).
  • the diameter of the wafer (30) is the same as the diameter of the inters ection formed by the flat surface (121a) and the inclination (121b) coming in contact with each other.
  • the wafer (30) slants, or is positioned on the hooping ring (120) while the center of the wafer (30) does not conform to the center of the second electrode (20), the slanted portion or the portion off the center of the wafer (30) contacts the inclination (121b) first.
  • the lower part of the wafer (30) contacting the inclination (121b) first falls along the inclination (121b), and is positioned on the flat surface (121a). Since the diameter of the intersection (121c) is the same as the outer diameter of the wafer (30), the wafer (30) can be positioned horizontally on the hooping ring (120) correctly.
  • Fig. 5 shows a functional state diagram illustrating a hooping ring which operates to make a wafer rest on a protrusion portion of a second electrode without sliding according to one embodiment of the present invention.
  • the hooping ring (120) goes up to the height of the stage of the second electrode (20), and the wafer is fallen by the lifting plate (40) and is put on the stage.
  • the position of the wafer (30) can be corrected by the hooping ring (120).
  • the hooping ring (120) is grounded, and the position of the hooping ring can be changed to adjust the etching ratio of the lower surface of the wafer (30) according to the process.
  • Fig. 7 shows a sectional view illustrating the etching area of a wafer applied to a dry etching chamber according to one embodiment of the present invention.
  • the distance d is the distance between the wafer (30) and the upper insulator (11) in the process.
  • the distance d can be selectively determined to be in the range of 0.3-0.5mm to limit plasma for the purpose of preventing damage of the wafer minute pattern (31, please refer to Fig. 2).
  • the distance d is determined to be less than twice of the sheath area in the general plasma.

Abstract

The present invention relates to electrodes for dry etching of a wafer and a dry etching chamber using the same. According to the present invention, there is provided an electrode chamber for dry etching of a wafer constituted by including a couple of a first electrode and a second electrode to form plasma by process gas provided at inside of a vacuum chamber and RF power and remove foreign materials in the edge of the wafer, comprising: a first electrode in which ring-shaped first protrusion portion and first non-protrusion portion are formed to be opposed to one side among the upper surface and lower surface of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer and; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion; a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and going up and down through an opening portion formed in the second electrode to make the wafer be put on the second protrusion portion selectively; an upper focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the first non-protrusion portion; an outer ring made of an insulating material and provided to restrain generation of plasma in the outer side of the second non-protrusion portion and determine the etching range of the lower surface of the wafer; a lower focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the outer ring; and a hooping ring going up and down to interlock with the lifting plate and provided to make the wafer align in position.

Description

Description
ELECTRODES FOR DRY ETCHING OF WAFER AND DRY
ETCHING CHAMBER
Technical Field
[1] The present invention relates to a dry etching device used in the manufacturing process of a semiconductor integrated circuit element, and more specifically, electrodes for dry etching of a wafer and a dry etching chamber for removing foreign materials in the upper surface, side and lower surface of the edge of the wafer without damaging a minute pattern with a single process. Background Art
[2] Generally, in the process of manufacturing a high integrated semiconductor device, the foreign materials remaining in the edge portion of the wafer can be flown into the part in which a minute pattern is formed, and the minute pattern can be damaged. To prevent this, it is requested to remove the foreign materials remaining in the edge of the wafer.
[3] When referring to Fig. 8, after the minute pattern (31) is formed by etching and chemical deposition process of the wafer (30), foreign materials like a poly film, an oxide film and a metal film (32,33) exist in the edge portion of the wafer (30), in which the minute pattern(31) is not formed. Also, foreign materials are generated in the edge and lower surface of the wafer (30) by the contact with a carrier used for the transportation of the wafer (30).
[4] Recently, the gate electrode of the semiconductor device is changed from tungsten suicide to a tungsten gate electrode, and the capacitor insulating film is changed from ONO structure to a tantalum oxide. An organic bottom ARC, SiON which is an inorganic ARC layer, and Ti and TiN layer which are barrier metals are used to form photomask minute pattern. Also, as the applications of processes using a material having lower electric permittivity that is used as an insulating layer in the non-memory process increase, lifting phenomenon occurs in the film of the polymer or stopper in the edge of the wafer after the etching or chemical deposition process. By the lifting phenomenon, the particle source in the edge is flown into the minute pattern portion during pre/post process, which becomes the direct cause of lowering of the yield. Especially, as the diameter of the wafer increases from 200mm (8inch) to 300mm (12inch), the particle pollution source increases due to the increase of the area of the edge portion. Since the management of minute particles according to the constitution of the high integrated circuit makes direct effects on the yield and the reliability of a chip, it is requested to remove foreign materials (particle source) in the edge of the wafer completely.
[5] As described above, wet etching method is used to remove foreign materials in the edge of the wafer conventionally. However, the steps of the wet etching process are complicated, and various devices for deposition of an oxide film, coating of a photo- sensitizer, dry removing of a photosensitizer, removing of an oxide film, wet etching, removing of a photosensitizer, cleansing, wet etching of a nitride film, etc. are needed to perform the wet etching process. Disclosure of Invention
Technical Problem
[6] The problem of such a wet etching method is that the costs for the devices for the wet etching increase, a single process for a multilayer film cannot be performed, and the process cycle time (TAT: Turn Around Time) increases. [7] The other problem of the wet etching method is that new particle source is generated according to the application of the wet process, and consumptive costs increase due to the use of chemical solutions. [8] The other problem of the wet etching process is that the solution after the process is a pollutional material which has a strong reactivity and is harmful to the environment, and thus separate treatment expenses are required. [9] The problem that the foreign materials in the upper surface, side and lower surface of the edge of the wafer cannot be selectively and simultaneously removed is shown in the poly silicon film removing process using a dry etching method, which is performed as another conventional embodiment. [10] The other problem of the dry etching method is that the side and lower surface of the wafer are not etched or the etching ratio thereof is low. [11] The other problem of the dry etching method is that a separate additional process is required to remove the foreign materials in the side or the lower surface of the wafer sufficiently, and thus additional expenses increase.
Technical Solution
[12] The present invention has been made taking the foregoing problems into consideration, an object of which is to provide electrodes for dry etching of a wafer and a dry etching chamber for removing foreign materials formed in the upper surface, the side and the lower surface of the edge portion of the wafer without damaging a wafer minute pattern in a semiconductor manufacturing process. [13] The other object of the present invention is to provide electrodes for dry etching of a wafer and a dry etching chamber for removing the foreign materials effectively with a single process wherein dry etching is used. [14] To obtain the objects, according to the present invention, there are provided electrodes for dry etching of a wafer, comprising: a first electrode, in which ring- shaped first protrusion portion and first non-protrusion portion are formed to be opposed to one side among the upper surface and the lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion portion; and a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and going up and down through an opening portion formed in the second electrode to let the wafer be selectively positioned on the second protrusion portion.
[15] According to the present invention, the outer diameter of the second protrusion portion can be smaller than the diameter of the wafer put on the second protrusion portion, and the outer diameter of the first protrusion portion can be larger than the diameter of the wafer.
[16] According to the present invention, the insulating material can be selected among ceramic, quartz and polymide.
[17] According to the present invention, there can be provided an electrode chamber for dry etching of a wafer constituted by including a couple of a first electrode and a second electrode to form plasma by process gas provided at inside of a vacuum chamber and RF power and remove foreign materials in the edge of the wafer, comprising: a first electrode in which ring-shaped first protrusion portion and first non- protrusion portion are formed to be opposed to one side among the upper surface and lower surface of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer and; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion; a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and going up and down through an opening portion formed in the second electrode to make the wafer be put on the second protrusion portion selectively; an upper focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the first non-protrusion portion; an outer ring made of an insulating material and provided to restrain generation of plasma in the outer side of the second non-protrusion portion and determine the etching range of the lower surface of the wafer; a lower focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the outer ring; and a hooping ring going up and down to interlock with the lifting plate and provided to make the wafer align in position.
[18] According to the present invention, the upper focus ring and the lower focus ring can be selected among ceramic, quartz and polymide.
[19] According to the present invention, the distance between the lower surface of the upper insulator installed in the center portion of the first electrode and the upper surface of the wafer put on the lifting plate can be maintained to be 0.3-0.5mm.
[20] Various foreign materials laminated in the upper surface, the lower surface and the side of the edge portion of the wafer can be removed by the present invention.
Advantageous Effects
[21] According to the dry etching chamber in which the aforesaid electrode of the present invention is used, a separate additional process is not required among the semiconductor manufacturing process. Also, according to the dry etching chamber in which the aforesaid electrode of the present invention is used, various foreign materials laminated in the upper surface, side and lower surface of the edge portion of the wafer can be selectively removed with a single dry etching type process. Therefore, the present invention can reduce the process cycle time, reduce the process ratio, and contribute to the improvement of the yield, quality and productivity. Brief Description of the Drawings
[22] The above features and advantages of the present invention will be more apparent by describing certain embodiments of the present invention with reference to the accompanying drawings, in which
[23] Fig. 1 shows a partial sectional view illustrating electrodes for dry etching of a wafer according to one embodiment of the present invention;
[24] Fig. 2 shows a sketch illustrating plasma area and plasma limitation area formed in the dry etching chamber according to one embodiment of the present invention;
[25] Fig. 3 shows a sectional view illustrating a dry etching chamber according to one embodiment of the present invention;
[26] Fig. 4 shows a sectional view illustrating the constitution of a dry etching chamber in which a hooping ring is installed to prevent the secession of a wafer according to one embodiment of the present invention;
[27] Fig. 5 shows a functional state diagram illustrating a hooping ring which operates to make a wafer rest on a protrusion portion of a second electrode without sliding according to one embodiment of the present invention;
[28] Fig. 6 shows a partial magnification illustrating a detailed hooping ring according to one embodiment of the present invention;
[29] Fig. 7 shows a sectional view illustrating etching area of a wafer applied to a dry etching chamber according to one embodiment of the present invention; and
[30] Fig. 8 shows a state diagram illustrating the laminated state of foreign materials in the edge portion of a wafer. Best Mode for Carrying Out the Invention
[31] The preferred embodiments of the present invention to achieve the objects specifically will be explained with reference to the accompanying drawings. When the embodiments are explained, the same title and reference numeral will be used for the same constitution, and additional explanation thereof will be omitted.
[32] The preferred embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
[33] Fig. 1 shows a partial sectional view illustrating electrodes for dry etching of a wafer according to one embodiment of the present invention, and Fig. 2 shows a sketch illustrating plasma area and plasma limitation area formed in a dry etching chamber according to one embodiment of the present invention.
[34] As illustrated in Figs. 1 and 2, the electrodes for dry etching of a wafer according to one embodiment of the present invention have a circular flat board structure that is a general electrode form, and include a first electrode (10) and a second electrode (20) which are opposed to each other in the upper and lower directions. The first electrode (10) includes ring-shaped first protrusion portion (10a) and first non-protrusion portion (10b). The upper insulator (11) is made of an insulating material, and is provided in the inner side of the first protrusion portion (10a).
[35] Like the first electrode (10), the second electrode (20) includes ring-shaped second protrusion portion (20a) and second non-protrusion portion (20b). The diameter of the second protrusion portion (20a), on which a wafer is put, is smaller than that of the wafer. An opening portion (20c) is formed in the inner side of the second protrusion (20a), and a lifting plate (40, please refer to Fig. T) made of an insulating material is positioned in the opening portion (20c).
[36] RF power (50) is connected to the second electrode (20), and the wafer (30) is put on the second protrusion portion (20a). The first electrode is grounded, and electric field is formed between the first protrusion portion (10a) and the second protrusion portion (20a). Process gas is jetted between the upper insulator (11) and the first electrode (10), and plasma is formed in area B limitedly. The electric field in areas A and C are offset by an insulating material. Strong electric field is formed in the area B between two protrusion portions (10a, 10b) opposed to each other, and the plasma limited to the area B is formed in the shape of a donut along the edge of the wafer (30). Here, the distance between the upper insulator (11) and the wafer (30) (area d in Fig. 7) is set up to be in the range not exceeding 0.5mm during the process, to limit the formation of plasma in area A. The upper insulator (11) can be formed to have sufficient thickness with an insulating material like ceramic, quartz and polymide. In the case of the area C, an insulator having sufficient thickness is provided in the outer diameter portion of the two protrusion portions (10a,20a). Therefore, as the electric field in the area C is offset, plasma is limited, and the damage of the inner wall of the vacuum chamber due to the plasma can be prevented. Mode for the Invention
[37] Fig. 3 shows a sectional view illustrating a dry etching chamber according to one embodiment of the present invention.
[38] As illustrated in Fig. 3, the process gas is injected into a process gas inlet (80) positioned in the upper part of the first electrode (10), and is uniformly jetted to the edge of the wafer through the space between the first electrode (10) and the upper insulator (11). The jetting gap of the process gas can be more than 0.3mm to be diffused sufficiently in a short moving distance. To limit the plasma to the edge of the wafer (30), an upper focus ring (90) is provided in the outer side of the first protrusion portion (10a). An insulator is used as the material of the upper focus ring (90) to offset electric field/electromagnetic field.
[39] The lifting slate (40) is provided in the opening portion (20c). The lifting plate (40) is used to make the wafer (30) received from a transport device (Robot) put on the second protrusion portion (20a). An outer ring (100) and a lower focus ring (110) are provided in the outer side of the second protrusion portion (20a). The outer ring (100) and the lower focus ring (110) can be made of an insulating material like ceramic, quartz and polymide. Therefore, the electric field in area C in Fig. 2 is offset, and the plasma is limited to the area B in Fig. 2. The outer ring (100) and the lower focus ring (110) have sufficient thickness to offset electric field, and are made of insulating materials having low permittivity. When the RF electric power (50) is applied within the dry etching chamber, stray capacitance is lowered and RF efficiency can be increased. The thickness of the insulator can be changed according to the used electric power.
[40] Fig. 4 shows a sectional view illustrating the constitution of a dry etching chamber in which a hooping ring is installed to prevent the secession of a wafer according to one embodiment of the present invention. [41] As illustrated in Fig. 4, when the wafer (30) is transported to the dry etching chamber, the wafer (30) is put on the second protrusion portion (20a). To prevent minute sliding of the wafer (30) in the second protrusion portion (20a), the hooping ring (120) is installed in the outer side of the outer ring (100). The hooping ring (120) compensates the position of the wafer (30) by the inclination formed in the inner side of the hooping ring, when the wafer minutely secedes out of position.
[42] Fig. 6 shows a partial magnification illustrating a detailed hooping ring according to one embodiment of the present invention.
[43] As illustrated in Fig. 6, the inner upper surface of the hooping ring (120) is formed as a flat surface (121a), and an inclination (121b) is formed in the outer side of the flat surface (121b). The diameter of the wafer (30) is the same as the diameter of the inters ection formed by the flat surface (121a) and the inclination (121b) coming in contact with each other. When the wafer (30) slants, or is positioned on the hooping ring (120) while the center of the wafer (30) does not conform to the center of the second electrode (20), the slanted portion or the portion off the center of the wafer (30) contacts the inclination (121b) first. The lower part of the wafer (30) contacting the inclination (121b) first falls along the inclination (121b), and is positioned on the flat surface (121a). Since the diameter of the intersection (121c) is the same as the outer diameter of the wafer (30), the wafer (30) can be positioned horizontally on the hooping ring (120) correctly.
[44] Fig. 5 shows a functional state diagram illustrating a hooping ring which operates to make a wafer rest on a protrusion portion of a second electrode without sliding according to one embodiment of the present invention.
[45] As illustrated in Fig. 5, the hooping ring (120) is lifted and fallen by a cylinder
(130) installed at the outside of the vacuum chamber (not illustrated). Firstly, the hooping ring (120) goes up to the height of the stage of the second electrode (20), and the wafer is fallen by the lifting plate (40) and is put on the stage. Here, even if the wafer (30) is slid, the position of the wafer (30) can be corrected by the hooping ring (120). The hooping ring (120) is grounded, and the position of the hooping ring can be changed to adjust the etching ratio of the lower surface of the wafer (30) according to the process.
[46] Fig. 7 shows a sectional view illustrating the etching area of a wafer applied to a dry etching chamber according to one embodiment of the present invention.
[47] As illustrated in Fig. 7, the etching range in the area b formed in the upper surface
(30a) of the wafer can be determined by the outer diameter of the upper insulator (11). The etching range in the area "b+c" formed in the lower surface (30c) of the wafer can be determined by the outer diameter of the outer ring (100) installed in the outer side of the second protrusion portion (20a). As described above, the distance d is the distance between the wafer (30) and the upper insulator (11) in the process. The distance d can be selectively determined to be in the range of 0.3-0.5mm to limit plasma for the purpose of preventing damage of the wafer minute pattern (31, please refer to Fig. 2). The distance d is determined to be less than twice of the sheath area in the general plasma.
[48] In the same manner as in the conventional art, the foreign materials removed from the wafer (30) and reaction gas are pumped out through an outlet (70, please, refer to Fig. 3) while the etching process is being executed.
[49] In the dry etching of the edge of the wafer (30) according to the present invention, corresponding foreign materials can be removed by the use of combination of etching reaction gases described in Table 1.
[50] Table 1
Figure imgf000009_0001
[51] The foregoing embodiment and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. Also, the description of the embodiments of the present invention is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

Claims
[1] Electrodes for dry etching of a wafer, comprising: a first electrode, in which ring-shaped first protrusion portion and first non- protrusion portion are formed to be opposed to one side among the upper surface and the lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer, and plasma is formed to remove foreign materials in the edge of the wafer; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion portion; and a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and going up and down through an opening portion formed in the second electrode to make the wafer be selectively positioned on the second protrusion portion.
[2] The electrodes for dry etching of a wafer as claimed in claim 1 , in which the outer diameter of the second protrusion portion is smaller than the diameter of the wafer put on the second protrusion portion, and the outer diameter of the first protrusion portion is larger than the diameter of the wafer
[3] The electrodes for dry etching of a wafer as claimed in claim 1, in which the insulating material is selected among ceramic, quartz and polymide
[4] An electrode chamber for dry etching of a wafer constituted by including a couple of a first electrode and a second electrode to form plasma by process gas provided at inside of a vacuum chamber and RF power and remove foreign materials in the edge of the wafer, the electrode chamber comprising: a first electrode in which ring-shaped first protrusion portion and first non- protrusion portion are formed to be opposed to one side among the upper surface and lower surface of the wafer; a second electrode in which ring-shaped second protrusion portion and second non-protrusion portion being smaller than the outer diameters of the first protrusion portion and the first non-protrusion portion respectively are formed to be opposed to the other side among the upper surface and lower surface of the wafer and; an upper insulator made of an insulating material and provided between the center portion of the first electrode and the inner diameter of the first protrusion portion to restrain generation of plasma in the inner side of the first protrusion; a lifting plate made of an insulating material, positioned in the center portion of the second electrode, and going up and down through an opening portion formed in the second electrode to make the wafer be put on the second protrusion portion selectively; an upper focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the first non-protrusion portion; an outer ring made of an insulating material and provided to restrain generation of plasma in the outer side of the second non-protrusion portion and determine the etching range of the lower surface of the wafer; a lower focus ring made of an insulating material and provided to restrain generation of plasma in the outer side of the outer ring; and a hooping ring going up and down to interlock with the lifting plate and provided to make the wafer align in position.
[5] The electrode chamber for dry etching of a wafer as claimed in claim 4, wherein the upper focus ring and the lower focus ring are selected among ceramic, quartz and polymide
[6] The electrode chamber for dry etching of a wafer as claimed in claim 4, the distance between the lower surface of the upper insulator installed in the center portion of the first electrode and the upper surface of the wafer put on the lifting plate is maintained to be 0.3-0.5mm
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