WO2006138424A3 - Through chip connection - Google Patents

Through chip connection Download PDF

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Publication number
WO2006138424A3
WO2006138424A3 PCT/US2006/023248 US2006023248W WO2006138424A3 WO 2006138424 A3 WO2006138424 A3 WO 2006138424A3 US 2006023248 W US2006023248 W US 2006023248W WO 2006138424 A3 WO2006138424 A3 WO 2006138424A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor material
substrate
forming
annular trench
metalizing
Prior art date
Application number
PCT/US2006/023248
Other languages
French (fr)
Other versions
WO2006138424A2 (en
Inventor
John Trzza
Original Assignee
Cubic Wafer Inc
John Trzza
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/329,852 external-priority patent/US7482272B2/en
Priority claimed from US11/329,887 external-priority patent/US7215032B2/en
Application filed by Cubic Wafer Inc, John Trzza filed Critical Cubic Wafer Inc
Publication of WO2006138424A2 publication Critical patent/WO2006138424A2/en
Publication of WO2006138424A3 publication Critical patent/WO2006138424A3/en

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench in the portion, forming an island of semiconductor material within the annular trench, filling the annular trench with an electrically insulating material, removing at least some of the island of semiconductor material to create an exposed inner surface, metalizing at least a portion of the exposed inner surface with a material, and thinning an outer surface side of the substrate until at least the material from the metalizing is exposed on the outer surface side of the substrate.
PCT/US2006/023248 2005-06-14 2006-06-14 Through chip connection WO2006138424A2 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US69075905P 2005-06-14 2005-06-14
US60/690,759 2005-06-14
US11/329,852 US7482272B2 (en) 2005-06-14 2006-01-10 Through chip connection
US11/329,953 US7157372B1 (en) 2005-06-14 2006-01-10 Coaxial through chip connection
US11/329,953 2006-01-10
US11/329,852 2006-01-10
US11/329,887 US7215032B2 (en) 2005-06-14 2006-01-10 Triaxial through-chip connection
US11/329,887 2006-01-10

Publications (2)

Publication Number Publication Date
WO2006138424A2 WO2006138424A2 (en) 2006-12-28
WO2006138424A3 true WO2006138424A3 (en) 2009-06-04

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PCT/US2006/023248 WO2006138424A2 (en) 2005-06-14 2006-06-14 Through chip connection

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498089B2 (en) * 2001-03-09 2002-12-24 Fujitsu Limited Semiconductor integrated circuit device with moisture-proof ring and its manufacture method
US20050101054A1 (en) * 2002-04-05 2005-05-12 Stmicroelectronics S.R.L. Process for manufacturing a through insulated interconnection in a body of semiconductor material
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498089B2 (en) * 2001-03-09 2002-12-24 Fujitsu Limited Semiconductor integrated circuit device with moisture-proof ring and its manufacture method
US20050101054A1 (en) * 2002-04-05 2005-05-12 Stmicroelectronics S.R.L. Process for manufacturing a through insulated interconnection in a body of semiconductor material
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same

Also Published As

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