WO2006138583A3 - Sequential scan test of interface between ic modules that operate at different frequencies - Google Patents

Sequential scan test of interface between ic modules that operate at different frequencies Download PDF

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Publication number
WO2006138583A3
WO2006138583A3 PCT/US2006/023516 US2006023516W WO2006138583A3 WO 2006138583 A3 WO2006138583 A3 WO 2006138583A3 US 2006023516 W US2006023516 W US 2006023516W WO 2006138583 A3 WO2006138583 A3 WO 2006138583A3
Authority
WO
WIPO (PCT)
Prior art keywords
modules
interface
operate
different frequencies
sequential scan
Prior art date
Application number
PCT/US2006/023516
Other languages
French (fr)
Other versions
WO2006138583A2 (en
Inventor
Naga Satya Srikanth Puvvada
Nikila Krishnamoorthy
Sandeep Jain
Jais Abraham
Original Assignee
Texas Instruments Inc
Naga Satya Srikanth Puvvada
Nikila Krishnamoorthy
Sandeep Jain
Jais Abraham
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/160,235 external-priority patent/US7421634B2/en
Application filed by Texas Instruments Inc, Naga Satya Srikanth Puvvada, Nikila Krishnamoorthy, Sandeep Jain, Jais Abraham filed Critical Texas Instruments Inc
Publication of WO2006138583A2 publication Critical patent/WO2006138583A2/en
Publication of WO2006138583A3 publication Critical patent/WO2006138583A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Abstract

Integrated circuit modules (160, 180) designed to operate at different frequencies in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment, the interface logic (170) connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).
PCT/US2006/023516 2005-06-15 2006-06-15 Sequential scan test of interface between ic modules that operate at different frequencies WO2006138583A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/160,235 US7421634B2 (en) 2005-05-02 2005-06-15 Sequential scan based techniques to test interface between modules designed to operate at different frequencies
US11/160,235 2005-06-15

Publications (2)

Publication Number Publication Date
WO2006138583A2 WO2006138583A2 (en) 2006-12-28
WO2006138583A3 true WO2006138583A3 (en) 2008-07-31

Family

ID=37571213

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/023516 WO2006138583A2 (en) 2005-06-15 2006-06-15 Sequential scan test of interface between ic modules that operate at different frequencies

Country Status (1)

Country Link
WO (1) WO2006138583A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644328B2 (en) * 2007-03-22 2010-01-05 Intel Corporation Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US20050102592A1 (en) * 2001-08-17 2005-05-12 Credence Systems Corporation Circuit testing with ring-connected test instrument modules

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US20050102592A1 (en) * 2001-08-17 2005-05-12 Credence Systems Corporation Circuit testing with ring-connected test instrument modules

Also Published As

Publication number Publication date
WO2006138583A2 (en) 2006-12-28

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