WO2007000060A3 - Software controlled clock synthesizer - Google Patents

Software controlled clock synthesizer Download PDF

Info

Publication number
WO2007000060A3
WO2007000060A3 PCT/CA2006/001120 CA2006001120W WO2007000060A3 WO 2007000060 A3 WO2007000060 A3 WO 2007000060A3 CA 2006001120 W CA2006001120 W CA 2006001120W WO 2007000060 A3 WO2007000060 A3 WO 2007000060A3
Authority
WO
WIPO (PCT)
Prior art keywords
enabling
software controlled
referencing
sccs
controlled clock
Prior art date
Application number
PCT/CA2006/001120
Other languages
French (fr)
Other versions
WO2007000060A2 (en
Inventor
John W Bogdan
Original Assignee
John W Bogdan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by John W Bogdan filed Critical John W Bogdan
Publication of WO2007000060A2 publication Critical patent/WO2007000060A2/en
Publication of WO2007000060A3 publication Critical patent/WO2007000060A3/en
Priority to US11/931,026 priority Critical patent/US8374075B2/en
Priority to US12/351,824 priority patent/US9794096B2/en
Priority to US13/323,820 priority patent/US9077315B2/en
Priority to US13/763,729 priority patent/US8982974B2/en
Priority to US13/844,722 priority patent/US9100165B2/en
Priority to US14/656,264 priority patent/US9641315B2/en
Priority to US14/738,920 priority patent/US9838236B2/en
Priority to US15/582,747 priority patent/US10057047B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition

Abstract

An inexpensive high accuracy software controlled clock synthesizer (SCCS) enabling by one order better accuracy of phase & frequency synthesis producing low jitter synchronized clock from external time referencing signals or time referencing messages. The SCCS includes; a hybrid PLL (HPLL) enabling frequency multiplication factors ranging from 1 to 50 000 while maintaining very low output jitter independent of reference clock quality, and noise filtering edge detectors (NFED) enabling by one order better accuracy of referencing signal phase detection.
PCT/CA2006/001120 2003-06-25 2006-06-27 Software controlled clock synthesizer WO2007000060A2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US11/931,026 US8374075B2 (en) 2006-06-27 2007-10-31 Phase and frequency recovery techniques
US12/351,824 US9794096B2 (en) 2005-06-27 2009-01-10 Direct synchronization of synthesized clock
US13/323,820 US9077315B2 (en) 2003-06-25 2011-12-12 Inverse signal transformation
US13/763,729 US8982974B2 (en) 2005-06-27 2013-02-10 OFDM clock recovery
US13/844,722 US9100165B2 (en) 2005-06-27 2013-03-15 Direct data recovery
US14/656,264 US9641315B2 (en) 2005-06-27 2015-03-12 Clock recovery techniques
US14/738,920 US9838236B2 (en) 2006-06-27 2015-06-14 Direct synthesis of receiver clock
US15/582,747 US10057047B2 (en) 2005-06-27 2017-04-30 Phase synthesis techniques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA 2510004 CA2510004A1 (en) 2005-06-27 2005-06-27 Software controlled clock synchronizer
CA2,510,004 2005-06-27

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CAPCT/CA2008/001991 Continuation-In-Part 2008-11-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/931,026 Continuation-In-Part US8374075B2 (en) 2003-06-25 2007-10-31 Phase and frequency recovery techniques

Publications (2)

Publication Number Publication Date
WO2007000060A2 WO2007000060A2 (en) 2007-01-04
WO2007000060A3 true WO2007000060A3 (en) 2007-02-15

Family

ID=37561589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2006/001120 WO2007000060A2 (en) 2003-06-25 2006-06-27 Software controlled clock synthesizer

Country Status (2)

Country Link
CA (1) CA2510004A1 (en)
WO (1) WO2007000060A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108712226A (en) * 2018-05-28 2018-10-26 中国电子科技集团公司第二十九研究所 A kind of chip semi-automatic synchronized method and system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112532239B (en) * 2020-11-24 2024-01-02 珠海泰芯半导体有限公司 USB data recovery system
CN116301197B (en) * 2023-04-27 2023-08-04 上海合见工业软件集团有限公司 Clock data recovery method, electronic device and medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US6686784B2 (en) * 2001-12-20 2004-02-03 Realtek Semiconductor Corp. Hybrid phase-locked loop
US20050007203A1 (en) * 2003-07-07 2005-01-13 Wei-Zen Chen Frequency synthesizing circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US6686784B2 (en) * 2001-12-20 2004-02-03 Realtek Semiconductor Corp. Hybrid phase-locked loop
US20050007203A1 (en) * 2003-07-07 2005-01-13 Wei-Zen Chen Frequency synthesizing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108712226A (en) * 2018-05-28 2018-10-26 中国电子科技集团公司第二十九研究所 A kind of chip semi-automatic synchronized method and system
CN108712226B (en) * 2018-05-28 2020-03-27 中国电子科技集团公司第二十九研究所 Chip semi-automatic synchronization method and system

Also Published As

Publication number Publication date
WO2007000060A2 (en) 2007-01-04
CA2510004A1 (en) 2006-12-27

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