WO2007001653A3 - Reticle alignment technique - Google Patents

Reticle alignment technique Download PDF

Info

Publication number
WO2007001653A3
WO2007001653A3 PCT/US2006/018380 US2006018380W WO2007001653A3 WO 2007001653 A3 WO2007001653 A3 WO 2007001653A3 US 2006018380 W US2006018380 W US 2006018380W WO 2007001653 A3 WO2007001653 A3 WO 2007001653A3
Authority
WO
WIPO (PCT)
Prior art keywords
reticle alignment
alignment technique
patterned layer
alignment grid
shrink
Prior art date
Application number
PCT/US2006/018380
Other languages
French (fr)
Other versions
WO2007001653A2 (en
Inventor
S M Reza Sadjadi
Original Assignee
Lam Res Corp
S M Reza Sadjadi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp, S M Reza Sadjadi filed Critical Lam Res Corp
Priority to CN2006800213270A priority Critical patent/CN101313403B/en
Priority to KR1020077030027A priority patent/KR101234891B1/en
Publication of WO2007001653A2 publication Critical patent/WO2007001653A2/en
Publication of WO2007001653A3 publication Critical patent/WO2007001653A3/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7007—Alignment other than original with workpiece
    • G03F9/7011—Pre-exposure scan; original with original holder alignment; Prealignment, i.e. workpiece with workpiece holder
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7019—Calibration
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7046—Strategy, e.g. mark, sensor or wavelength selection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Abstract

A method for aligning a reticle is provided (304, 324). A first patterned layer with a first alignment grid is formed (308). Sidewall layers are formed over the first patterned layer to perform a first shrink (312). The first alignment grid after shrink is etched into an etch layer to form an etched first alignment grid (316). The patterned layer is removed (320).
PCT/US2006/018380 2005-06-21 2006-05-10 Reticle alignment technique WO2007001653A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800213270A CN101313403B (en) 2005-06-21 2006-05-10 Reticle alignment technique
KR1020077030027A KR101234891B1 (en) 2005-06-21 2006-05-10 Reticle alignment technique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/158,680 US7629259B2 (en) 2005-06-21 2005-06-21 Method of aligning a reticle for formation of semiconductor devices
US11/158,680 2005-06-21

Publications (2)

Publication Number Publication Date
WO2007001653A2 WO2007001653A2 (en) 2007-01-04
WO2007001653A3 true WO2007001653A3 (en) 2007-08-23

Family

ID=37573030

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/018380 WO2007001653A2 (en) 2005-06-21 2006-05-10 Reticle alignment technique

Country Status (6)

Country Link
US (1) US7629259B2 (en)
KR (1) KR101234891B1 (en)
CN (1) CN101313403B (en)
MY (1) MY142277A (en)
TW (1) TWI460558B (en)
WO (1) WO2007001653A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7629259B2 (en) 2005-06-21 2009-12-08 Lam Research Corporation Method of aligning a reticle for formation of semiconductor devices
JP5259380B2 (en) * 2008-12-24 2013-08-07 株式会社東芝 Manufacturing method of semiconductor device
US8559001B2 (en) 2010-01-11 2013-10-15 Kla-Tencor Corporation Inspection guided overlay metrology
US8745546B2 (en) 2011-12-29 2014-06-03 Nanya Technology Corporation Mask overlay method, mask, and semiconductor device using the same
US9171703B2 (en) 2013-12-20 2015-10-27 Seagate Technology Llc Apparatus with sidewall protection for features
DE102017213330A1 (en) * 2017-08-02 2019-02-07 Dr. Johannes Heidenhain Gmbh Scanning plate for an optical position measuring device
US11055464B2 (en) * 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Critical dimension uniformity

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661105B2 (en) * 2001-04-13 2003-12-09 Oki Electric Industry Co., Ltd. Alignment mark structure
US20030229880A1 (en) * 2002-06-07 2003-12-11 David White Test masks for lithographic and etch processes

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547446A (en) 1983-06-20 1985-10-15 The Perkin-Elmer Corporation Motion measurement and alignment method and apparatus
US4778739A (en) 1986-08-25 1988-10-18 International Business Machines Corporation Photoresist process for reactive ion etching of metal patterns for semiconductor devices
US6109775A (en) * 1991-07-19 2000-08-29 Lsi Logic Corporation Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
KR100230430B1 (en) * 1997-07-16 1999-11-15 윤종용 Gas compound and method for etching electrode layer using the same
CA2246087A1 (en) * 1998-08-28 2000-02-28 Northern Telecom Limited Method of cleaving a semiconductor wafer
JP2000294490A (en) * 1999-04-07 2000-10-20 Nec Corp Semiconductor device and its manufacture
US6251745B1 (en) 1999-08-18 2001-06-26 Taiwan Semiconductor Manufacturing Company Two-dimensional scaling method for determining the overlay error and overlay process window for integrated circuits
US6396569B2 (en) * 1999-09-02 2002-05-28 Texas Instruments Incorporated Image displacement test reticle for measuring aberration characteristics of projection optics
US7317531B2 (en) 2002-12-05 2008-01-08 Kla-Tencor Technologies Corporation Apparatus and methods for detecting overlay errors using scatterometry
JP2004523906A (en) 2000-10-12 2004-08-05 ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム Templates for room-temperature and low-pressure micro and nano-transfer lithography
US6819426B2 (en) 2001-02-12 2004-11-16 Therma-Wave, Inc. Overlay alignment metrology using diffraction gratings
US20040023253A1 (en) * 2001-06-11 2004-02-05 Sandeep Kunwar Device structure for closely spaced electrodes
US6486549B1 (en) * 2001-11-10 2002-11-26 Bridge Semiconductor Corporation Semiconductor module with encapsulant base
US6809824B1 (en) 2001-11-30 2004-10-26 Lsi Logic Corporation Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate
US6759180B2 (en) * 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
EP1532670A4 (en) * 2002-06-07 2007-09-12 Praesagus Inc Characterization adn reduction of variation for integrated circuits
US6734107B2 (en) * 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US7170604B2 (en) * 2002-07-03 2007-01-30 Tokyo Electron Limited Overlay metrology method and apparatus using more than one grating per measurement direction
US6936386B2 (en) * 2003-10-17 2005-08-30 United Microelectronics Corp. Reticle alignment procedure
US7241538B2 (en) * 2003-11-05 2007-07-10 Promos Technologies Method for providing representative features for use in inspection of photolithography mask and for use in inspection photo-lithographically developed and/or patterned wafer layers, and products of same
US7629259B2 (en) 2005-06-21 2009-12-08 Lam Research Corporation Method of aligning a reticle for formation of semiconductor devices
US7572572B2 (en) * 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661105B2 (en) * 2001-04-13 2003-12-09 Oki Electric Industry Co., Ltd. Alignment mark structure
US20030229880A1 (en) * 2002-06-07 2003-12-11 David White Test masks for lithographic and etch processes

Also Published As

Publication number Publication date
CN101313403A (en) 2008-11-26
CN101313403B (en) 2011-03-16
US20060285113A1 (en) 2006-12-21
WO2007001653A2 (en) 2007-01-04
TW200710613A (en) 2007-03-16
KR20080017386A (en) 2008-02-26
US7629259B2 (en) 2009-12-08
TWI460558B (en) 2014-11-11
KR101234891B1 (en) 2013-02-19
MY142277A (en) 2010-11-15

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