WO2007015951A3 - Semiconductor structures formed on substrates and methods of manufacturing the same - Google Patents

Semiconductor structures formed on substrates and methods of manufacturing the same Download PDF

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Publication number
WO2007015951A3
WO2007015951A3 PCT/US2006/028270 US2006028270W WO2007015951A3 WO 2007015951 A3 WO2007015951 A3 WO 2007015951A3 US 2006028270 W US2006028270 W US 2006028270W WO 2007015951 A3 WO2007015951 A3 WO 2007015951A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor structures
layer
doped silicon
silicon dioxide
initial substrate
Prior art date
Application number
PCT/US2006/028270
Other languages
French (fr)
Other versions
WO2007015951A2 (en
Inventor
Qi Wang
Minhua Li
Jeffrey H Rice
Original Assignee
Fairchild Semiconductor
Qi Wang
Minhua Li
Jeffrey H Rice
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor, Qi Wang, Minhua Li, Jeffrey H Rice filed Critical Fairchild Semiconductor
Priority to JP2008523983A priority Critical patent/JP2009503853A/en
Priority to DE112006001943T priority patent/DE112006001943T5/en
Priority to AT0928306A priority patent/AT504591A2/en
Publication of WO2007015951A2 publication Critical patent/WO2007015951A2/en
Publication of WO2007015951A3 publication Critical patent/WO2007015951A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the doped silicon layer and the initial substrate. Semiconductor structures are formed within/on an epitaxial layer disposed on the doped silicon layer forming an intermediate semiconductor structure. A process handle is temporarily bonded to the semiconductor structures for support. The initial substrate is thinned and removed by a mechanical thinning process followed by chemical etching using the buried silicon dioxide layer as an etch stop. The silicon dioxide layer is chemically removed from the doped silicon layer. A base substrate is formed on the doped silicon layer. The process handle is removed leaving the semiconductor structures disposed on the base substrate.
PCT/US2006/028270 2005-07-25 2006-07-19 Semiconductor structures formed on substrates and methods of manufacturing the same WO2007015951A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008523983A JP2009503853A (en) 2005-07-25 2006-07-19 Semiconductor structure formed on a substrate and method of manufacturing the same
DE112006001943T DE112006001943T5 (en) 2005-07-25 2006-07-19 Semiconductor structures formed on substrates and methods for manufacturing the same
AT0928306A AT504591A2 (en) 2005-07-25 2006-07-19 SUBSTRATE SEMICONDUCTOR SEMICONDUCTOR STRUCTURES AND METHOD FOR MANUFACTURING THEM

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/189,163 US7635637B2 (en) 2005-07-25 2005-07-25 Semiconductor structures formed on substrates and methods of manufacturing the same
US11/189,163 2005-07-25

Publications (2)

Publication Number Publication Date
WO2007015951A2 WO2007015951A2 (en) 2007-02-08
WO2007015951A3 true WO2007015951A3 (en) 2007-08-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/028270 WO2007015951A2 (en) 2005-07-25 2006-07-19 Semiconductor structures formed on substrates and methods of manufacturing the same

Country Status (8)

Country Link
US (2) US7635637B2 (en)
JP (1) JP2009503853A (en)
KR (1) KR20080042833A (en)
CN (1) CN101233603A (en)
AT (1) AT504591A2 (en)
DE (1) DE112006001943T5 (en)
TW (1) TW200710991A (en)
WO (1) WO2007015951A2 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
CN100474642C (en) * 2005-10-27 2009-04-01 晶能光电（江西）有限公司 Indium gallium aluminium nitrogen semi-conductor luminous element containing metallic chromium substrate and manufacturing method thereof
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US8101500B2 (en) * 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US7951688B2 (en) * 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
DE102008006745B3 (en) * 2008-01-30 2009-10-08 Siltronic Ag Method for producing a semiconductor structure
JP2010045123A (en) * 2008-08-11 2010-02-25 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US8039877B2 (en) * 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
US8237195B2 (en) * 2008-09-29 2012-08-07 Fairchild Semiconductor Corporation Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
US20110147796A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Austria Ag Semiconductor device with metal carrier and manufacturing method
CN102110605B (en) * 2009-12-24 2012-06-06 北大方正集团有限公司 Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip
US8525260B2 (en) * 2010-03-19 2013-09-03 Monolithic Power Systems, Inc. Super junction device with deep trench and implant
US8242013B2 (en) * 2010-03-30 2012-08-14 Alpha & Omega Semiconductor Inc. Virtually substrate-less composite power semiconductor device and method
TWI414069B (en) * 2011-01-05 2013-11-01 Anpec Electronics Corp Power transistor with low interface of low Miller capacitor and its making method
US9887283B2 (en) * 2013-05-10 2018-02-06 Alpha And Omega Semiconductor Incorporated Process method and structure for high voltage MOSFETs
KR20160130538A (en) * 2015-05-04 2016-11-14 이태복 Apparatus and method for manufacturing a ultra thin device
KR102388994B1 (en) 2016-03-22 2022-04-22 실텍트라 게엠베하 Combined laser treatment of a solid body to be split
CN107275197A (en) 2016-04-08 2017-10-20 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
EP3551373A1 (en) * 2016-12-12 2019-10-16 Siltectra GmbH Method for thinning solid body layers provided with components
US11796737B2 (en) * 2020-08-10 2023-10-24 GenXComm, Inc. Co-manufacturing of silicon-on-insulator waveguides and silicon nitride waveguides for hybrid photonic integrated circuits
CN112967982B (en) * 2020-09-10 2022-04-19 重庆康佳光电技术研究院有限公司 Transfer substrate, manufacturing method of transfer substrate, chip transfer method and display panel

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4616408A (en) * 1982-11-24 1986-10-14 Hewlett-Packard Company Inversely processed resistance heater
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US6468923B1 (en) * 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
US20040140479A1 (en) * 2003-01-10 2004-07-22 Takeshi Akatsu Compliant substrate for a heteroepitaxial structure and method for making same

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2280427A1 (en) * 1974-07-31 1976-02-27 Commissariat Energie Atomique PROCESS FOR MANUFACTURING A CRYSTAL BY EPITAXIS ON A LIQUID METAL SUBSTRATE
US4598461A (en) * 1982-01-04 1986-07-08 General Electric Company Methods of making self-aligned power MOSFET with integral source-base short
US5528058A (en) * 1986-03-21 1996-06-18 Advanced Power Technology, Inc. IGBT device with platinum lifetime control and reduced gaw
DE59209470D1 (en) * 1991-06-24 1998-10-01 Siemens Ag Semiconductor component and method for its production
FR2681472B1 (en) * 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
US5298086A (en) * 1992-05-15 1994-03-29 United Solar Systems Corporation Method for the manufacture of improved efficiency tandem photovoltaic device and device manufactured thereby
US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
FR2714524B1 (en) * 1993-12-23 1996-01-26 Commissariat Energie Atomique PROCESS FOR MAKING A RELIEF STRUCTURE ON A SUPPORT IN SEMICONDUCTOR MATERIAL
JP3381443B2 (en) * 1995-02-02 2003-02-24 ソニー株式会社 Method for separating semiconductor layer from substrate, method for manufacturing semiconductor device, and method for manufacturing SOI substrate
US6573534B1 (en) * 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
FR2738671B1 (en) * 1995-09-13 1997-10-10 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS WITH SEMICONDUCTOR MATERIAL
FR2744285B1 (en) * 1996-01-25 1998-03-06 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN FILM FROM AN INITIAL SUBSTRATE TO A FINAL SUBSTRATE
JP3520660B2 (en) * 1996-03-28 2004-04-19 アイシン・エィ・ダブリュ株式会社 Fluid transmission
KR100481994B1 (en) * 1996-08-27 2005-12-01 세이코 엡슨 가부시키가이샤 Stripping method, transfer method of thin film device, and thin film device, thin film integrated circuit device and liquid crystal display device manufactured using the same
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP3324469B2 (en) * 1997-09-26 2002-09-17 信越半導体株式会社 Method for producing SOI wafer and SOI wafer produced by this method
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6033489A (en) * 1998-05-29 2000-03-07 Fairchild Semiconductor Corp. Semiconductor substrate and method of making same
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6455398B1 (en) * 1999-07-16 2002-09-24 Massachusetts Institute Of Technology Silicon on III-V semiconductor bonding for monolithic optoelectronic integration
US6500732B1 (en) * 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
KR100462980B1 (en) * 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 Chip scale surface mount package for semiconductor device and process of fabricating the same
US6602767B2 (en) * 2000-01-27 2003-08-05 Canon Kabushiki Kaisha Method for transferring porous layer, method for making semiconductor devices, and method for making solar battery
US6392290B1 (en) * 2000-04-07 2002-05-21 Siliconix Incorporated Vertical structure for semiconductor wafer-level chip scale packages
US6635534B2 (en) * 2000-06-05 2003-10-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy
US6586833B2 (en) * 2000-11-16 2003-07-01 Silicon Semiconductor Corporation Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6555405B2 (en) * 2001-03-22 2003-04-29 Uni Light Technology, Inc. Method for forming a semiconductor device having a metal substrate
US6649973B2 (en) * 2001-03-28 2003-11-18 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
EP1453096B1 (en) * 2001-12-04 2017-02-22 Shin-Etsu Handotai Co., Ltd. Method for producing a bonded wafer
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4158453B2 (en) * 2002-08-22 2008-10-01 株式会社デンソー Semiconductor device and manufacturing method thereof
US7033891B2 (en) * 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
DE10324751B4 (en) * 2003-05-30 2009-01-22 Infineon Technologies Ag Method for producing a semiconductor structure with a semiconductor substrate and semiconductor structure produced by this method
US6939781B2 (en) * 2003-06-27 2005-09-06 Freescale Semiconductor, Inc. Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate
US7666827B2 (en) * 2004-09-15 2010-02-23 The Procter & Gamble Company Wet wipe lotions comprising particulate material
US20060108635A1 (en) * 2004-11-23 2006-05-25 Alpha Omega Semiconductor Limited Trenched MOSFETS with part of the device formed on a (110) crystal plane
JP2008546189A (en) * 2005-05-26 2008-12-18 フェアチャイルド・セミコンダクター・コーポレーション Trench gate field effect transistor and method of manufacturing the same
TWI400757B (en) * 2005-06-29 2013-07-01 Fairchild Semiconductor Methods for forming shielded gate field effect transistors
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
TWI489557B (en) * 2005-12-22 2015-06-21 Vishay Siliconix High mobility p-channel trench and planar depletion-mode power metal-oxide semiconductor field-effect transistors
US7807536B2 (en) * 2006-02-10 2010-10-05 Fairchild Semiconductor Corporation Low resistance gate for power MOSFET applications and method of manufacture
KR101447048B1 (en) * 2007-04-20 2014-10-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing soi substrate and semiconductor device
US8101500B2 (en) * 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4616408A (en) * 1982-11-24 1986-10-14 Hewlett-Packard Company Inversely processed resistance heater
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6468923B1 (en) * 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
US20040140479A1 (en) * 2003-01-10 2004-07-22 Takeshi Akatsu Compliant substrate for a heteroepitaxial structure and method for making same

Also Published As

Publication number Publication date
US20100052046A1 (en) 2010-03-04
TW200710991A (en) 2007-03-16
WO2007015951A2 (en) 2007-02-08
US7635637B2 (en) 2009-12-22
KR20080042833A (en) 2008-05-15
AT504591A2 (en) 2008-06-15
JP2009503853A (en) 2009-01-29
CN101233603A (en) 2008-07-30
DE112006001943T5 (en) 2008-05-29
US20070020884A1 (en) 2007-01-25

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