WO2007028541A1 - Chip carrying group - Google Patents

Chip carrying group Download PDF

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Publication number
WO2007028541A1
WO2007028541A1 PCT/EP2006/008528 EP2006008528W WO2007028541A1 WO 2007028541 A1 WO2007028541 A1 WO 2007028541A1 EP 2006008528 W EP2006008528 W EP 2006008528W WO 2007028541 A1 WO2007028541 A1 WO 2007028541A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
carrier
assembly according
positioning means
carrier assembly
Prior art date
Application number
PCT/EP2006/008528
Other languages
German (de)
French (fr)
Inventor
Manfred Herz
Goran Pandza
Original Assignee
Ic-Haus Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ic-Haus Gmbh filed Critical Ic-Haus Gmbh
Publication of WO2007028541A1 publication Critical patent/WO2007028541A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a chip carrier assembly according to the preamble of claim 1, which has a carrier and at least one chip mountable on the carrier.
  • Chip mounting methods are known in which a chip is adhesively bonded or soldered to the back side on a carrier, or in which the attachment takes place via contact surfaces on the top side in flip-chip technology.
  • a disadvantage of these conventional chip mounting methods is the fact that chips can only be placed on the carrier with a settling accuracy of approximately 10 .mu.m. If the chip is fastened to the carrier by means of an adhesive, further shifts of the chip with respect to the carrier can take place during curing of the adhesive so that the chip can be displaced 20 to 30 ⁇ m in relation to the previously indicated space on the carrier during assembly. In the flip-chip technique, there is a shift in the melting of the solder joints or in the curing of the conductive adhesive. These shifting inaccuracies can not be avoided by the use of known image processing mechanisms and precision machines.
  • the invention is therefore an object of the invention to provide a chip carrier assembly in which a chip to be mounted with a higher precision, ie placement accuracy, are mounted on a support can, as was possible with conventional techniques.
  • Higher precision or placement accuracy means that the chip is reproducibly offset in its end position relative to a predetermined reference of the support surface by less than 20 microns, preferably even by a few microns.
  • a core idea of the invention is to achieve a very high placement accuracy when mounting a chip on the carrier by means of mechanical guides, which are formed at least on the surface of the carrier, and / y pder to be mounted chips.
  • a chip carrier assembly which has a carrier and at least one chip mountable on the carrier.
  • the chip may be conventional electronic, optoelectronic or magnetic circuits.
  • the carrier and / or the chip has at least one mechanical positioning device, which enables precise mounting of the at least one chip on the carrier.
  • precise assembly refers to the final positional accuracy with which a chip can be placed on a predetermined region of the support. Thanks to the invention, a significantly higher placement accuracy can be achieved than with conventional assembly methods.
  • Positioning device which fixes at least one edge of the male chip.
  • the positioning means of the carrier at least one elevation, which leads to the edge of the assembly of the chip.
  • the positioning means may comprise three elevations offset by 120 ° or a plurality of arcuate elevations, wherein the arcuate elevations are adapted to the circular cross-section of the chip.
  • the positioning device of the carrier may have at least two projections which are arranged at a predetermined distance from each other and each guide a chip edge during the assembly of the chip.
  • elevations may have a circular, elliptical or quadrangular cross section, i. H. Base area have. Any other base surfaces are conceivable.
  • the positioning device may also form a recess in the surface of the carrier, whose area of the cross-sectional area of the chip substantially equivalent. During assembly of the chip, the inner surface of the recess leads the outer surface of the chip.
  • Positioning has accuracy
  • the chip also has a positioning device which is complementary to the positioning means of the carrier.
  • the higher Absetzgenaumaschine is achieved by the fact that the leadership and alignment of the chip does not take place over the chip edges on the positioning means of the carrier, but on their own positioning.
  • the at least one positioning device of the carrier comprises at least one cavity and the positioning device of the chip comprises at least one cavity-complementary projection, which engages in the assembled state in the cavity.
  • Positioning means of the carrier at least one elevation and the positioning means of the chip has at least one complementary cavity, which receives the elevation of the carrier in the mounted state.
  • the cavity may be disposed either in or on the surface of the carrier or the chip.
  • a cavity is to be formed on the surface of the carrier or of the chip, then respectively four square-shaped elevations form such a cavity.
  • the positioning means of the carrier and / or the chip are at least partially formed electrically or optically conductive, in order to additionally serve as a conductor connection in this way.
  • the elevations are preferably 20 to 40 microns high.
  • the elevations preferably have steep edges or side surfaces.
  • FIG. 1 is a perspective view of an exemplary chip carrier assembly, wherein the carrier and chip are shown separated from each other,
  • Fig. 2 is a sectional view of that shown in Fig. 1
  • Chip carrier assembly along the lines AA 'and B- B', in which the positioning means of the chip is inserted into the positioning means of the carrier, and 3 shows an alternative chip carrier assembly in which only the carrier has a positioning device.
  • Fig. 2 shows a generally designated 5
  • Chip carrier assembly comprising a chip 10 and a carrier 20.
  • the assembly shown in Fig. 2 shows the chip 10 just before placing on the carrier 20.
  • the carrier 20 may be made of silicon, glass or of a material whose temperature coefficient to the
  • both the chip 10 and the carrier 20 have positioning devices.
  • the positioning means of the chip 10 is formed by protrusions 12 and 14 on a surface of the chip.
  • the cross section of the elevations 12 and 14, for example, rectangular, as shown in perspective in Fig. 1.
  • at least two elevations 12 and 14 are provided on the chip 10.
  • the two elevations 12 and 14 are located on opposite sides of the chip 10, but with a distance from the respective chip edge.
  • On a surface of the carrier 20 are to the projections 12 and 14 of the chip 10 complementary rectangular cavities 30 and 40, as shown in Fig. 1.
  • the cavities are each formed by four elevations, each preferably rectangular
  • the cavity 40 is formed by the elevations 41 to 44, as shown in particular in Fig. 1, whereas the cavity 30 is formed by the four elevations 31 to 34.
  • the cavities 30 and 40 have substantially the same cross section as the elevations 12 and 14 on the chip 10.
  • the cavities 30 and 40 are slightly larger in cross section than the cross sections of the elevations 12 and 14 dimensioned so that the projections 12 and 14 can be inserted into the cavities 30 and 40 with a small clearance.
  • the chip 10 can be bonded to the carrier 20, for example by means of a preferably electrically conductive adhesive, which is filled into the cavities 30 and 40. It is also conceivable to solder the elevations 12 and 14 of the chip with the cavities 30 and 40 forming elevations.
  • the protrusion 41 which is part of the cavity 40, is made of an electrically conductive material.
  • the elevation 41 can thus serve as a conductor connection for a conductor, which in the present example is shown as a flat strip 50.
  • the protrusions 12 and 14, which serve as positioning means of the chip 10 may be made of electrically or optically conductive material to form pads for external and / or internal chip lines.
  • an optical sensor 60 which contains a plurality of photodetectors, is formed on the chip 10.
  • the sensor 60 and the protrusions 12 and 14 are arranged on the same surface of the chip 10.
  • Fig. 2 shows is between the cavities 30 and 40 and / or on the opposite side of the carrier 20, a structure, aperture and / or a filter 70 (not shown in Fig. 1) applied to the surface of the carrier, thanks to the positioning technique used precisely with respect to the sensor 60 of the chip can be positioned.
  • the chip 10 equipped with mechanical positioning devices can be mounted very precisely on the support 20 both manually and in appropriately designed automated assembly systems, regardless of the placement accuracy of the placement system used.
  • a plurality of cavities may also be formed on the carrier 20 and a plurality of elevations complementary thereto may be formed on the carrier. It is also conceivable to arrange several chips next to each other on a carrier.
  • FIG. 3 shows an alternative chip carrier assembly 100 in which, for example, a chip 80 and a chip 85 are mounted on a carrier 90.
  • positioning devices 92 and 94 are arranged on only one surface of the carrier 90.
  • four elevations are arranged on the support 90, which form a lateral guide of a rectangular cross-section, for example, chip 80.
  • two elevations 92, 94 are shown in FIG.
  • the elevation 94 serves both as lateral guidance of a chip edge of the chip 80 and as guidance of an edge of the further chip 85.
  • a photodiode with an aperture and / or a filter 110 or 112 is respectively arranged on the chips 80 and 85.
  • the height of the elevations 92 and 94 is for example 20 to 40 microns.
  • the complementary positioning means can be formed on the support 90 by an annular ridge. It is also conceivable that in the surface of the carrier 90 e / Lne circular recess may be provided, in which the circular chip can be used.

Abstract

The invention relates to a chip carrying group comprising a carrier (20) and at least one chip (10) mountable thereon. Said carrier and/or chip are provided with at least one positioning device (12, 14; 31, 34; 41, 42) which enables the chip to be accurately mounted on the carrier. Said invention makes it possible to attain a high accuracy on at least one support and/or chip surface when mounting the chip on the carrier by means of said mechanical guides.

Description

Chipträgerbaugruppe Chip carrier assembly
Beschreibungdescription
Die Erfindung betrifft eine Chipträgerbaugruppe gemäß dem Oberbegriff des Anspruchs 1, welche einen Träger und wenigstens einen auf dem Träger montierbaren Chip aufweist.The invention relates to a chip carrier assembly according to the preamble of claim 1, which has a carrier and at least one chip mountable on the carrier.
Es sind Chipmontageverfahren bekannt, bei denen ein Chip mit der Rückseite auf einem Träger aufgeklebt oder daran festgelötet wird, oder bei denen die Befestigung über Kontaktflächen an der Oberseite in Flip-Chip-Technik erfolgt. Ein Nachteil dieser herkömmlichen Chipmontageverfahren ist darin zu sehen, dass Chips nur mit einer Absetzgenauigkeit von etwa 10 μm auf den Träger aufgesetzt werden können. Wird der Chip mittels eines Klebstoffs an dem Träger befestigt, können beim Aushärten des Klebers weitere Verschiebungen des Chips bezüglich des Trägers erfolgen, so dass der Chip bei der Montage 20 bis 30 μm gegenüber dem vorbezeichneten Platz auf dem Träger verschoben sein kann. Bei der Flip-Chip-Technik erfolgt eine Verschiebung beim Aufschmelzen der Lotverbindungen oder beim Aushärten des leitfähigen Klebers. Diese Verschiebeungenauigkeiten lassen sich auch durch den Einsatz bekannter Bildverarbeitungsmechanismen und Präzisionsmaschinen nicht vermeiden.Chip mounting methods are known in which a chip is adhesively bonded or soldered to the back side on a carrier, or in which the attachment takes place via contact surfaces on the top side in flip-chip technology. A disadvantage of these conventional chip mounting methods is the fact that chips can only be placed on the carrier with a settling accuracy of approximately 10 .mu.m. If the chip is fastened to the carrier by means of an adhesive, further shifts of the chip with respect to the carrier can take place during curing of the adhesive so that the chip can be displaced 20 to 30 μm in relation to the previously indicated space on the carrier during assembly. In the flip-chip technique, there is a shift in the melting of the solder joints or in the curing of the conductive adhesive. These shifting inaccuracies can not be avoided by the use of known image processing mechanisms and precision machines.
Der Erfindung liegt demzufolge die Aufgabe zugrunde, eine Chipträgerbaugruppe zu schaffen, bei der ein zu montierender Chip mit einer höheren Präzision, d. h. Platzierungsgenauigkeit, auf einem Träger montiert werden kann, als dies mit herkömmlichen Techniken möglich war. Höhere Präzision oder Platzierungsgenauigkeit bedeutet, dass der Chip in seiner Endposition relativ zu einer vorbestimmten Referenz der Trägerfläche reproduzierbar um weniger als 20 μm, vorzugsweise sogar nur um wenige μm versetzt ist.The invention is therefore an object of the invention to provide a chip carrier assembly in which a chip to be mounted with a higher precision, ie placement accuracy, are mounted on a support can, as was possible with conventional techniques. Higher precision or placement accuracy means that the chip is reproducibly offset in its end position relative to a predetermined reference of the support surface by less than 20 microns, preferably even by a few microns.
Ein Kerngedanke der Erfindung ist darin zu sehen, mit Hilfe mechanischer Führungen, die zumindest an der Oberfläche des Trägers ,und/ypder zu montierenden Chips ausgebildet sind, eine sehr hohe Platzierungsgenauigkeit bei der Montage eines Chips auf dem Träger zu erreichen.A core idea of the invention is to achieve a very high placement accuracy when mounting a chip on the carrier by means of mechanical guides, which are formed at least on the surface of the carrier, and / y pder to be mounted chips.
Das oben genannte technische Problem wird mit den Merkmalen des Anspruchs 1 gelöst.The above technical problem is solved with the features of claim 1.
Danach ist eine Chipträgerbaugruppe vorgesehen, die einen Träger und wenigstens einen auf dem Träger montierbaren Chip aufweist. Bei dem Chip kann es sich um herkömmliche elektronische, optoelektronische oder magnetische Schaltkreise handeln.Thereafter, a chip carrier assembly is provided which has a carrier and at least one chip mountable on the carrier. The chip may be conventional electronic, optoelectronic or magnetic circuits.
Der Träger und/oder der Chip weist wenigstens eine mechanische Positionierungseinrichtung auf, die eine präzise Montage des wenigstens einen Chips auf dem Träger ermöglicht. Wie bereits oben ausgeführt, bezieht sich der Ausdruck „präzise Montage" auf die endgültige Lagegenauigkeit, mit der ein Chip auf einem vorbestimmten Bereich des Trägers platziert werden kann. Dank der Erfindung kann eine deutliche höhere Platzierungsgenauigkeit als bei herkömmlichen Montageverfahren erzielt werden.The carrier and / or the chip has at least one mechanical positioning device, which enables precise mounting of the at least one chip on the carrier. As already stated above, the term "precise assembly" refers to the final positional accuracy with which a chip can be placed on a predetermined region of the support. Thanks to the invention, a significantly higher placement accuracy can be achieved than with conventional assembly methods.
Vorteilhafte Weiterbildungen sind Gegenstand der Unteransprüche . Zunächst werden Ausführungsbeispiele angeführt, bei denen lediglich der Träger eine mechanischeAdvantageous developments are the subject of the dependent claims. First, embodiments are given, in which only the carrier is a mechanical
Positionierungseinrichtung aufweist, die wenigstens einen Rand des aufzunehmenden Chips fixiert.Positioning device which fixes at least one edge of the male chip.
Bei einer bevorzugten Ausführungsform weist die Positionierungseinrichtung des Trägers wenigstens eine Erhebung auf, die bei der Montage des Chips dessen Rand führt. Wenn der Chip beispielsweise einen kreisförmigen Querschnitt aufweist, kann die Positionierungseinrichtung drei um 120° versetzte Erhebungen oder mehrere bogenförmige Erhebungen darstellen, wobei die bogenförmigen Erhebungen an den kreisförmigen Querschnitt des Chips angepasst sind.In a preferred embodiment, the positioning means of the carrier at least one elevation, which leads to the edge of the assembly of the chip. For example, if the chip has a circular cross-section, the positioning means may comprise three elevations offset by 120 ° or a plurality of arcuate elevations, wherein the arcuate elevations are adapted to the circular cross-section of the chip.
Bei einer bevorzugten Ausführungsform kann dieIn a preferred embodiment, the
Querschnittsfläche des Chips viereckig sein. In diesem Fall kann die Positionierungseinrichtung des Trägers mindestens zwei in einem vorbestimmten Abstand zueinander angeordnete Erhebungen aufweisen, die bei der Montage des Chips jeweils eine Chipkante führen.Cross sectional area of the chip be square. In this case, the positioning device of the carrier may have at least two projections which are arranged at a predetermined distance from each other and each guide a chip edge during the assembly of the chip.
Diese Erhebungen können einen kreisförmigen, elliptischen oder viereckigen Querschnitt, d. h. Grundfläche aufweisen. Beliebig andere Grundflächen sind denkbar.These elevations may have a circular, elliptical or quadrangular cross section, i. H. Base area have. Any other base surfaces are conceivable.
Die Verwendung einzelner, im Abstand zueinander angeordneter Erhebungen hat gegenüber einem geschlossenen Positionierungsrahmen den Vorteil, dass die benötigte Menge an Material, vorzugsweise Gold, deutlich reduziert werden kann. Zudem können elektrische Leiterbahnen direkt zwischen den Erhebungen zum Chip geführt werden.The use of individual, spaced-apart elevations over a closed positioning frame has the advantage that the required amount of material, preferably gold, can be significantly reduced. In addition, electrical conductors can be routed directly between the surveys to the chip.
Alternativ kann die Positionierungseinrichtung auch eine Aussparung in der Oberfläche des Trägers bilden, deren Fläche der Querschnittsfläche des Chips im Wesentlichen entspricht. Bei der Montage des Chips führt die Innenfläche der Aussparung die Außenfläche des Chips.Alternatively, the positioning device may also form a recess in the surface of the carrier, whose area of the cross-sectional area of the chip substantially equivalent. During assembly of the chip, the inner surface of the recess leads the outer surface of the chip.
Nunmehr werden Ausführungsbeispiele erwähnt, bei denen sowohl der Träger als auch der Chip lokale Positionierungseinrichtungen aufweisen.Embodiments are now mentioned in which both the carrier and the chip have local positioning devices.
Um zu vermeiden, dass der Sägeprozess beim Aussägen der Chips aus einer Siliziumscheibe Einfluss auf dieIn order to avoid that the sawing process with the cutting out of the chips from a silicon disk influence on the
Positioniergenauigkeit hat, weist auch der Chip eine Positionierungseinrichtung auf, die zu der Positionierungseinrichtung des Trägers komplementär ausgebildet ist. Die höhere Absetzgenauigkeit wird dadurch erreicht, dass die Führung und Ausrichtung des Chips nicht über dessen Chipkanten an der Positionierungseinrichtung des Trägers, sondern über eigene Positioniermittel erfolgt.Positioning has accuracy, the chip also has a positioning device which is complementary to the positioning means of the carrier. The higher Absetzgenauigkeit is achieved by the fact that the leadership and alignment of the chip does not take place over the chip edges on the positioning means of the carrier, but on their own positioning.
Vorzugsweise enthält die wenigstens eine Positionierungseinrichtung des Trägers wenigstens einen Hohlraum und die Positionierungseinrichtung des Chips wenigstens eine zum Hohlraum komplementäre Erhebung, die im montierten Zustand in den Hohlraum eingreift.Preferably, the at least one positioning device of the carrier comprises at least one cavity and the positioning device of the chip comprises at least one cavity-complementary projection, which engages in the assembled state in the cavity.
Alternativ ist es denkbar, dass die wenigstens eineAlternatively, it is conceivable that the at least one
Positionierungseinrichtung des Trägers wenigstens eine Erhebung und die Positionierungseinrichtung des Chips wenigstens einen dazu komplementären Hohlraum aufweist, der im montierten Zustand die Erhebung des Trägers aufnimmt.Positioning means of the carrier at least one elevation and the positioning means of the chip has at least one complementary cavity, which receives the elevation of the carrier in the mounted state.
Der Hohlraum kann entweder in oder auf der Oberfläche des Trägers oder des Chips angeordnet sein.The cavity may be disposed either in or on the surface of the carrier or the chip.
Soll beispielsweise ein Hohlraum an der Oberfläche des Trägers oder des Chips gebildet werden, so können jeweils vier viereckförmige Erhebungen einen solchen Hohlraum bilden.If, for example, a cavity is to be formed on the surface of the carrier or of the chip, then respectively four square-shaped elevations form such a cavity.
Gemäß einer vorteilhaften Weiterbildung sind die Positionierungseinrichtungen des Trägers und/oder des Chips wenigstens teilweise elektrisch oder optisch leitfähig ausgebildet, um auf diese Weise zusätzlich als Leiteranschluss dienen zu können.According to an advantageous development, the positioning means of the carrier and / or the chip are at least partially formed electrically or optically conductive, in order to additionally serve as a conductor connection in this way.
Um eine zuverlässige und präzise Positionierung eines Chips auf einem Träger ermöglichen zu können, sind die Erhebungen vorzugsweise 20 bis 40 μm hoch. Die Erhebungen weisen vorzugsweise steile Kanten oder Seitenflächen auf.In order to enable a reliable and precise positioning of a chip on a carrier, the elevations are preferably 20 to 40 microns high. The elevations preferably have steep edges or side surfaces.
Gemäß einer zweckmäßigen Ausführungsform können die auf die Chips und/oder den Träger aufgebrachten höcker- oder ballförmigen Kontakte, die aus Gold oder schmelzbarenAccording to an advantageous embodiment, applied to the chips and / or the carrier humped or ball-shaped contacts made of gold or fusible
Legierungen bestehen können und auch als Bumps oder Balls •bekannt sind, welche unter Verwendung der für Herstellung von elektrischen Verbindungen oder Kontakten verwendeten herkömmlichen Techniken aufgebracht werden sind, als mechanische Positionierungseinrichtungen genützt werden.May consist alloys, and also known as bumps or balls • which are to be applied using the conventional techniques used for making electrical connections or contacts, be utilized as a mechanical positioning means.
Die Erfindung wird an Hand mehrerer Ausführungsbeispiele in Verbindung mit den beiliegenden Zeichnungen näher erläutert. Es zeigen:The invention will be explained in more detail with reference to several embodiments in conjunction with the accompanying drawings. Show it:
Fig. 1 eine perspektivische Ansicht einer beispielhaften Chipträgerbaugruppe, wobei Träger und Chip voneinander getrennt dargestellt sind, Fig. 2 eine Schnittansicht der in Fig. 1 dargestellten1 is a perspective view of an exemplary chip carrier assembly, wherein the carrier and chip are shown separated from each other, Fig. 2 is a sectional view of that shown in Fig. 1
Chipträgerbaugruppe entlang der Linien A-A' und B- B' , bei der die Positionierungseinrichtung des Chips in die Positionierungseinrichtung des Trägers eingeführt wird, und Fig. 3 eine alternative Chipträgerbaugruppe, bei der lediglich der Träger eine Positionierungseinrichtung aufweist .Chip carrier assembly along the lines AA 'and B- B', in which the positioning means of the chip is inserted into the positioning means of the carrier, and 3 shows an alternative chip carrier assembly in which only the carrier has a positioning device.
Fig. 2 zeigt eine allgemein mit 5 bezeichneteFig. 2 shows a generally designated 5
Chipträgerbaugruppe, die einen Chip 10 sowie einen Träger 20 aufweist. Die in Fig. 2 dargestellte Baugruppe zeigt den Chip 10 kurz vor dem Aufsetzen auf den Träger 20. Der Träger 20 kann aus Silizium, Glas oder aus einem Material hergestellt sein, dessen Temperaturkoeffizient an denChip carrier assembly comprising a chip 10 and a carrier 20. The assembly shown in Fig. 2 shows the chip 10 just before placing on the carrier 20. The carrier 20 may be made of silicon, glass or of a material whose temperature coefficient to the
Temperaturkoeffizient des Chiphalbleitermaterials angepasst ist.Temperature coefficient of the chip semiconductor material is adjusted.
Bei der in Fig. 2 gezeigten Chipträgerbaugruppe 5 weisen sowohl der Chip 10 als auch der Träger 20 Positionierungseinrichtungen auf. Die Positionierungseinrichtung des Chips 10 wird durch Erhebungen 12 und 14 an einer Oberfläche des Chips gebildet. Der Querschnitt der Erhebungen 12 und 14 ist beispielsweise rechteckig, wie es in Fig. 1 perspektivisch dargestellt ist. Vorzugsweise sind wenigstens zwei Erhebungen 12 und 14 auf dem Chip 10 vorgesehen. Wie in Fig. 1 dargestellt, befinden sich die beiden Erhebungen 12 und 14 an gegenüberliegenden Seiten des Chips 10, allerdings mit einem Abstand zur jeweiligen Chipkante. Auf einer Oberfläche des Trägers 20 befinden sich zu den Erhebungen 12 und 14 des Chips 10 komplementäre rechteckförmige Hohlräume 30 und 40, wie in Fig. 1 gezeigt. Die Hohlräume werden jeweils durch vier Erhebungen gebildet, die jeweils vorzugsweise rechteckförmigenIn the chip carrier assembly 5 shown in FIG. 2, both the chip 10 and the carrier 20 have positioning devices. The positioning means of the chip 10 is formed by protrusions 12 and 14 on a surface of the chip. The cross section of the elevations 12 and 14, for example, rectangular, as shown in perspective in Fig. 1. Preferably, at least two elevations 12 and 14 are provided on the chip 10. As shown in Fig. 1, the two elevations 12 and 14 are located on opposite sides of the chip 10, but with a distance from the respective chip edge. On a surface of the carrier 20 are to the projections 12 and 14 of the chip 10 complementary rectangular cavities 30 and 40, as shown in Fig. 1. The cavities are each formed by four elevations, each preferably rectangular
Querschnitt aufweisen. So wird beispielsweise der Hohlraum 40 durch die Erhebungen 41 bis 44 gebildet, wie dies insbesondere in Fig. 1 dargestellt ist, wohingegen der Hohlraum 30 durch die vier Erhebungen 31 bis 34 gebildet wird. Wie insbesondere Fig. 1 zeigt, weisen die Hohlräume 30 und 40 im Wesentlichen den gleichen Querschnitt auf, wie die Erhebungen 12 und 14 auf dem Chip 10. Die Hohlräume 30 und 40 sind im Querschnitt geringfügig größer als die Querschnitte der Erhebungen 12 und 14 bemessen, so dass die Erhebungen 12 und 14 mit geringem Spiel in die Hohlräume 30 und 40 eingeführt werden können. Mit Hilfe derartig hergestellter Positionierungseinrichtungen ist es möglich, die Platzierungsgenauigkeit des Chips 10 auf dem Träger 20 drastisch gegenüber herkömmlichen Montageverfahren zu erhöhen, d. h. bis in den μm-Bereich.Have cross-section. Thus, for example, the cavity 40 is formed by the elevations 41 to 44, as shown in particular in Fig. 1, whereas the cavity 30 is formed by the four elevations 31 to 34. As shown particularly in FIG. 1, the cavities 30 and 40 have substantially the same cross section as the elevations 12 and 14 on the chip 10. The cavities 30 and 40 are slightly larger in cross section than the cross sections of the elevations 12 and 14 dimensioned so that the projections 12 and 14 can be inserted into the cavities 30 and 40 with a small clearance. With the aid of positioning devices produced in this way, it is possible to drastically increase the placement accuracy of the chip 10 on the carrier 20 compared to conventional assembly methods, ie, into the μm range.
Der Chip 10 kann beispielsweise mittels eines vorzugsweise elektrisch leitfähigen Klebers, welcher in die Hohlräume 30 und 40 eingefüllt wird, auf dem Träger 20 verklebt werden. Denkbar ist auch, die Erhebungen 12 und 14 des Chips mit den die Hohlräume 30 und 40 bildenden Erhebungen zu verlöten .The chip 10 can be bonded to the carrier 20, for example by means of a preferably electrically conductive adhesive, which is filled into the cavities 30 and 40. It is also conceivable to solder the elevations 12 and 14 of the chip with the cavities 30 and 40 forming elevations.
In dem vorliegenden Beispiel ist die Erhebung 41, welche Bestandteil des Hohlraums 40 ist, aus einem elektrisch leitfähigen Material hergestellt. Die Erhebung 41 kann somit als Leiteranschluss für einen Leiter, der im vorliegenden Beispiel als Flachband 50 dargestellt ist, dienen. In ähnlicher Weise können die Erhebungen 12 und 14, die als Positionierungseinrichtungen des Chips 10 dienen, aus elektrisch oder optisch leitfähigem Material bestehen, um Anschlussflächen für externe und/oder interne Chipleitungen zu bilden.In the present example, the protrusion 41, which is part of the cavity 40, is made of an electrically conductive material. The elevation 41 can thus serve as a conductor connection for a conductor, which in the present example is shown as a flat strip 50. Similarly, the protrusions 12 and 14, which serve as positioning means of the chip 10, may be made of electrically or optically conductive material to form pads for external and / or internal chip lines.
Auf dem Chip 10 ist beispielsweise ein optischer Sensor 60, der mehrere Fotodetektoren enthält, ausgebildet. Der Sensor 60 und die Erhebungen 12 und 14 sind auf der gleichen Oberfläche des Chips 10 angeordnet. Wie Fig. 2 zeigt, ist zwischen den Hohlräumen 30 und 40 und/oder auf der gegenüberliegenden Seite des Trägers 20 eine Struktur, Blende und/oder ein Filter 70 (in Fig. 1 nicht dargestellt) auf der Oberfläche des Trägers aufgebracht, die dank der verwendeten Positionierungstechnik präzise gegenüber dem Sensor 60 des Chips positioniert werden kann.On the chip 10, for example, an optical sensor 60, which contains a plurality of photodetectors, is formed. The sensor 60 and the protrusions 12 and 14 are arranged on the same surface of the chip 10. As Fig. 2 shows is between the cavities 30 and 40 and / or on the opposite side of the carrier 20, a structure, aperture and / or a filter 70 (not shown in Fig. 1) applied to the surface of the carrier, thanks to the positioning technique used precisely with respect to the sensor 60 of the chip can be positioned.
An dieser Stelle sei darauf hingewiesen, dass der mit mechanischen Positionierungseinrichtungen ausgestattete Chip 10 sowohl manuell als auch in entsprechend ausgebildeten automatisierten Bestückungsanlagen sehr präzise auf dem Träger 20 montiert werden kann, und zwar unabhängig von der Absetzgenauigkeit der verwendeten Bestückungsanlage .It should be noted at this point that the chip 10 equipped with mechanical positioning devices can be mounted very precisely on the support 20 both manually and in appropriately designed automated assembly systems, regardless of the placement accuracy of the placement system used.
Wie Fig. 1 weiter zeigt, können auf dem Träger 20 auch mehrere Hohlräumen und auf dem Chip mehrere dazu komplementäre Erhebungen ausgebildet sein. Ebenfalls ist es denkbar, auf einem Träger mehrere Chips nebeneinander anzuordnen.As FIG. 1 further shows, a plurality of cavities may also be formed on the carrier 20 and a plurality of elevations complementary thereto may be formed on the carrier. It is also conceivable to arrange several chips next to each other on a carrier.
Fig. 3 zeigt eine alternative Chipträgerbaugruppe 100, bei der beispielsweise ein Chip 80 und ein Chip 85 auf einem Träger 90 montiert sind. Im Unterschied zu der in den Figuren 1 und 2 dargestellten Chipträgerbaugruppe sind lediglich auf einer Oberfläche des Trägers 90 Positionierungseinrichtungen 92 und 94 angeordnet. Vorzugsweise sind vier Erhebungen auf dem Träger 90 angeordnet, die eine seitliche Führung eines beispielsweise im Querschnitt rechteckförmigen Chips 80 bilden. Im vorliegenden Beispiel sind in Fig. 3 zwei Erhebungen 92, 94 dargestellt. Die Erhebung 94 dient im vorliegenden Beispiel sowohl als seitliche Führung einer Chipkante des Chips 80 als auch als Führung einer Kante des weiteren Chips 85. Beispielsweise ist auf den Chips 80 und 85 jeweils eine Fotodiode mit Blende und/oder Filter 110 beziehungsweise 112 angeordnet. Die Höhe der Erhebungen 92 und 94 ist beispielsweise 20 bis 40 μm.FIG. 3 shows an alternative chip carrier assembly 100 in which, for example, a chip 80 and a chip 85 are mounted on a carrier 90. In contrast to the chip carrier assembly shown in FIGS. 1 and 2, positioning devices 92 and 94 are arranged on only one surface of the carrier 90. Preferably, four elevations are arranged on the support 90, which form a lateral guide of a rectangular cross-section, for example, chip 80. In the present example, two elevations 92, 94 are shown in FIG. In the present example, the elevation 94 serves both as lateral guidance of a chip edge of the chip 80 and as guidance of an edge of the further chip 85. For example, a photodiode with an aperture and / or a filter 110 or 112 is respectively arranged on the chips 80 and 85. The height of the elevations 92 and 94 is for example 20 to 40 microns.
Für den Fall, dass der Querschnitt des Chips 80 kreisförmig ist, kann die dazu komplementäre Positionierungseinrichtung auf dem Träger 90 durch einen ringförmigen Steg gebildet werden. Ferner ist denkbar, dass in der Oberfläche des Trägers 90 e/Lne kreisförmige Aussparung vorgesehen sein kann, in die der kreisförmige Chip eingesetzt werden kann. In the case that the cross section of the chip 80 is circular, the complementary positioning means can be formed on the support 90 by an annular ridge. It is also conceivable that in the surface of the carrier 90 e / Lne circular recess may be provided, in which the circular chip can be used.

Claims

Patentansprüche claims
1. Chipträgerbaugruppe umfassend einen Träger (20; 90) und wenigstens einen auf dem Träger montierbaren Chip (10; 80, 85), dadurch gekennzeichnet, .dass der Träger (20; 90) und/oder der Chip (10; 80, 85) wenigstens eine mechanische Positionierungseinrichtung (12, 14; 30, 40; 92, 94) aufweist, die eine präzise Montage des wenigstens einen Chips auf dem Träger ermöglicht .A chip carrier assembly comprising a carrier (20; 90) and at least one carrier mountable chip (10; 80,85), characterized in that the carrier (20; 90) and / or the chip (10,80,85 ) has at least one mechanical positioning device (12, 14, 30, 40, 92, 94) which enables a precise mounting of the at least one chip on the carrier.
2. Chipträgerbaugruppe nach Anspruch 1, dadurch gekennzeichnet, dass die Positionierungseinrichtung (92, 94) des Trägers (90) wenigstens eine Erhebung aufweist, die bei der2. chip carrier assembly according to claim 1, characterized in that the positioning means (92, 94) of the carrier (90) has at least one elevation, which in the
Montage des Chips dessen Rand führt.Mounting the chip whose edge leads.
3. Chipträgerbaugruppe nach Anspruch 1, dadurch gekennzeichnet, dass die Positionierungseinrichtung des Trägers (90) eine Aussparung in der Oberfläche des Trägers ist, deren Innenfläche die Außenfläche des Chips führt.3. chip carrier assembly according to claim 1, characterized in that the positioning means of the carrier (90) is a recess in the surface of the carrier, the inner surface of which leads to the outer surface of the chip.
4. Chipträgerbaugruppe nach Anspruch 1, dadurch gekennzeichnet, dass der Chip (90) einen viereckförmigen Querschnitt aufweist und die Positionierungseinrichtung des Trägers mindesten zwei in einem vorbestimmten Abstand zueinander angeordnete Erhebungen (92, 94) aufweist, die bei der Montage des Chips jeweils eine Chipkante führen . 4. chip carrier assembly according to claim 1, characterized in that the chip (90) has a quadrangular cross-section and the positioning means of the carrier at least two at a predetermined distance from each other arranged elevations (92, 94) which in each case a chip edge during assembly of the chip to lead .
5. Chipträgerbaugruppe nach Anspruch 2 oder 4, dadurch gekennzeichnet, dass die Erhebungen einen kreisförmigen, elliptischen, viereckigen oder kreisbogenförmigen Querschnitt haben.5. chip carrier assembly according to claim 2 or 4, characterized in that the elevations have a circular, elliptical, quadrangular or circular arc-shaped cross-section.
6. Chipträgerbaugruppe nach Anspruch 1, dadurch gekennzeichnet, dass der Chip (10) eine Positionierungseinrichtung (12, 14) aufweist, die zu der Positionierungseinrichtung (30, 40) des Trägers (20) komplementär ausgebildet ist.6. chip carrier assembly according to claim 1, characterized in that the chip (10) has a positioning device (12, 14) which is complementary to the positioning means (30, 40) of the carrier (20).
7. Chipträgerbaugruppe nach Anspruch 6, dadurch gekennzeichnet, dass die wenigstens eine Positionierungseinrichtung (30, 40) des Trägers wenigstens einen Hohlraum enthält und dass die Positionierungseinrichtung (12, 14) des Chips (10) wenigstens eine komplementäre Erhebung aufweist, die im montierten Zustand in den Hohlraum (30, 40) eingreift.7. chip carrier assembly according to claim 6, characterized in that the at least one positioning means (30, 40) of the carrier comprises at least one cavity and that the positioning means (12, 14) of the chip (10) has at least one complementary elevation, in the mounted state in the cavity (30, 40) engages.
8. Chipträgerbaugruppe nach Anspruch 6, dadurch gekennzeichnet, dass die wenigstens eine Positionierungseinrichtung des Trägers (20) wenigstens eine Erhebung aufweist und dass die Positionierungseinrichtung des Chips (10) wenigstens einen komplementären Hohlraum aufweist, der im montierten Zustand die Erhebung aufnimmt.8. chip carrier assembly according to claim 6, characterized in that the at least one positioning means of the carrier (20) has at least one elevation and that the positioning means of the chip (10) has at least one complementary cavity which receives the survey in the mounted state.
9. Chipträgerbaugruppe nach Anspruch 7 oder 8, dadurch gekennzeichnet, dass der Hohlraum (30, 40) in oder auf der Oberfläche des Trägers (20) oder des Chips (10) angeordnet ist.9. chip carrier assembly according to claim 7 or 8, characterized in that the cavity (30, 40) in or on the surface of the carrier (20) or the chip (10) is arranged.
10. Chipträgerbaugruppe nach Anspruch 9, dadurch gekennzeichnet, dass jeweils vier viereckförmige Erhebungen (31-34; 41-44) einen Hohlraum (30, 40) auf der Oberfläche des Trägers (20) oder Chips (10) bilden.10. Chip carrier assembly according to claim 9, characterized in that in each case four quadrangular elevations (31-34; 41-44) form a cavity (30, 40) on the surface of the carrier (20) or chips (10).
11. Chipträgerbaugruppe nach einem der Ansprüche 1 bis 10, dadurch gekennzeichnet, dass die Positionierungseinrichtung des Trägers und/oder des Chips wenigstens teilweise elektrisch -oder optisch leitfähig sind und als Leiteranschluss dienen.11. chip carrier assembly according to one of claims 1 to 10, characterized in that the positioning means of the carrier and / or the chip are at least partially electrically or optically conductive and serve as a conductor connection.
12. Chipträgerbaugruppe nach einem der Ansprüche 2 bis 11, dadurch gekennzeichnet, dass die Erhebungen 20 bis 40 μm hoch sind.12. chip carrier assembly according to one of claims 2 to 11, characterized in that the elevations are 20 to 40 microns high.
13. Chipträgerbaugruppe nach einem der Ansprüche 2 bis 12, dadurch gekennzeichnet, dass auf dem Chip und/oder dem Träger aufgebrachte höcker- oder ballförmige Kontakte als mechanische Positionierungseinrichtungen dienen . 13. chip carrier assembly according to one of claims 2 to 12, characterized in that on the chip and / or the carrier applied humped or ball-shaped contacts serve as mechanical positioning means.
PCT/EP2006/008528 2005-09-06 2006-08-31 Chip carrying group WO2007028541A1 (en)

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DE202005014073U DE202005014073U1 (en) 2005-09-06 2005-09-06 Chip e.g. electronic circuit, carrying assembly, has chip mountable on carrier, where carrier and chip have respective mechanical positioning units, which enable assembly of chip on carrier and are formed by elevations on chip and carrier
DE202005014073.2 2005-09-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8427839B2 (en) 2007-09-28 2013-04-23 Osram Opto Semiconductors Gmbh Arrangement comprising an optoelectronic component
CN113597137A (en) * 2021-08-10 2021-11-02 苏州维信电子有限公司 SMT (surface mount technology) component welding method and circuit board product

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT520857A1 (en) * 2018-02-08 2019-08-15 Friedrich Eibensteiner Dr Method for placing and soldering elements on component carriers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657207A (en) * 1995-03-24 1997-08-12 Packard Hughes Interconnect Company Alignment means for integrated circuit chips
US20020100971A1 (en) * 2000-12-27 2002-08-01 Shinji Honda Integrated circuit packages
US20030111727A1 (en) * 2001-12-18 2003-06-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device and printed wired board for mounting the same
DE10343065A1 (en) * 2003-09-16 2005-04-07 Siemens Ag Circuit board arrangement for mobile telephones and laptops comprises a circuit board layer, a component arranged on the circuit board layer, and a positioning element formed on the circuit board layer for fixing the component on the layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3721000B2 (en) * 1999-02-24 2005-11-30 ローム株式会社 Semiconductor device
DE10308871B3 (en) * 2003-02-28 2004-07-22 Infineon Technologies Ag Semiconductor chip for use in semiconductor chip stack in complex electronic circuit with surface structure for alignment of stacked semiconductor chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657207A (en) * 1995-03-24 1997-08-12 Packard Hughes Interconnect Company Alignment means for integrated circuit chips
US20020100971A1 (en) * 2000-12-27 2002-08-01 Shinji Honda Integrated circuit packages
US20030111727A1 (en) * 2001-12-18 2003-06-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device and printed wired board for mounting the same
DE10343065A1 (en) * 2003-09-16 2005-04-07 Siemens Ag Circuit board arrangement for mobile telephones and laptops comprises a circuit board layer, a component arranged on the circuit board layer, and a positioning element formed on the circuit board layer for fixing the component on the layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8427839B2 (en) 2007-09-28 2013-04-23 Osram Opto Semiconductors Gmbh Arrangement comprising an optoelectronic component
CN113597137A (en) * 2021-08-10 2021-11-02 苏州维信电子有限公司 SMT (surface mount technology) component welding method and circuit board product
CN113597137B (en) * 2021-08-10 2022-08-16 苏州维信电子有限公司 SMT (surface mount technology) component welding method and circuit board product

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