WO2007030343A3 - Silicided recessed silicon - Google Patents

Silicided recessed silicon Download PDF

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Publication number
WO2007030343A3
WO2007030343A3 PCT/US2006/033374 US2006033374W WO2007030343A3 WO 2007030343 A3 WO2007030343 A3 WO 2007030343A3 US 2006033374 W US2006033374 W US 2006033374W WO 2007030343 A3 WO2007030343 A3 WO 2007030343A3
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WO
WIPO (PCT)
Prior art keywords
silicon
trench
metals
metal
recessed
Prior art date
Application number
PCT/US2006/033374
Other languages
French (fr)
Other versions
WO2007030343A2 (en
Inventor
Hasan Nejad
Thomas A Figura
Gordon A Haller
Ravi Iyer
John Mark Meldrim
Justin Harnish
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to CN2006800394948A priority Critical patent/CN101297392B/en
Priority to JP2008529139A priority patent/JP4984177B2/en
Priority to EP06813796A priority patent/EP1929510A2/en
Publication of WO2007030343A2 publication Critical patent/WO2007030343A2/en
Publication of WO2007030343A3 publication Critical patent/WO2007030343A3/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Abstract

Methods and structures are provided for full silicidation of recessed silicon. Silicon (52) is provided within a trench (50). A mixture of metals (55) is provided over the silicon (52) in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon (52) within the trench (50) is allowed to fully silicide (56) without void formation, despite a relatively high aspect ratio for the trench (50). Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays (10).
PCT/US2006/033374 2005-09-01 2006-08-28 Silicided recessed silicon WO2007030343A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2006800394948A CN101297392B (en) 2005-09-01 2006-08-28 Silicided recessed silicon
JP2008529139A JP4984177B2 (en) 2005-09-01 2006-08-28 Silicified channel silicon
EP06813796A EP1929510A2 (en) 2005-09-01 2006-08-28 Silicided recessed silicon

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/219,303 2005-09-01
US11/219,303 US7557032B2 (en) 2005-09-01 2005-09-01 Silicided recessed silicon

Publications (2)

Publication Number Publication Date
WO2007030343A2 WO2007030343A2 (en) 2007-03-15
WO2007030343A3 true WO2007030343A3 (en) 2007-06-14

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PCT/US2006/033374 WO2007030343A2 (en) 2005-09-01 2006-08-28 Silicided recessed silicon

Country Status (8)

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US (3) US7557032B2 (en)
EP (1) EP1929510A2 (en)
JP (1) JP4984177B2 (en)
KR (1) KR100984469B1 (en)
CN (1) CN101297392B (en)
SG (3) SG165336A1 (en)
TW (1) TWI329351B (en)
WO (1) WO2007030343A2 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7349232B2 (en) * 2006-03-15 2008-03-25 Micron Technology, Inc. 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
KR100801078B1 (en) * 2006-06-29 2008-02-11 삼성전자주식회사 Non volatile memory integrate circuit having vertical channel and fabricating method thereof
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7858471B2 (en) 2006-09-13 2010-12-28 Micron Technology, Inc. Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery transistors and access transistors, and methods of fabricating an access device comprising access transistors in an access circuitry region and peripheral transistors in a peripheral circuitry region spaced from the access circuitry region
US7696057B2 (en) * 2007-01-02 2010-04-13 International Business Machines Corporation Method for co-alignment of mixed optical and electron beam lithographic fabrication levels
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8222159B2 (en) 2008-08-25 2012-07-17 Elpida Memory, Inc. Manufacturing method of semiconductor device
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
CN102054526B (en) * 2009-11-10 2012-10-31 中芯国际集成电路制造(上海)有限公司 Dynamic random access memory (DRAM)
US20110129991A1 (en) * 2009-12-02 2011-06-02 Kyle Armstrong Methods Of Patterning Materials, And Methods Of Forming Memory Cells
US20110223770A1 (en) * 2010-03-15 2011-09-15 Lam Research Corporation Nitride plasma etch with highly tunable selectivity to oxide
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8569810B2 (en) 2010-12-07 2013-10-29 International Business Machines Corporation Metal semiconductor alloy contact with low resistance
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9496357B2 (en) * 2011-07-22 2016-11-15 X-Fab Semiconductor Foundries Ag Semiconductor device
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
JP2013135029A (en) * 2011-12-26 2013-07-08 Elpida Memory Inc Semiconductor device manufacturing method
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
KR101901322B1 (en) 2012-02-28 2018-09-21 삼성전자주식회사 Variable resistive memory device
KR20130104200A (en) * 2012-03-13 2013-09-25 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US20140036565A1 (en) * 2012-08-02 2014-02-06 Nanya Technology Corporation Memory device and method of manufacturing memory structure
US9064745B2 (en) 2012-08-29 2015-06-23 International Business Machines Corporation Sublithographic width finFET employing solid phase epitaxy
US10103247B1 (en) 2017-10-17 2018-10-16 Globalfoundries Inc. Vertical transistor having buried contact, and contacts using work function metals and silicides
WO2020191068A1 (en) * 2019-03-20 2020-09-24 Tokyo Electron Limited Method of selectively forming metal silicides for semiconductor devices
US11088147B2 (en) 2019-06-26 2021-08-10 Micron Technology, Inc. Apparatus with doped surfaces, and related methods with in situ doping
DE102021203566A1 (en) 2021-04-12 2022-10-13 Robert Bosch Gesellschaft mit beschränkter Haftung MEMS switch with embedded metal contact

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0967643A2 (en) * 1998-06-22 1999-12-29 International Business Machines Corporation Low-resistance salicide fill for trench capacitors
US20020000608A1 (en) * 2000-06-02 2002-01-03 Hirofumi Harada Vertical MOS transistor and a method of manufacturing the same
US20020102848A1 (en) * 2000-12-07 2002-08-01 Advanced Micro Devices, Inc. Damascene nisi metal gate high-k transistor
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
US20020160557A1 (en) * 2001-04-28 2002-10-31 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
US20020187578A1 (en) * 2001-06-12 2002-12-12 Kwon Hong Method for manufacturing memory device
US20030170955A1 (en) * 2001-07-10 2003-09-11 Takahiro Kawamura Trench-gate semiconductor device and its manufacturing method
US20050153530A1 (en) * 2004-01-09 2005-07-14 International Business Machines Corporation Fet gate structure with metal gate electrode and silicide contact
US20070007571A1 (en) * 2005-07-06 2007-01-11 Richard Lindsay Semiconductor device with a buried gate and method of forming the same

Family Cites Families (286)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE755502A (en) 1969-09-09 1971-03-01 Basf Ag FORMYL-3-BUTANEDIOL-1,2 BISMONOCARBOXYLATES AND PROCESS FOR THEIR PREPARATION
US3731287A (en) 1971-07-02 1973-05-01 Gen Instrument Corp Single device memory system having shift register output characteristics
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4419809A (en) 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
DE3242113A1 (en) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart METHOD FOR PRODUCING A THIN DIELECTRIC INSULATION IN A SILICON SEMICONDUCTOR BODY
US4716131A (en) 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4570325A (en) * 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
JPS60202166A (en) 1984-03-26 1985-10-12 Toshiba Chem Corp Electrically conductive paint
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
GB8528967D0 (en) 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4983544A (en) * 1986-10-20 1991-01-08 International Business Machines Corporation Silicide bridge contact process
JPS6413290A (en) 1987-07-07 1989-01-18 Oki Electric Ind Co Ltd Semiconductor memory
US4776922A (en) 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
US4838991A (en) 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US5024959A (en) 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
US5497497A (en) 1989-11-03 1996-03-05 Compaq Computer Corp. Method and apparatus for resetting multiple processors using a common ROM
US5387555A (en) * 1992-09-03 1995-02-07 Harris Corporation Bonded wafer processing with metal silicidation
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JP2792211B2 (en) * 1990-07-06 1998-09-03 日本電気株式会社 Semiconductor storage device
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5053105A (en) 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5177027A (en) 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
US5064683A (en) * 1990-10-29 1991-11-12 Motorola, Inc. Method for polish planarizing a semiconductor substrate by using a boron nitride polish stop
DE4034612A1 (en) 1990-10-31 1992-05-07 Huels Chemische Werke Ag METHOD FOR PRODUCING ORGANOSILANES CONTAINING METHACRYLOXY OR ACRYLOXY GROUPS
IT1243919B (en) 1990-11-20 1994-06-28 Cons Ric Microelettronica PROCEDURE FOR OBTAINING PLANARIZED SUBMICHROMETRIC GROOVES IN INTEGRATED CIRCUITS REALIZED WITH ULSI TECHNOLOGY
US5122848A (en) 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5250450A (en) 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
JP2851962B2 (en) * 1992-01-21 1999-01-27 シャープ株式会社 Semiconductor read-only memory
JPH05343370A (en) 1992-06-10 1993-12-24 Toshiba Corp Forming method for fine pattern
US5330879A (en) 1992-07-16 1994-07-19 Micron Technology, Inc. Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
US5420819A (en) 1992-09-24 1995-05-30 Nonvolatile Electronics, Incorporated Method for sensing data in a magnetoresistive memory using large fractions of memory cell films for data storage
DE4236609A1 (en) 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
JP2884962B2 (en) * 1992-10-30 1999-04-19 日本電気株式会社 Semiconductor memory
US6042998A (en) * 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
US5645887A (en) * 1994-01-14 1997-07-08 Lg Semicon Co., Ltd. Method for forming platinum silicide plugs
JP3720064B2 (en) 1994-01-20 2005-11-24 株式会社ルネサステクノロジ Semiconductor integrated circuit
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
JP2658870B2 (en) 1994-04-22 1997-09-30 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
US5841611A (en) 1994-05-02 1998-11-24 Matsushita Electric Industrial Co., Ltd. Magnetoresistance effect device and magnetoresistance effect type head, memory device, and amplifying device using the same
US5495441A (en) * 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
JPH0855920A (en) 1994-08-15 1996-02-27 Toshiba Corp Manufacture of semiconductor device
JPH0855908A (en) 1994-08-17 1996-02-27 Toshiba Corp Semiconductor device
JP3469362B2 (en) 1994-08-31 2003-11-25 株式会社東芝 Semiconductor storage device
US5600153A (en) 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
US6175128B1 (en) 1998-03-31 2001-01-16 International Business Machines Corporation Process for building borderless bitline, wordline and DRAM structure and resulting structure
US5539229A (en) 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack
US6252267B1 (en) 1994-12-28 2001-06-26 International Business Machines Corporation Five square folded-bitline DRAM cell
US5795830A (en) 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US5700733A (en) 1995-06-27 1997-12-23 Micron Technology, Inc. Semiconductor processing methods of forming field oxide regions on a semiconductor substrate
KR100190757B1 (en) 1995-06-30 1999-06-01 김영환 Method of forming mosfet
US5604370A (en) 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
US5756395A (en) 1995-08-18 1998-05-26 Lsi Logic Corporation Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
US5677865A (en) 1995-09-11 1997-10-14 Micron Technology, Inc. Ferroelectric memory using reference charge circuit
US5680344A (en) 1995-09-11 1997-10-21 Micron Technology, Inc. Circuit and method of operating a ferrolectric memory in a DRAM mode
US5638318A (en) 1995-09-11 1997-06-10 Micron Technology, Inc. Ferroelectric memory using ferroelectric reference cells
US5771150A (en) 1996-01-03 1998-06-23 Micron Technology, Inc. Capacitor constructions
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JP3164026B2 (en) * 1996-08-21 2001-05-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5861328A (en) 1996-10-07 1999-01-19 Motorola, Inc. Method of fabricating GMR devices
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US6395613B1 (en) * 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US6150211A (en) 1996-12-11 2000-11-21 Micron Technology, Inc. Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry
JP2956626B2 (en) * 1996-12-12 1999-10-04 日本電気株式会社 Method for manufacturing MOS type semiconductor device
US5748519A (en) 1996-12-13 1998-05-05 Motorola, Inc. Method of selecting a memory cell in a magnetic random access memory device
US5804458A (en) 1996-12-16 1998-09-08 Motorola, Inc. Method of fabricating spaced apart submicron magnetic memory cells
US5913116A (en) 1997-01-08 1999-06-15 Advanced Micro Devices Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer
JP2982895B2 (en) 1997-02-06 1999-11-29 日本電気株式会社 CMOS semiconductor device and method of manufacturing the same
US5780349A (en) 1997-02-20 1998-07-14 National Semiconductor Corporation Self-aligned MOSFET gate/source/drain salicide formation
US5902690A (en) 1997-02-25 1999-05-11 Motorola, Inc. Stray magnetic shielding for a non-volatile MRAM
US5998257A (en) * 1997-03-13 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
US6004835A (en) 1997-04-25 1999-12-21 Micron Technology, Inc. Method of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to anode location and an electrical interconnection with a transistor source/drain region
EP0882806B1 (en) * 1997-05-21 2002-01-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Hard molybdenum alloy, wear resistant alloy and method for manufacturing the same
US5917749A (en) 1997-05-23 1999-06-29 Motorola, Inc. MRAM cell requiring low switching field
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6063688A (en) 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US5989966A (en) 1997-12-15 1999-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
US5956267A (en) 1997-12-18 1999-09-21 Honeywell Inc Self-aligned wordline keeper and method of manufacture therefor
US6291334B1 (en) 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6165833A (en) 1997-12-19 2000-12-26 Micron Technology, Inc. Semiconductor processing method of forming a capacitor
US6004862A (en) 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
US5963803A (en) 1998-02-02 1999-10-05 Advanced Micro Devices, Inc. Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
JP2975917B2 (en) * 1998-02-06 1999-11-10 株式会社半導体プロセス研究所 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
US6104633A (en) 1998-02-10 2000-08-15 International Business Machines Corporation Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices
US6147405A (en) 1998-02-19 2000-11-14 Micron Technology, Inc. Asymmetric, double-sided self-aligned silicide and method of forming the same
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6696746B1 (en) 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
US5933725A (en) 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6632718B1 (en) * 1998-07-15 2003-10-14 Texas Instruments Incorporated Disposable spacer technology for reduced cost CMOS processing
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6362506B1 (en) * 1998-08-26 2002-03-26 Texas Instruments Incorporated Minimization-feasible word line structure for DRAM cell
US6320222B1 (en) 1998-09-01 2001-11-20 Micron Technology, Inc. Structure and method for reducing threshold voltage variations due to dopant fluctuations
US6104068A (en) 1998-09-01 2000-08-15 Micron Technology, Inc. Structure and method for improved signal processing
JP4197775B2 (en) 1998-09-10 2008-12-17 浜松ホトニクス株式会社 Semiconductor position detector
WO2000017939A1 (en) * 1998-09-22 2000-03-30 Hitachi, Ltd. Semiconductor device and its manufacturing method
US6333866B1 (en) 1998-09-28 2001-12-25 Texas Instruments Incorporated Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US6071789A (en) 1998-11-10 2000-06-06 Vanguard International Semiconductor Corporation Method for simultaneously fabricating a DRAM capacitor and metal interconnections
US6005800A (en) 1998-11-23 1999-12-21 International Business Machines Corporation Magnetic memory array with paired asymmetric memory cells for improved write margin
US5977579A (en) 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
US6211044B1 (en) * 1999-04-12 2001-04-03 Advanced Micro Devices Process for fabricating a semiconductor device component using a selective silicidation reaction
US6136662A (en) 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
US6908800B1 (en) 1999-06-04 2005-06-21 Texas Instruments Incorporated Tunable sidewall spacer process for CMOS integrated circuits
JP4063450B2 (en) 1999-06-14 2008-03-19 エルピーダメモリ株式会社 Semiconductor integrated circuit device
US6436526B1 (en) 1999-06-17 2002-08-20 Matsushita Electric Industrial Co., Ltd. Magneto-resistance effect element, magneto-resistance effect memory cell, MRAM and method for performing information write to or read from the magneto-resistance effect memory cell
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
US6134139A (en) 1999-07-28 2000-10-17 Hewlett-Packard Magnetic memory structure with improved half-select margin
JP2001077196A (en) 1999-09-08 2001-03-23 Sony Corp Manufacture of semiconductor device
US6282113B1 (en) 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6362057B1 (en) * 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
SE518965C2 (en) 1999-11-04 2002-12-10 Ruben Haegglund Currency Management Device
US6582891B1 (en) * 1999-12-02 2003-06-24 Axcelis Technologies, Inc. Process for reducing edge roughness in patterned photoresist
KR100311050B1 (en) 1999-12-14 2001-11-05 윤종용 Method for manufacturing electrode of capacitor
US6271080B1 (en) 1999-12-16 2001-08-07 International Business Machines Corporation Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
JP4860022B2 (en) 2000-01-25 2012-01-25 エルピーダメモリ株式会社 Manufacturing method of semiconductor integrated circuit device
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6967140B2 (en) * 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6297554B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Dual damascene interconnect structure with reduced parasitic capacitance
US6251711B1 (en) 2000-03-17 2001-06-26 United Microelectronics Corp. Method for forming bridge free silicide
US6423474B1 (en) 2000-03-21 2002-07-23 Micron Technology, Inc. Use of DARC and BARC in flash memory processing
US20050164443A1 (en) 2000-05-18 2005-07-28 Youngmin Kim Tunable sidewall spacer process for CMOS integrated circuits
CA2349139C (en) 2000-05-31 2007-09-11 Kansai Paint Co., Ltd. Cationic resin composition
US6396096B1 (en) 2000-06-21 2002-05-28 International Business Machines Corporation Design layout for a dense memory cell structure
US6424561B1 (en) 2000-07-18 2002-07-23 Micron Technology, Inc. MRAM architecture using offset bits for increased write selectivity
US6632741B1 (en) 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6236590B1 (en) 2000-07-21 2001-05-22 Hewlett-Packard Company Optimal write conductors layout for improved performance in MRAM
US6455372B1 (en) 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics
US6348380B1 (en) * 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
DE10041749A1 (en) * 2000-08-27 2002-03-14 Infineon Technologies Ag Vertical non-volatile semiconductor memory cell and method for its production
US7118960B2 (en) * 2000-08-31 2006-10-10 Micron Technology, Inc. Selective polysilicon stud growth
SE517275C2 (en) * 2000-09-20 2002-05-21 Obducat Ab Wet etching of substrate involves arranging on the substrate a passivating substance comprising active substance reacting with component contained in etchant to form etch protecting compound
US6667237B1 (en) 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
JP2002124585A (en) 2000-10-17 2002-04-26 Hitachi Ltd Nonvolatile semiconductor memory device and production method therefor
US6534243B1 (en) * 2000-10-23 2003-03-18 Advanced Micro Devices, Inc. Chemical feature doubling process
US6926843B2 (en) 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US6368950B1 (en) * 2000-12-12 2002-04-09 Advanced Micro Devices, Inc. Silicide gate transistors
US6377070B1 (en) 2001-02-09 2002-04-23 Micron Technology, Inc. In-service programmable logic arrays with ultra thin vertical body transistors
US6448601B1 (en) 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
US6559491B2 (en) 2001-02-09 2003-05-06 Micron Technology, Inc. Folded bit line DRAM with ultra thin body transistors
US6496034B2 (en) 2001-02-09 2002-12-17 Micron Technology, Inc. Programmable logic arrays with ultra thin body transistors
US6566682B2 (en) 2001-02-09 2003-05-20 Micron Technology, Inc. Programmable memory address and decode circuits with ultra thin vertical body transistors
US6531727B2 (en) 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6424001B1 (en) 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6649476B2 (en) 2001-02-15 2003-11-18 Micron Technology, Inc. Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
JP2002261161A (en) * 2001-03-05 2002-09-13 Hitachi Ltd Manufacturing method of semiconductor device
US20040074949A1 (en) * 2001-03-07 2004-04-22 Masayuki Narita Friction agitation joining method flat material for plastic working and closed end sleeve like body
US6545904B2 (en) * 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
US6475867B1 (en) 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US6548347B2 (en) 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6498062B2 (en) 2001-04-27 2002-12-24 Micron Technology, Inc. DRAM access transistor
US6740594B2 (en) 2001-05-31 2004-05-25 Infineon Technologies Ag Method for removing carbon-containing polysilane from a semiconductor without stripping
KR20030002863A (en) * 2001-06-30 2003-01-09 주식회사 하이닉스반도체 Ferroelectric memory device over cored pulg and method for fabricating the same
US6522584B1 (en) * 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6744094B2 (en) 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
TW497138B (en) * 2001-08-28 2002-08-01 Winbond Electronics Corp Method for improving consistency of critical dimension
DE10142590A1 (en) 2001-08-31 2003-04-03 Infineon Technologies Ag Production of resist structures used in semiconductor industry comprises applying a resist film on a substrate, forming a resist structure with bars from the film, and removing reinforced sections
US7226853B2 (en) 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure
US6638441B2 (en) 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
US7078296B2 (en) 2002-01-16 2006-07-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFETs and methods for making the same
DE10207131B4 (en) 2002-02-20 2007-12-20 Infineon Technologies Ag Process for forming a hardmask in a layer on a flat disk
US6838722B2 (en) * 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
US6759180B2 (en) 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
US20030207584A1 (en) 2002-05-01 2003-11-06 Swaminathan Sivakumar Patterning tighter and looser pitch geometries
US6951709B2 (en) 2002-05-03 2005-10-04 Micron Technology, Inc. Method of fabricating a semiconductor multilevel interconnect structure
US6602779B1 (en) 2002-05-13 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6900521B2 (en) 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
TW543195B (en) 2002-06-12 2003-07-21 Powerchip Semiconductor Corp Split-gate flash memory structure and method of manufacture
US6734107B2 (en) 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6559017B1 (en) 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
KR100476924B1 (en) 2002-06-14 2005-03-17 삼성전자주식회사 Method Of Forming Fine Pattern Of Semiconductor Device
US6777725B2 (en) 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
US6924191B2 (en) 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
DE10228807B4 (en) * 2002-06-27 2009-07-23 Advanced Micro Devices, Inc., Sunnyvale Process for the production of microstructure elements
AU2003280498A1 (en) 2002-06-27 2004-01-19 Advanced Micro Devices, Inc. Method of defining the dimensions of circuit elements by using spacer deposition techniques
US6689695B1 (en) * 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US6835663B2 (en) * 2002-06-28 2004-12-28 Infineon Technologies Ag Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
US6960510B2 (en) * 2002-07-01 2005-11-01 International Business Machines Corporation Method of making sub-lithographic features
US7182823B2 (en) * 2002-07-05 2007-02-27 Olin Corporation Copper alloy containing cobalt, nickel and silicon
US20040018738A1 (en) * 2002-07-22 2004-01-29 Wei Liu Method for fabricating a notch gate structure of a field effect transistor
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6673684B1 (en) * 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
US6764949B2 (en) * 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6939808B2 (en) * 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
US20040046048A1 (en) * 2002-08-13 2004-03-11 Hsu Shih Hao Sprayer assembly for positioning hoses
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US6794699B2 (en) 2002-08-29 2004-09-21 Micron Technology Inc Annular gate and technique for fabricating an annular gate
US7205598B2 (en) * 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
US6756284B2 (en) * 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US7041047B2 (en) * 2002-10-04 2006-05-09 Boston Scientific Scimed, Inc. Method and apparatus for the delivery of brachytherapy
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7119020B2 (en) 2002-12-04 2006-10-10 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US6825529B2 (en) 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
JP2004193483A (en) 2002-12-13 2004-07-08 Renesas Technology Corp Semiconductor storage device
US6686245B1 (en) * 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US7084076B2 (en) 2003-02-27 2006-08-01 Samsung Electronics, Co., Ltd. Method for forming silicon dioxide film using siloxane
US6861701B2 (en) * 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
US7105089B2 (en) 2003-03-13 2006-09-12 3M Innovative Properties Company Liquid—liquid extraction system and method
KR100870176B1 (en) * 2003-06-27 2008-11-25 삼성전자주식회사 Nickel alloy salicide process, Methods of fabricating a semiconductor device using the same, nickel alloy silicide layer formed thereby and semiconductor devices fabricated using the same
US7015124B1 (en) * 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
JP4578785B2 (en) 2003-05-21 2010-11-10 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
DE10332725A1 (en) 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Method for self-adjusting reduction of structures
US7049702B2 (en) * 2003-08-14 2006-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Damascene structure at semiconductor substrate level
US7112483B2 (en) 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types
KR100499175B1 (en) 2003-09-01 2005-07-01 삼성전자주식회사 Semiconductor device and method of manufacturing the same
US7384868B2 (en) * 2003-09-15 2008-06-10 International Business Machines Corporation Reduction of silicide formation temperature on SiGe containing substrates
US6844591B1 (en) 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
DE10345455A1 (en) 2003-09-30 2005-05-04 Infineon Technologies Ag Method for producing a hard mask and hard mask arrangement
US20050156208A1 (en) * 2003-09-30 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Device having multiple silicide types and a method for its fabrication
KR100536801B1 (en) 2003-10-01 2005-12-14 동부아남반도체 주식회사 Semiconductor device and fabrication method thereof
US6867116B1 (en) * 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
US6946709B2 (en) 2003-12-02 2005-09-20 International Business Machines Corporation Complementary transistors having different source and drain extension spacing controlled by different spacer sizes
US7153734B2 (en) * 2003-12-29 2006-12-26 Intel Corporation CMOS device with metal and silicide gate electrodes and a method for making it
US20050144792A1 (en) 2004-01-06 2005-07-07 The Shire Corporation In-line sanding paddle with multiple extensions having certain tensile strengths
US6875703B1 (en) * 2004-01-20 2005-04-05 International Business Machines Corporation Method for forming quadruple density sidewall image transfer (SIT) structures
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
KR100574317B1 (en) * 2004-02-19 2006-04-26 삼성전자주식회사 Gate structure, semiconductor device having the same and methods of forming the gate structure and semiconductor device
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
US8486287B2 (en) 2004-03-19 2013-07-16 The Regents Of The University Of California Methods for fabrication of positional and compositionally controlled nanostructures on substrate
DE102004016073B4 (en) 2004-03-30 2010-12-23 Texas Instruments Deutschland Gmbh A method of generating a pulse output signal from a periodic sawtooth signal and a reference voltage, and a clocked current transformer
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
US7183205B2 (en) 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7473644B2 (en) * 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
US7396767B2 (en) * 2004-07-16 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure including silicide regions and method of making same
US7518182B2 (en) * 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7176125B2 (en) * 2004-07-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a static random access memory with a buried local interconnect
KR100704470B1 (en) * 2004-07-29 2007-04-10 주식회사 하이닉스반도체 Method for fabrication of semiconductor device using amorphous carbon layer to sacrificial hard mask
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7042047B2 (en) 2004-09-01 2006-05-09 Micron Technology, Inc. Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7442976B2 (en) * 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7655387B2 (en) * 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
JP4771271B2 (en) 2004-09-24 2011-09-14 トヨタ自動車株式会社 Single cell, method for manufacturing single cell, fuel cell, method for manufacturing fuel cell
US20060073613A1 (en) * 2004-09-29 2006-04-06 Sanjeev Aggarwal Ferroelectric memory cells and methods for fabricating ferroelectric memory cells and ferroelectric capacitors thereof
KR100614651B1 (en) 2004-10-11 2006-08-22 삼성전자주식회사 Apparatus And Method For Pattern Exposure, Photomask Used Therefor, Design Method For The Photomask, Illuminating System Therefor and Implementing Method For The Illuminating System
US7098536B2 (en) * 2004-10-21 2006-08-29 International Business Machines Corporation Structure for strained channel field effect transistor pair having a member and a contact via
US20060094180A1 (en) * 2004-11-02 2006-05-04 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
US7214629B1 (en) 2004-11-16 2007-05-08 Xilinx, Inc. Strain-silicon CMOS with dual-stressed film
US7208379B2 (en) 2004-11-29 2007-04-24 Texas Instruments Incorporated Pitch multiplication process
US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
KR100596795B1 (en) 2004-12-16 2006-07-05 주식회사 하이닉스반도체 Capacitor of semiconductor device and method for forming the same
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7238580B2 (en) 2005-01-26 2007-07-03 Freescale Semiconductor, Inc. Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US7163853B2 (en) * 2005-02-09 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a capacitor and a metal gate on a semiconductor device
US7227331B2 (en) 2005-02-14 2007-06-05 International Rectifier Corporation Safety interlock and protection circuit for permanent magnet motor drive
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US20060246217A1 (en) * 2005-03-18 2006-11-02 Weidman Timothy W Electroless deposition process on a silicide contact
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100640639B1 (en) 2005-04-19 2006-10-31 삼성전자주식회사 Semiconductor device having fine contact and method of manufacturing the same
JP2006313784A (en) * 2005-05-06 2006-11-16 Nec Electronics Corp Semiconductor device and its manufacturing method
US7214621B2 (en) 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7547599B2 (en) 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7413981B2 (en) * 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7759197B2 (en) * 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7393789B2 (en) * 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) * 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8716772B2 (en) 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
US7807536B2 (en) 2006-02-10 2010-10-05 Fairchild Semiconductor Corporation Low resistance gate for power MOSFET applications and method of manufacture
US20070210449A1 (en) 2006-03-07 2007-09-13 Dirk Caspary Memory device and an array of conductive lines and methods of making the same
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US8129289B2 (en) 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0967643A2 (en) * 1998-06-22 1999-12-29 International Business Machines Corporation Low-resistance salicide fill for trench capacitors
US20020000608A1 (en) * 2000-06-02 2002-01-03 Hirofumi Harada Vertical MOS transistor and a method of manufacturing the same
US20020102848A1 (en) * 2000-12-07 2002-08-01 Advanced Micro Devices, Inc. Damascene nisi metal gate high-k transistor
US6465309B1 (en) * 2000-12-12 2002-10-15 Advanced Micro Devices, Inc. Silicide gate transistors
US20020160557A1 (en) * 2001-04-28 2002-10-31 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
US20020187578A1 (en) * 2001-06-12 2002-12-12 Kwon Hong Method for manufacturing memory device
US20030170955A1 (en) * 2001-07-10 2003-09-11 Takahiro Kawamura Trench-gate semiconductor device and its manufacturing method
US20050153530A1 (en) * 2004-01-09 2005-07-14 International Business Machines Corporation Fet gate structure with metal gate electrode and silicide contact
US20070007571A1 (en) * 2005-07-06 2007-01-11 Richard Lindsay Semiconductor device with a buried gate and method of forming the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HONG-XIANG MO ET AL: "Formation and properties of ternary silicide (CoxNi1-x)Si2 thin films", SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY, 1998. PROCEEDINGS. 1998 5TH INTERNATIONAL CONFERENCE ON BEIJING, CHINA 21-23 OCT. 1998, PISCATAWAY, NJ, USA,IEEE, US, 21 October 1998 (1998-10-21), pages 271 - 274, XP010347126, ISBN: 0-7803-4306-9 *
LIU J ET AL: "DUAL-WORK-FUNCTION METAL GATES BY FULL SILICIDATION OF POLY-SI WITH CO-NI BI-LAYERS", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 26, no. 4, April 2005 (2005-04-01), pages 228 - 230, XP001230446, ISSN: 0741-3106 *

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