WO2007035284A3 - High performance flash memory device using a programming window for predetermination of bits to be programmed and dc-to-dc converter - Google Patents

High performance flash memory device using a programming window for predetermination of bits to be programmed and dc-to-dc converter Download PDF

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Publication number
WO2007035284A3
WO2007035284A3 PCT/US2006/035029 US2006035029W WO2007035284A3 WO 2007035284 A3 WO2007035284 A3 WO 2007035284A3 US 2006035029 W US2006035029 W US 2006035029W WO 2007035284 A3 WO2007035284 A3 WO 2007035284A3
Authority
WO
WIPO (PCT)
Prior art keywords
bits
programmed
array
predetermination
converter
Prior art date
Application number
PCT/US2006/035029
Other languages
French (fr)
Other versions
WO2007035284A2 (en
Inventor
Tiao-Hua Kuo
Nancy Leong
Nian Yang
Guowei Wang
Aaron Lee
Sachit Chandra
Michael A Vanbuskirk
Johnny Chen
Darlene Hamilton
Binh Quang Le
Original Assignee
Spansion Llc
Tiao-Hua Kuo
Nancy Leong
Nian Yang
Guowei Wang
Aaron Lee
Sachit Chandra
Michael A Vanbuskirk
Johnny Chen
Darlene Hamilton
Binh Quang Le
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc, Tiao-Hua Kuo, Nancy Leong, Nian Yang, Guowei Wang, Aaron Lee, Sachit Chandra, Michael A Vanbuskirk, Johnny Chen, Darlene Hamilton, Binh Quang Le filed Critical Spansion Llc
Priority to EP06803199.6A priority Critical patent/EP1927115B1/en
Priority to JP2008532263A priority patent/JP4763793B2/en
Priority to CN2006800333253A priority patent/CN101263563B/en
Publication of WO2007035284A2 publication Critical patent/WO2007035284A2/en
Publication of WO2007035284A3 publication Critical patent/WO2007035284A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A method is provided for programming a nonvolatile memory array including an array (102) of memory cells (201), where each memory cell (201) including a substrate (310), a control gate (328), a charge storage element (322), a source region (203) and a drain region (202). The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array (700) and determining which of the predetermined number of bits are to be programmed in the memory array (703). The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array (705). A programming state of the predetermined number of bits in the array is simultaneously verified (708).
PCT/US2006/035029 2005-09-20 2006-09-08 High performance flash memory device using a programming window for predetermination of bits to be programmed and dc-to-dc converter WO2007035284A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06803199.6A EP1927115B1 (en) 2005-09-20 2006-09-08 High performance flash memory device using a programming window for predetermination of bits to be programmed
JP2008532263A JP4763793B2 (en) 2005-09-20 2006-09-08 High performance flash memory device using a programming window and a DC-DC converter for predetermining bits to be programmed
CN2006800333253A CN101263563B (en) 2005-09-20 2006-09-08 High performance flash memory device capable of high density data storage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/229,527 2005-09-20
US11/229,527 US7443732B2 (en) 2005-09-20 2005-09-20 High performance flash memory device capable of high density data storage

Publications (2)

Publication Number Publication Date
WO2007035284A2 WO2007035284A2 (en) 2007-03-29
WO2007035284A3 true WO2007035284A3 (en) 2007-05-31

Family

ID=37526663

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/035029 WO2007035284A2 (en) 2005-09-20 2006-09-08 High performance flash memory device using a programming window for predetermination of bits to be programmed and dc-to-dc converter

Country Status (7)

Country Link
US (1) US7443732B2 (en)
EP (1) EP1927115B1 (en)
JP (2) JP4763793B2 (en)
KR (1) KR100953991B1 (en)
CN (1) CN101263563B (en)
TW (1) TWI337358B (en)
WO (1) WO2007035284A2 (en)

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JP4661707B2 (en) * 2005-10-03 2011-03-30 セイコーエプソン株式会社 Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device
JP4804479B2 (en) * 2005-12-13 2011-11-02 スパンション エルエルシー Semiconductor device and control method thereof
KR101303177B1 (en) * 2007-06-22 2013-09-17 삼성전자주식회사 Non-volatile memory device and operating method of the same
US7869273B2 (en) * 2007-09-04 2011-01-11 Sandisk Corporation Reducing the impact of interference during programming
US7633798B2 (en) * 2007-11-21 2009-12-15 Micron Technology, Inc. M+N bit programming and M+L bit read for M bit memory cells
KR100967001B1 (en) * 2008-05-29 2010-06-30 주식회사 하이닉스반도체 Method of programming a non volatile memory device
US7852671B2 (en) * 2008-10-30 2010-12-14 Micron Technology, Inc. Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
JP2010129154A (en) * 2008-11-28 2010-06-10 Samsung Electronics Co Ltd Nonvolatile semiconductor memory device
KR101679358B1 (en) * 2009-08-14 2016-11-24 삼성전자 주식회사 Flash memory device, program method and read method for the same
US8804429B2 (en) * 2011-12-08 2014-08-12 Silicon Storage Technology, Inc. Non-volatile memory device and a method of programming such device
TWI552162B (en) * 2014-07-31 2016-10-01 Zhi-Cheng Xiao Low power memory

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US5495442A (en) * 1993-07-08 1996-02-27 Sandisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
EP0762429A2 (en) * 1995-08-11 1997-03-12 Interuniversitair Microelektronica Centrum Vzw Method of programming a flash EEPROM memory cell optimized for low power consumption and a method for erasing said cell
US5646890A (en) * 1996-03-29 1997-07-08 Aplus Integrated Circuits, Inc. Flexible byte-erase flash memory and decoder
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US6744675B1 (en) * 2002-11-26 2004-06-01 Advanced Micro Devices, Inc. Program algorithm including soft erase for SONOS memory device

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JPH06267283A (en) * 1993-03-16 1994-09-22 Mitsubishi Electric Corp Read-only memory writable data and method for writing/ reading data
JPH0721791A (en) * 1993-03-16 1995-01-24 Toshiba Corp Semiconductor memory and memory card and power supply driving system for eeprom
US5537350A (en) * 1993-09-10 1996-07-16 Intel Corporation Method and apparatus for sequential programming of the bits in a word of a flash EEPROM memory array
US5530803A (en) * 1994-04-14 1996-06-25 Advanced Micro Devices, Inc. Method and apparatus for programming memory devices
US5497119A (en) * 1994-06-01 1996-03-05 Intel Corporation High precision voltage regulation circuit for programming multilevel flash memory
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Publication number Priority date Publication date Assignee Title
US5270979A (en) * 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US5495442A (en) * 1993-07-08 1996-02-27 Sandisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
EP0762429A2 (en) * 1995-08-11 1997-03-12 Interuniversitair Microelektronica Centrum Vzw Method of programming a flash EEPROM memory cell optimized for low power consumption and a method for erasing said cell
US5646890A (en) * 1996-03-29 1997-07-08 Aplus Integrated Circuits, Inc. Flexible byte-erase flash memory and decoder
US20020109539A1 (en) * 1999-07-22 2002-08-15 Kabushiki Kaisha Toshiba Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient
US6744675B1 (en) * 2002-11-26 2004-06-01 Advanced Micro Devices, Inc. Program algorithm including soft erase for SONOS memory device

Also Published As

Publication number Publication date
KR20080047408A (en) 2008-05-28
WO2007035284A2 (en) 2007-03-29
JP2011023111A (en) 2011-02-03
JP4763793B2 (en) 2011-08-31
KR100953991B1 (en) 2010-04-21
CN101263563A (en) 2008-09-10
EP1927115A2 (en) 2008-06-04
EP1927115B1 (en) 2015-11-18
TW200719347A (en) 2007-05-16
US7443732B2 (en) 2008-10-28
TWI337358B (en) 2011-02-11
US20070064464A1 (en) 2007-03-22
JP2009509287A (en) 2009-03-05
CN101263563B (en) 2012-05-02

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