WO2007035416A3 - Integrated circuit with gate self-protection - Google Patents

Integrated circuit with gate self-protection Download PDF

Info

Publication number
WO2007035416A3
WO2007035416A3 PCT/US2006/035849 US2006035849W WO2007035416A3 WO 2007035416 A3 WO2007035416 A3 WO 2007035416A3 US 2006035849 W US2006035849 W US 2006035849W WO 2007035416 A3 WO2007035416 A3 WO 2007035416A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
body contacting
protection
contacting structure
gate
Prior art date
Application number
PCT/US2006/035849
Other languages
French (fr)
Other versions
WO2007035416A2 (en
Inventor
Badih El-Kareh
Scott Balster
Hiroshi Yasuda
Manfred Schiekofer
Original Assignee
Texas Instruments Inc
Badih El-Kareh
Scott Balster
Hiroshi Yasuda
Manfred Schiekofer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102005044124A external-priority patent/DE102005044124B4/en
Application filed by Texas Instruments Inc, Badih El-Kareh, Scott Balster, Hiroshi Yasuda, Manfred Schiekofer filed Critical Texas Instruments Inc
Publication of WO2007035416A2 publication Critical patent/WO2007035416A2/en
Publication of WO2007035416A3 publication Critical patent/WO2007035416A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer (14) with electrically active regions (16) in which and on which the MOS device and the bipolar device are formed and electrically inactive regions (18) for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The invention further relates to a method for fabricating such an integrated circuit.
PCT/US2006/035849 2005-09-15 2006-09-15 Integrated circuit with gate self-protection WO2007035416A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102005044124A DE102005044124B4 (en) 2005-09-15 2005-09-15 A method of fabricating an integrated circuit with gate self-protection, and integrated circuit with gate self-protection
DE102005044124.6 2005-09-15
US11/470,760 US7772057B2 (en) 2005-09-15 2006-09-07 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
US11/470,760 2006-09-07

Publications (2)

Publication Number Publication Date
WO2007035416A2 WO2007035416A2 (en) 2007-03-29
WO2007035416A3 true WO2007035416A3 (en) 2007-11-22

Family

ID=37889332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/035849 WO2007035416A2 (en) 2005-09-15 2006-09-15 Integrated circuit with gate self-protection

Country Status (1)

Country Link
WO (1) WO2007035416A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5643810A (en) * 1995-10-06 1997-07-01 Samsung Electronics Co., Ltd. Methods of forming BiCMOS semiconductor devices
US5760445A (en) * 1994-09-13 1998-06-02 Hewlett-Packard Company Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies
US6277708B1 (en) * 1998-03-31 2001-08-21 Philips Electronics North America Corp. Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760445A (en) * 1994-09-13 1998-06-02 Hewlett-Packard Company Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies
US5643810A (en) * 1995-10-06 1997-07-01 Samsung Electronics Co., Ltd. Methods of forming BiCMOS semiconductor devices
US6277708B1 (en) * 1998-03-31 2001-08-21 Philips Electronics North America Corp. Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same

Also Published As

Publication number Publication date
WO2007035416A2 (en) 2007-03-29

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