WO2007053606A3 - Multiple die integrated circuit package - Google Patents

Multiple die integrated circuit package Download PDF

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Publication number
WO2007053606A3
WO2007053606A3 PCT/US2006/042450 US2006042450W WO2007053606A3 WO 2007053606 A3 WO2007053606 A3 WO 2007053606A3 US 2006042450 W US2006042450 W US 2006042450W WO 2007053606 A3 WO2007053606 A3 WO 2007053606A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
insulator
vias
multiple die
circuit package
Prior art date
Application number
PCT/US2006/042450
Other languages
French (fr)
Other versions
WO2007053606A2 (en
Inventor
Robert F Wallace
Original Assignee
Sandisk Corp
Robert F Wallace
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/264,112 external-priority patent/US7511371B2/en
Priority claimed from US11/264,556 external-priority patent/US7352058B2/en
Application filed by Sandisk Corp, Robert F Wallace filed Critical Sandisk Corp
Priority to CN2006800450011A priority Critical patent/CN101341593B/en
Priority to EP06827158A priority patent/EP1949440A2/en
Publication of WO2007053606A2 publication Critical patent/WO2007053606A2/en
Publication of WO2007053606A3 publication Critical patent/WO2007053606A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2924/14Integrated circuits
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Abstract

A multiple die package for integrated circuits is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A removable storage card package is also described.
PCT/US2006/042450 2005-11-01 2006-10-30 Multiple die integrated circuit package WO2007053606A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800450011A CN101341593B (en) 2005-11-01 2006-10-30 Multiple die integrated circuit package
EP06827158A EP1949440A2 (en) 2005-11-01 2006-10-30 Multiple die integrated circuit package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/264,112 US7511371B2 (en) 2005-11-01 2005-11-01 Multiple die integrated circuit package
US11/264,556 US7352058B2 (en) 2005-11-01 2005-11-01 Methods for a multiple die integrated circuit package
US11/264,112 2005-11-01
US11/264,556 2005-11-01

Publications (2)

Publication Number Publication Date
WO2007053606A2 WO2007053606A2 (en) 2007-05-10
WO2007053606A3 true WO2007053606A3 (en) 2007-09-07

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ID=37680599

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Application Number Title Priority Date Filing Date
PCT/US2006/042450 WO2007053606A2 (en) 2005-11-01 2006-10-30 Multiple die integrated circuit package

Country Status (4)

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EP (1) EP1949440A2 (en)
KR (1) KR100996982B1 (en)
TW (2) TWI324385B (en)
WO (1) WO2007053606A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI405279B (en) * 2010-07-23 2013-08-11 Global Unichip Corp Packaging of semiconductor components

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US4288841A (en) * 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
JPS5763850A (en) * 1980-10-06 1982-04-17 Nec Corp Semiconductor device
US4423468A (en) * 1980-10-01 1983-12-27 Motorola, Inc. Dual electronic component assembly
JPH0330494A (en) * 1989-06-28 1991-02-08 Sharp Corp Through-hole forming method for flexible circuit board
WO1993026144A1 (en) * 1992-06-15 1993-12-23 Dyconex Patente Ag Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points
DE19522338A1 (en) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Deformable substrate through-contact production method for chip carrier
EP0798772A1 (en) * 1996-03-26 1997-10-01 Commissariat A L'energie Atomique Process for realizing a deposition on a detachable support, and realized deposition on a support
DE19648492A1 (en) * 1996-11-22 1997-11-13 Siemens Ag Three=dimensional multi-chip module, e.g. memory module
US6316825B1 (en) * 1998-05-15 2001-11-13 Hyundai Electronics Industries Co., Ltd. Chip stack package utilizing a connecting hole to improve electrical connection between leadframes
US20020084522A1 (en) * 2000-10-10 2002-07-04 Akira Yoshizawa Semiconductor device using interposer substrate and manufacturing method therefor
US20020121690A1 (en) * 1987-06-24 2002-09-05 Hitachi, Ltd. (Jp) Semiconductor memory module having double-sided stacked memory chip layout

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US5715193A (en) * 1996-05-23 1998-02-03 Micron Quantum Devices, Inc. Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
JP3296306B2 (en) * 1997-10-28 2002-06-24 ソニーケミカル株式会社 Anisotropic conductive adhesive and adhesive film
JP3674333B2 (en) * 1998-09-11 2005-07-20 株式会社日立製作所 Power semiconductor module and electric motor drive system using the same
JP2000332055A (en) * 1999-05-17 2000-11-30 Sony Corp Flip-chip mounting structure and mounting method
JP2004199887A (en) * 2002-12-16 2004-07-15 Agilent Technol Inc Electrical contact switching device using conductive fluid and its manufacturing method

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288841A (en) * 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
US4423468A (en) * 1980-10-01 1983-12-27 Motorola, Inc. Dual electronic component assembly
JPS5763850A (en) * 1980-10-06 1982-04-17 Nec Corp Semiconductor device
US20020121690A1 (en) * 1987-06-24 2002-09-05 Hitachi, Ltd. (Jp) Semiconductor memory module having double-sided stacked memory chip layout
JPH0330494A (en) * 1989-06-28 1991-02-08 Sharp Corp Through-hole forming method for flexible circuit board
WO1993026144A1 (en) * 1992-06-15 1993-12-23 Dyconex Patente Ag Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points
DE19522338A1 (en) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Deformable substrate through-contact production method for chip carrier
EP0798772A1 (en) * 1996-03-26 1997-10-01 Commissariat A L'energie Atomique Process for realizing a deposition on a detachable support, and realized deposition on a support
DE19648492A1 (en) * 1996-11-22 1997-11-13 Siemens Ag Three=dimensional multi-chip module, e.g. memory module
US6316825B1 (en) * 1998-05-15 2001-11-13 Hyundai Electronics Industries Co., Ltd. Chip stack package utilizing a connecting hole to improve electrical connection between leadframes
US20020084522A1 (en) * 2000-10-10 2002-07-04 Akira Yoshizawa Semiconductor device using interposer substrate and manufacturing method therefor

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WO2007053606A2 (en) 2007-05-10
KR20080087790A (en) 2008-10-01
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