WO2007053606A3 - Multiple die integrated circuit package - Google Patents
Multiple die integrated circuit package Download PDFInfo
- Publication number
- WO2007053606A3 WO2007053606A3 PCT/US2006/042450 US2006042450W WO2007053606A3 WO 2007053606 A3 WO2007053606 A3 WO 2007053606A3 US 2006042450 W US2006042450 W US 2006042450W WO 2007053606 A3 WO2007053606 A3 WO 2007053606A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuit
- insulator
- vias
- multiple die
- circuit package
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2006800450011A CN101341593B (en) | 2005-11-01 | 2006-10-30 | Multiple die integrated circuit package |
EP06827158A EP1949440A2 (en) | 2005-11-01 | 2006-10-30 | Multiple die integrated circuit package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/264,112 US7511371B2 (en) | 2005-11-01 | 2005-11-01 | Multiple die integrated circuit package |
US11/264,556 US7352058B2 (en) | 2005-11-01 | 2005-11-01 | Methods for a multiple die integrated circuit package |
US11/264,112 | 2005-11-01 | ||
US11/264,556 | 2005-11-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007053606A2 WO2007053606A2 (en) | 2007-05-10 |
WO2007053606A3 true WO2007053606A3 (en) | 2007-09-07 |
Family
ID=37680599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/042450 WO2007053606A2 (en) | 2005-11-01 | 2006-10-30 | Multiple die integrated circuit package |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1949440A2 (en) |
KR (1) | KR100996982B1 (en) |
TW (2) | TWI324385B (en) |
WO (1) | WO2007053606A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI405279B (en) * | 2010-07-23 | 2013-08-11 | Global Unichip Corp | Packaging of semiconductor components |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288841A (en) * | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
JPS5763850A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
US4423468A (en) * | 1980-10-01 | 1983-12-27 | Motorola, Inc. | Dual electronic component assembly |
JPH0330494A (en) * | 1989-06-28 | 1991-02-08 | Sharp Corp | Through-hole forming method for flexible circuit board |
WO1993026144A1 (en) * | 1992-06-15 | 1993-12-23 | Dyconex Patente Ag | Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points |
DE19522338A1 (en) * | 1995-06-20 | 1997-01-02 | Fraunhofer Ges Forschung | Deformable substrate through-contact production method for chip carrier |
EP0798772A1 (en) * | 1996-03-26 | 1997-10-01 | Commissariat A L'energie Atomique | Process for realizing a deposition on a detachable support, and realized deposition on a support |
DE19648492A1 (en) * | 1996-11-22 | 1997-11-13 | Siemens Ag | Three=dimensional multi-chip module, e.g. memory module |
US6316825B1 (en) * | 1998-05-15 | 2001-11-13 | Hyundai Electronics Industries Co., Ltd. | Chip stack package utilizing a connecting hole to improve electrical connection between leadframes |
US20020084522A1 (en) * | 2000-10-10 | 2002-07-04 | Akira Yoshizawa | Semiconductor device using interposer substrate and manufacturing method therefor |
US20020121690A1 (en) * | 1987-06-24 | 2002-09-05 | Hitachi, Ltd. (Jp) | Semiconductor memory module having double-sided stacked memory chip layout |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0179921B1 (en) * | 1996-05-17 | 1999-03-20 | 문정환 | Stacked semiconductor package |
US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
JP3296306B2 (en) * | 1997-10-28 | 2002-06-24 | ソニーケミカル株式会社 | Anisotropic conductive adhesive and adhesive film |
JP3674333B2 (en) * | 1998-09-11 | 2005-07-20 | 株式会社日立製作所 | Power semiconductor module and electric motor drive system using the same |
JP2000332055A (en) * | 1999-05-17 | 2000-11-30 | Sony Corp | Flip-chip mounting structure and mounting method |
JP2004199887A (en) * | 2002-12-16 | 2004-07-15 | Agilent Technol Inc | Electrical contact switching device using conductive fluid and its manufacturing method |
-
2006
- 2006-10-30 WO PCT/US2006/042450 patent/WO2007053606A2/en active Application Filing
- 2006-10-30 EP EP06827158A patent/EP1949440A2/en not_active Withdrawn
- 2006-10-30 KR KR1020087013254A patent/KR100996982B1/en active IP Right Grant
- 2006-10-31 TW TW095140244A patent/TWI324385B/en not_active IP Right Cessation
- 2006-10-31 TW TW098135181A patent/TWI475662B/en not_active IP Right Cessation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288841A (en) * | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
US4423468A (en) * | 1980-10-01 | 1983-12-27 | Motorola, Inc. | Dual electronic component assembly |
JPS5763850A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
US20020121690A1 (en) * | 1987-06-24 | 2002-09-05 | Hitachi, Ltd. (Jp) | Semiconductor memory module having double-sided stacked memory chip layout |
JPH0330494A (en) * | 1989-06-28 | 1991-02-08 | Sharp Corp | Through-hole forming method for flexible circuit board |
WO1993026144A1 (en) * | 1992-06-15 | 1993-12-23 | Dyconex Patente Ag | Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points |
DE19522338A1 (en) * | 1995-06-20 | 1997-01-02 | Fraunhofer Ges Forschung | Deformable substrate through-contact production method for chip carrier |
EP0798772A1 (en) * | 1996-03-26 | 1997-10-01 | Commissariat A L'energie Atomique | Process for realizing a deposition on a detachable support, and realized deposition on a support |
DE19648492A1 (en) * | 1996-11-22 | 1997-11-13 | Siemens Ag | Three=dimensional multi-chip module, e.g. memory module |
US6316825B1 (en) * | 1998-05-15 | 2001-11-13 | Hyundai Electronics Industries Co., Ltd. | Chip stack package utilizing a connecting hole to improve electrical connection between leadframes |
US20020084522A1 (en) * | 2000-10-10 | 2002-07-04 | Akira Yoshizawa | Semiconductor device using interposer substrate and manufacturing method therefor |
Also Published As
Publication number | Publication date |
---|---|
WO2007053606A2 (en) | 2007-05-10 |
KR20080087790A (en) | 2008-10-01 |
TW201003888A (en) | 2010-01-16 |
EP1949440A2 (en) | 2008-07-30 |
TWI324385B (en) | 2010-05-01 |
TWI475662B (en) | 2015-03-01 |
KR100996982B1 (en) | 2010-11-26 |
TW200746381A (en) | 2007-12-16 |
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