WO2007054844A2 - Vertical insulated gate field-effect transistor and method of manufacturing the same - Google Patents

Vertical insulated gate field-effect transistor and method of manufacturing the same Download PDF

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Publication number
WO2007054844A2
WO2007054844A2 PCT/IB2006/053890 IB2006053890W WO2007054844A2 WO 2007054844 A2 WO2007054844 A2 WO 2007054844A2 IB 2006053890 W IB2006053890 W IB 2006053890W WO 2007054844 A2 WO2007054844 A2 WO 2007054844A2
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WO
WIPO (PCT)
Prior art keywords
fin
contact
effect transistor
gate
field effect
Prior art date
Application number
PCT/IB2006/053890
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French (fr)
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WO2007054844A3 (en
Inventor
Gilberto A. Curatola
Radu Surdeanu
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Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2007054844A2 publication Critical patent/WO2007054844A2/en
Publication of WO2007054844A3 publication Critical patent/WO2007054844A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the invention relates to a FINFET (field effect transistor) and a method of manufacture.
  • the doping needed for such devices combined with the short channel length results in device characteristics which can be seriously degraded, known as the "short channel effect".
  • FIG. 1 illustrates a FINFET.
  • Substrate 10 has a plurality of fins 12 extending vertically from the substrate and laterally across the substrate. The fins extend longitudinally in the direction into the page of Figure 1. The fins are separated by buried oxide (BOX) layer 14.
  • a gate dielectric 16 extends over the top of each fin 12 between the BOX layers 14, and a gate 18 extends over the gate dielectric.
  • Source and drain contacts are provided on either end of the gate 18 and the gate controls conduction between source and drain.
  • a common gate voltage may be applied to all gate electrodes in parallel.
  • inversion layers are formed on either side of the fin, controlled by the two gates one on either side.
  • the use of two gates instead of one reduces the short channel effect. Further the provision of two inversion layers, one on either side of the fin, can increase current carrying capacity.
  • US2005/0035399. Another similar structure and manufacturing method is described in US2005/0035399. Again, the structure is difficult to fabricate to precise dimensions. US2005/0035399 deals with this by providing a central semiconducting region in each body region to reduce the channel thickness in spite of the thick fin. It would however be more beneficial to provide a method and device with narrower bodies to increase the integration density.
  • a gold nanoparticle on a substrate is used as a mask to form a nanopillar.
  • a gate stack is deposited, the nanopillar removed to form a hole and a gate conductor, gate dielectric and semiconductor channel formed within the hole, with the channel in the centre.
  • a vertical transistor is thus formed, with the base of the channel connected through a highly doped region of the substrate and the top of the channel formed to have a source or drain contact.
  • the method allows a fin FET to be fabricated at reduced cost compared to alternative methods. Further, the resulting structure has the advantage that the separate contacts on either side of the fin allow the FET to be operated in either a symmetric or an asymmetric configuration.
  • the step of fabricating at least one semiconductor fin may conveniently be carried out by etching the first major surface to form the at least one semiconductor fin.
  • the method may further form an oxide layer at the base of the fin on either side of the fin. This keeps the gate spaced from the substrate on either side of the fin so that when a voltage is applied to the gate the voltage creates an inversion layer in the fin but not the substrate on either side of the fin.
  • the method may further include implanting a dopant to form a source/drain implant at the top of the fin. This may be carried out before forming the gate dielectric which can reduce damage caused by the implantation step in the subsequently formed structure.
  • the step of etching back the top of the fin includes carrying out a chemical mechanical polishing step.
  • the method may further include etching the gate dielectric and the gate material from the top of the sides of the fin, after the step of etching back the top of the fin. This separates the gate from the contact at the top of the fin in the finished structure.
  • the method may further include depositing oxide on either side of the fin to the top of the fin after etching back the top of the fin. This protects the device while the next step is carried out.
  • the step of forming a contact at the top of the fin may be carried out by growing a silicon epilayer on the exposed semiconductor at the top of the fin, and suiciding the silicon epilayer to form the contact of suicide.
  • the invention also relates to a fin FET as set out in claim 9.
  • an array of fin FETs is provided.
  • the fin FETs may have a common contact to the base of the fins and separate contacts to the top of each fin.
  • Figure 1 shows a prior art FINFET
  • Figures 2 to 7 show stages in the manufacture of a FINFET according to a first embodiment of the invention; and Figure 8 illustrates a second embodiment of the invention.
  • a semiconductor substrate 10 is provided having a first major surface 20.
  • a fin 12 is patterned by etching the first major surface 20. The fin 12 extends into the substrate 10 from the first major surface and extends longitudinally.
  • a deep implantation step is carried out to deposit a source or drain implant 24 at the base of the fins, as illustrated schematically by the arrows 28 indicating the implantation in Figure 2 and resulting drain contact 30.
  • a gate dielectric layer 16 is then deposited over the whole of the first major surface.
  • the gate dielectric layer 16 may be of silicon oxide, silicon nitride, silicon oxynitride, a medium k material or a high k material.
  • a metal gate 18 is then deposited over the whole surface and patterned as illustrated in Figure 3.
  • a chemical-mechanical polishing step is carried out to remove the top of the fin 12, and a timed selective etch-back carried out to remove the gate dielectric 16 and gate metal 18 from the upper region 30 of the fin 12, leaving the fin exposed in the upper region 30, as illustrated in Figure 4, and the gate metal divided into a first gate 42 and a second gate 44 on opposed sides of the fin 12.
  • Oxide 32 is then grown up to the top of each fin leaving the top 34 of each fin 12 exposed. If required, oxide can be grown over the whole surface and then selectively etched back to expose the top 34 of the fin.
  • a silicon epilayer 35 is selectively grown on the exposed top 34 of each fin, resulting in the structure shown in Figure 5.
  • the silicon epilayer 35 is then suicided to form a suicide source layer 36.
  • a source contacts 38 to the suicide layer are formed.
  • First and second gate contacts 46, 48 are provided to contact the respective first and second gates 42,44 on respective opposed sides of the fin. Note that care is taken to avoid a short between the gate contacts 46,48 and the suicide source layer 36 or source contact 38.
  • a substrate contact 40 in contact with drain region 24 is then formed, adjacent to the fin, as illustrated in Figure 6 which is a side section of Figure 5 showing the length of the fin 12 in the horizontal direction.
  • the structure delivers a vertical FINFET with all the advantages of reduced short channel effects.
  • the semiconductor in the fin can be undoped because of quantum confinement effects in the fin, which leads to improved mobility.
  • the fabrication process is cheap compared to silicon-on- insulator devices.
  • the buried oxide layer can be fabricated using normal oxidation processes.
  • the source and drain resistance can be a very significant factor leading to poor device performance.
  • the source and drain contacts are no longer affected by the length of the source and drain regions of the fin which can greatly improve (reduce) the series resistance.
  • the separate gate contacts 46, 48 on either side of the fin can be separately controlled to allow the FINFET to be operated symmetrically or asymmetrically.
  • a plurality of FINFETs are connected to one another as illustrated in Figure 8.
  • Figure 8 also shows a further alternative.
  • the deep implantation 24 extends through the full thickness of substrate 10 and the drain contact 40 is provided on the rear of the substrate instead of the source.
  • the bulk drain contact 40 can be used as a common contact for each of a plurality of FINFETs on a wafer, with the individual source/drain contacts 38 being connected individually or in parallel depending on the application.

Abstract

A fin FET includes at least one semiconductor fin (12) extending in a vertical direction, gate dielectric (16) on the sides of the fin (12) and a pair of opposed gates (42,44) on either side of the fin. Source and drain contacts (38,40) are provided to the top and bottom of the fin (12). An array of fin FETs may include a common contact at the base of the fin and separate contacts to the top of the fin. A method of manufacturing the fin FET is described.

Description

DESCRIPTION
FINFET AND METHOD OF MANUFACTURE
The invention relates to a FINFET (field effect transistor) and a method of manufacture.
As the channel length of semiconductor devices becomes increasingly short the doping needed for such devices combined with the short channel length results in device characteristics which can be seriously degraded, known as the "short channel effect".
One approach to this problem is a FINFET (fin field effect transistor) which is a field effect transistor with a plurality of fins. Figure 1 illustrates a FINFET. Substrate 10 has a plurality of fins 12 extending vertically from the substrate and laterally across the substrate. The fins extend longitudinally in the direction into the page of Figure 1. The fins are separated by buried oxide (BOX) layer 14. A gate dielectric 16 extends over the top of each fin 12 between the BOX layers 14, and a gate 18 extends over the gate dielectric.
Longitudinally spaced source and drain contacts (not shown) are provided on either end of the gate 18 and the gate controls conduction between source and drain.
A common gate voltage may be applied to all gate electrodes in parallel. With an appropriate gate voltage, inversion layers are formed on either side of the fin, controlled by the two gates one on either side. The use of two gates instead of one reduces the short channel effect. Further the provision of two inversion layers, one on either side of the fin, can increase current carrying capacity.
An alternative FET and method of manufacturing it is presented in US2005/0164454. In the process described, the semiconductor body region forming the transistor is grown using selective epitaxy. This process has a number of disadvantages. Firstly, it is expensive. Secondly, epitaxial growth does not in practice grow vertical pillars, but the pillars will also extend laterally, meaning that it is difficult to control the fin width, which in turn must be specified to be reasonably wide. It is indeed far from clear how the clean vertical pillars shown in the drawings of US2005/0164454 can be produced. If an extra etching step were used to pattern the fins, this would result in misalignment problems and again prevent very narrow fins from being formed.
As a result, the width of the body of the transistor of US2005/0164454 will be poorly controlled leading to a number of further problems, such as dislocations at the oxide. Poor device performance can accordingly be expected.
Another similar structure and manufacturing method is described in US2005/0035399. Again, the structure is difficult to fabricate to precise dimensions. US2005/0035399 deals with this by providing a central semiconducting region in each body region to reduce the channel thickness in spite of the thick fin. It would however be more beneficial to provide a method and device with narrower bodies to increase the integration density.
Another complex manufacturing process is described in US2004/0097040. In this process, a gold nanoparticle on a substrate is used as a mask to form a nanopillar. A gate stack is deposited, the nanopillar removed to form a hole and a gate conductor, gate dielectric and semiconductor channel formed within the hole, with the channel in the centre. A vertical transistor is thus formed, with the base of the channel connected through a highly doped region of the substrate and the top of the channel formed to have a source or drain contact.
Again, the process has a number of disadvantages. Gold nanoparticles can cause serious contamination problems. A large number of steps are required. It is very difficult to grow a single crystal semiconductor channel since the quality of the semiconductor at the bottom of the channel is low, and stacking faults and defects can appear at the oxide interface further degrading transistor performance. Thus, there remains a need for a process for manufacturing a FET that addresses these issues in which the process can be carried out at reasonable cost and without undue difficulty.
According to the invention there is provided a FINFET according to claim 1.
The method allows a fin FET to be fabricated at reduced cost compared to alternative methods. Further, the resulting structure has the advantage that the separate contacts on either side of the fin allow the FET to be operated in either a symmetric or an asymmetric configuration.
The step of fabricating at least one semiconductor fin may conveniently be carried out by etching the first major surface to form the at least one semiconductor fin.
The method may further form an oxide layer at the base of the fin on either side of the fin. This keeps the gate spaced from the substrate on either side of the fin so that when a voltage is applied to the gate the voltage creates an inversion layer in the fin but not the substrate on either side of the fin.
The method may further include implanting a dopant to form a source/drain implant at the top of the fin. This may be carried out before forming the gate dielectric which can reduce damage caused by the implantation step in the subsequently formed structure.
Conveniently, the step of etching back the top of the fin includes carrying out a chemical mechanical polishing step.
The method may further include etching the gate dielectric and the gate material from the top of the sides of the fin, after the step of etching back the top of the fin. This separates the gate from the contact at the top of the fin in the finished structure.
The method may further include depositing oxide on either side of the fin to the top of the fin after etching back the top of the fin. This protects the device while the next step is carried out. The step of forming a contact at the top of the fin may be carried out by growing a silicon epilayer on the exposed semiconductor at the top of the fin, and suiciding the silicon epilayer to form the contact of suicide.
In another aspect, the invention also relates to a fin FET as set out in claim 9.
In preferred embodiments, an array of fin FETs is provided. The fin FETs may have a common contact to the base of the fins and separate contacts to the top of each fin.
For a better understanding of the invention, embodiments will now be described, with reference to the accompanying drawings, in which: Figure 1 shows a prior art FINFET;
Figures 2 to 7 show stages in the manufacture of a FINFET according to a first embodiment of the invention; and Figure 8 illustrates a second embodiment of the invention.
Like components are given the same reference numerals in the different Figures. The Figures are schematic and not to scale.
A semiconductor substrate 10 is provided having a first major surface 20. A fin 12 is patterned by etching the first major surface 20. The fin 12 extends into the substrate 10 from the first major surface and extends longitudinally.
The skilled person will be aware of many techniques for patterning surfaces, for example by depositing photoresist, patterning the photoresist using a mask, developing the photoresist to create a photoresist pattern, using reactive ion etching to etch the regions not covered by the photoresist pattern, and removing the remainder of the photoresist. Alternatives include using a hard mask, or using a wet etch. Since the skilled person is already aware of many suitable patterning techniques, for example for patterning the fin, they will not be described in detail here. Next, oxide is deposited over the whole surface 20 and etched back to leave a pseudo buried oxide layer 22 adjacent to the base of the fin 12, as illustrated in Figure 2.
A deep implantation step is carried out to deposit a source or drain implant 24 at the base of the fins, as illustrated schematically by the arrows 28 indicating the implantation in Figure 2 and resulting drain contact 30.
A gate dielectric layer 16 is then deposited over the whole of the first major surface. The gate dielectric layer 16 may be of silicon oxide, silicon nitride, silicon oxynitride, a medium k material or a high k material. A metal gate 18 is then deposited over the whole surface and patterned as illustrated in Figure 3.
Next, a chemical-mechanical polishing step is carried out to remove the top of the fin 12, and a timed selective etch-back carried out to remove the gate dielectric 16 and gate metal 18 from the upper region 30 of the fin 12, leaving the fin exposed in the upper region 30, as illustrated in Figure 4, and the gate metal divided into a first gate 42 and a second gate 44 on opposed sides of the fin 12.
Oxide 32 is then grown up to the top of each fin leaving the top 34 of each fin 12 exposed. If required, oxide can be grown over the whole surface and then selectively etched back to expose the top 34 of the fin.
A silicon epilayer 35 is selectively grown on the exposed top 34 of each fin, resulting in the structure shown in Figure 5.
The silicon epilayer 35 is then suicided to form a suicide source layer 36. A source contacts 38 to the suicide layer are formed. First and second gate contacts 46, 48 are provided to contact the respective first and second gates 42,44 on respective opposed sides of the fin. Note that care is taken to avoid a short between the gate contacts 46,48 and the suicide source layer 36 or source contact 38.
A substrate contact 40 in contact with drain region 24 is then formed, adjacent to the fin, as illustrated in Figure 6 which is a side section of Figure 5 showing the length of the fin 12 in the horizontal direction.
This results in the structure shown in Figure 7. The structure delivers a vertical FINFET with all the advantages of reduced short channel effects. The semiconductor in the fin can be undoped because of quantum confinement effects in the fin, which leads to improved mobility. Importantly, the fabrication process is cheap compared to silicon-on- insulator devices. In particular, the buried oxide layer can be fabricated using normal oxidation processes.
In conventional, horizontal, FINFET devices the source and drain resistance can be a very significant factor leading to poor device performance. By providing a vertical rather than a horizontal FINFET the source and drain contacts are no longer affected by the length of the source and drain regions of the fin which can greatly improve (reduce) the series resistance.
In use, the separate gate contacts 46, 48 on either side of the fin can be separately controlled to allow the FINFET to be operated symmetrically or asymmetrically.
In an alternative embodiment, a plurality of FINFETs are connected to one another as illustrated in Figure 8.
Figure 8 also shows a further alternative. The deep implantation 24 extends through the full thickness of substrate 10 and the drain contact 40 is provided on the rear of the substrate instead of the source.
The bulk drain contact 40 can be used as a common contact for each of a plurality of FINFETs on a wafer, with the individual source/drain contacts 38 being connected individually or in parallel depending on the application.
Alternatively, a single FINFET only need be provided. The above embodiments are provided purely by way of example and variations are possible.
The use of the term "vertical" is used with reference to a horizontal direction of the first major surface 20 and is not intended to imply any particular orientation in space of the resulting device.

Claims

1. A method of manufacturing a field effect transistor, comprising: providing a substrate (10) having a first major surface (20); fabricating at least one semiconductor fin (12) on the first major surface; depositing gate dielectric (16) on the sides and top of the fin (12); depositing gate material (18) on the gate dielectric (16) on the sides and top of the fin (12); etching back the top of the fin (12) to expose the semiconductor of the fin and to divide the gate material (18) to form a first gate (42) and a second gate (44) on opposed sides of the fin; forming a contact (38) to the top of the fin; and forming a contact (40) in electrical contact with the base of the fin (12), so that the contacts (38,40) form source and drain contacts (38,40) for the field effect transistor.
2. A method according to claim 1 , wherein the step of fabricating at least one semiconductor fin (12) is carried out by etching the first major surface (20) to form the at least one semiconductor fin (12).
3. A method according to claim 1 or 2, further comprising the step of forming an oxide layer (14) at the base of the fin (12) on either side of the fin (12).
4. A method according to any preceding claim, further comprising implanting a dopant to form a source/drain implant (24) at the top of the fin.
5. A method according to any preceding claim wherein the step of etching back the top of the fin includes carrying out a chemical mechanical polishing step.
6. A method according to any preceding claim further comprising etching the gate dielectric (16) and the gate material (18) from the top of the sides of the fin, after the step of etching back the top of the fin.
7, A method according to any preceding claim, further comprising depositing oxide on either side of the fin to the top of the fin after etching back the top of the fin.
8. A method according to any preceding claim, wherein the step of forming a contact at the top of the fin includes growing a silicon epilayer (36) on the exposed semiconductor at the top of the fin, and suiciding the silicon epilayer (36) to form the contact (38) of suicide.
9. A field effect transistor, comprising: a substrate (10); at least one semiconductor fin (12) extending in a vertical direction; gate dielectric (16) on the sides of the fin (12); a pair of opposed gates (42,44) on either side of the fin; a contact (38) to the top of the fin (12), and a contact (40) to the base of the fin (12) at the substrate (10), the contacts (38,40) providing the source and drain contacts of the field effect transistor.
10. A field effect transistor array, comprising a plurality of field effect transistors according to claim 9 arranged on a common substrate, wherein the contact (40) to the base of each fin is a common contact (40) for all transistors and separate contacts (38) to the top of each fin are provided for each field effect transistor.
PCT/IB2006/053890 2005-11-14 2006-10-23 Vertical insulated gate field-effect transistor and method of manufacturing the same WO2007054844A2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566403B (en) * 2012-06-14 2017-01-11 聯華電子股份有限公司 Field effect transistor and manufacturing method thereof
CN106601618A (en) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof and electronic device
US9871123B2 (en) 2012-06-14 2018-01-16 United Microelectronics Corp. Field effect transistor and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19846063A1 (en) * 1998-10-07 2000-04-20 Forschungszentrum Juelich Gmbh Method of manufacturing a double-gate MOSFET
US20050164454A1 (en) * 2004-01-27 2005-07-28 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components and methods

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19846063A1 (en) * 1998-10-07 2000-04-20 Forschungszentrum Juelich Gmbh Method of manufacturing a double-gate MOSFET
US20050164454A1 (en) * 2004-01-27 2005-07-28 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components and methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566403B (en) * 2012-06-14 2017-01-11 聯華電子股份有限公司 Field effect transistor and manufacturing method thereof
US9871123B2 (en) 2012-06-14 2018-01-16 United Microelectronics Corp. Field effect transistor and manufacturing method thereof
CN106601618A (en) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof and electronic device
CN106601618B (en) * 2015-10-15 2019-12-10 中芯国际集成电路制造(上海)有限公司 semiconductor device, manufacturing method thereof and electronic device

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