WO2007056737A3 - Reconfigurable processing array having hierarchical communication network - Google Patents

Reconfigurable processing array having hierarchical communication network Download PDF

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Publication number
WO2007056737A3
WO2007056737A3 PCT/US2006/060631 US2006060631W WO2007056737A3 WO 2007056737 A3 WO2007056737 A3 WO 2007056737A3 US 2006060631 W US2006060631 W US 2006060631W WO 2007056737 A3 WO2007056737 A3 WO 2007056737A3
Authority
WO
WIPO (PCT)
Prior art keywords
communication network
tiles
hierarchical communication
processing array
reconfigurable processing
Prior art date
Application number
PCT/US2006/060631
Other languages
French (fr)
Other versions
WO2007056737A2 (en
Inventor
Anthony Mark Jones
Paul M Wasson
Michael R Butts
Original Assignee
Ambric Inc
Anthony Mark Jones
Paul M Wasson
Michael R Butts
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/340,957 external-priority patent/US7801033B2/en
Priority claimed from US11/458,061 external-priority patent/US20070038782A1/en
Application filed by Ambric Inc, Anthony Mark Jones, Paul M Wasson, Michael R Butts filed Critical Ambric Inc
Publication of WO2007056737A2 publication Critical patent/WO2007056737A2/en
Publication of WO2007056737A3 publication Critical patent/WO2007056737A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Abstract

A processor includes multiple compute units and memory units arranged in groups of abutted tiles. Multiple tiles are arranged together along with input/output interfaces to form a processor system that can be configured to perform many different operations. A hierarchical communication network efficiently connects components within the tiles and between multiple tiles.
PCT/US2006/060631 2005-11-07 2006-11-07 Reconfigurable processing array having hierarchical communication network WO2007056737A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US73462305P 2005-11-07 2005-11-07
US60/734,623 2005-11-07
US11/340,957 US7801033B2 (en) 2005-07-26 2006-01-27 System of virtual data channels in an integrated circuit
US11/340,957 2006-01-27
US11/458,061 2006-07-17
US11/458,061 US20070038782A1 (en) 2005-07-26 2006-07-17 System of virtual data channels across clock boundaries in an integrated circuit

Publications (2)

Publication Number Publication Date
WO2007056737A2 WO2007056737A2 (en) 2007-05-18
WO2007056737A3 true WO2007056737A3 (en) 2007-12-06

Family

ID=56290868

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2006/060629 WO2007056735A2 (en) 2005-11-07 2006-11-07 System of virtual data channels across clock boundaries in an integrated circuit
PCT/US2006/060631 WO2007056737A2 (en) 2005-11-07 2006-11-07 Reconfigurable processing array having hierarchical communication network

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2006/060629 WO2007056735A2 (en) 2005-11-07 2006-11-07 System of virtual data channels across clock boundaries in an integrated circuit

Country Status (2)

Country Link
EP (1) EP1952583A4 (en)
WO (2) WO2007056735A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Catholique Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0387909A (en) * 1989-05-10 1991-04-12 Seiko Epson Corp Information processor and microprocessor
US5577213A (en) * 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
US5799208A (en) * 1996-04-03 1998-08-25 United Microelectronics Corporation Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units
US6636922B1 (en) * 1999-03-17 2003-10-21 Adaptec, Inc. Methods and apparatus for implementing a host side advanced serial protocol
US6963535B2 (en) * 2000-12-28 2005-11-08 Intel Corporation MAC bus interface
US20050044324A1 (en) * 2002-10-08 2005-02-24 Abbas Rashid Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
US6816562B2 (en) * 2003-01-07 2004-11-09 Mathstar, Inc. Silicon object array with unidirectional segmented bus architecture
US7191256B2 (en) * 2003-12-19 2007-03-13 Adams Lyle E Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEE M-H. ET AL.: "Design and Implementation of the MorphoSys Reconfigurable Computing Processor", THE JOURNAL OF VLSI SIGNAL PROCESSING, vol. 24, no. 2-3, March 2000 (2000-03-01), pages 147 - 164, XP003019908, Retrieved from the Internet <URL:http://www.eng.uci.edu/morphosys/docs/JVSP.pdf> *

Also Published As

Publication number Publication date
WO2007056735A3 (en) 2007-12-13
WO2007056735A2 (en) 2007-05-18
EP1952583A2 (en) 2008-08-06
WO2007056737A2 (en) 2007-05-18
EP1952583A4 (en) 2009-02-04

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