WO2007058002A1

WO2007058002A1 - Frequency synthesizer

Info

Publication number: WO2007058002A1
Application number: PCT/JP2006/314210
Authority: WO
Inventors: Takeshi Ikeda; Hiroshi Miyagi
Original assignee: Neuro Solution Corp.
Priority date: 2005-11-18
Filing date: 2006-07-12
Publication date: 2007-05-24
Also published as: US20090085672A1; TW200721686A; CN101310444A; JP2007142791A

Abstract

By performing rough adjustment of a local oscillation frequency by a first lock loop using an up/down counter (5) and micro adjustment of the local oscillation frequency by a second lock loop using an S/H circuit (11), it is possible to eliminate the need of operation of charging and pumping a capacitor according to a phase difference and to omit an LPF using a large-scale capacitor from the frequency synthesizer. Moreover, by performing micro adjustment using the S/H circuit (11), it is possible to accurately lock the local oscillation frequency and eliminate the need of increasing the bit quantity of the up/down counter (5) to increase the control accuracy of the frequency to be locked. Thus, it is possible to rapidly lock the local oscillation frequency to a desired frequency.

Description

Description Frequency Synthesizer Technical Field

The present invention relates to a frequency synthesizer, and is particularly suitable for a frequency synthesizer using a phase lock loop. Background art

In general, a wireless communication device uses a frequency synthesizer using a PLL (Phase Locked Loop). Figure 1 shows the general structure of a frequency synthesizer using PLL. As shown in Figure 1, the frequency synthesizer consists of a quasi-generator 10 1, a programmable force counter (PC) 1 0 2

, Phase comparator 1 0 3, Charge pump circuit 1 0 4 Pass filter (

L PF) 1 0 5 It is configured with a vibration controlled voltage oscillator (V C O) 1 0 6.

The reference generator 1 0 1 generates a reference signal having a reference frequency. PC 1 0 2 divides the output frequency of V co 1 0 6 by the specified division ratio and outputs the result as a variable frequency comparison signal to phase comparator 1 0 3 Phase comparator 1 0 3 detects the phase difference between the reference signal output from the reference generator 10 0 1 and the comparison signal output from the PC 1 0 2, and the logic “L” or Γ H Output control signals from the Up and Down terminals.

The charge pump circuit 10 4 performs charge operation or pump operation of the capacitor constituting LPF 1 0 5 based on the control signal output from the Up and D own terminals of the phase comparator 10 3. Go. Figure 2 shows FIG. 4 is a diagram illustrating a configuration example of a dipump circuit 10 4. As shown in Fig. 2, the charge pump circuit 10 4 includes a first switch 1 0 4 a connected between the power source and the LPF 1 0 5 and a ground and the LPF 1 0 5. A second switch 10 4 b connected between them, and either switch is turned on based on the control signal output from the Up and D own terminals of the phase comparator 10 3 It becomes.

That is, when the phase of the comparison signal is delayed from the phase of the reference signal, a logic “HJ control signal having a pulse width corresponding to the phase difference is output from the Up terminal of the phase comparator 10 3. A logic “L” control signal is output to the D own terminal of the phase comparator 1 0 3. As a result, the first switch 10 04 a of the charge pump circuit 10 4 becomes ON, and electric charge is supplied (charged) to the capacitor of L PF 1 105.

On the other hand, when the phase of the comparison signal advances from the phase of the reference signal, a control signal of logic Γ H having a pulse width corresponding to the phase difference is output from the D ow n terminal of the phase comparator 103. At this time, a logic “L” control signal is output to the U p terminal of the phase comparator 10 3. As a result, the second switch 10 04 b of the charge pump circuit 10 4 becomes ON, and the charge charged in the capacitor of L PF 1 105 is discharged (pumped).

L PF 1 0 5 includes a capacitor and a resistor, and removes a high-frequency component of the signal output from the charge pump circuit 10 4 and outputs it to V CO 1 0 6. VCO 10 6 oscillates at a frequency proportional to the voltage of the output signal from LPF 10 5, and outputs it as a local oscillation signal outside the frequency synthesizer. Output to.

When the charge pump circuit 10 4 charges the LPF 1 0 5 due to the phase of the comparison signal being delayed from the phase of the reference signal, the oscillation frequency of the VCO 1 0 6 increases. To do. Stations output from this VCO l 0 6 The local oscillation signal is output to PC 1 0 2. At this time, the frequency of the comparison signal output from PC 10 2 increases, and the phase difference from the reference signal decreases. As a result, the frequency of the local oscillation signal output from VCO 10 6 approaches a desired frequency proportional to the frequency of the reference signal.

On the other hand, when the charge pump circuit 10 4 discharges the charge of L PF 1 0 5 due to the phase of the comparison signal being advanced from the phase of the reference signal, the oscillation frequency of V C 1 0 6 decreases. The local oscillation signal output from V C O l 0 6 is output to P C 1 0 2 ′. At this time, the frequency of the comparison signal output from P C 10 0 2 decreases and the phase difference from the reference signal decreases. As a result, the frequency of the local oscillation signal output from V COL 6 approaches a desired frequency proportional to the frequency of the reference signal.

In this way, the frequency synthesizer will eventually determine whether the frequency of the comparison signal (which is proportional to the output frequency of VCO 106) is higher or lower than the frequency of the reference signal. Operates so as to approach the frequency of the reference signal, so that the oscillation frequency of VCO 106 is boosted to a constant frequency. In this locked state, the control signal output from the phase comparator 103 is a logic “L” signal at both the U p terminal and the Dow n terminal.

In the frequency synthesizer configured as described above, the lower the frequency compared by the phase comparator 103, the larger the capacitor that constitutes the LPF 105 is used. Will have to. For this reason, it was difficult to integrate LPF 105 into a semiconductor chip. On the other hand, a technique for configuring a PLL circuit using an up-Z down counter and a DZA converter is provided (for example, see Patent Document 1). If this technology is used, the LPF using a large-capacity capacitor can be omitted from the PLL circuit. Patent Document 1 Japanese Patent Laid-Open No. 9-1 1 5 2 5 6 1 Disclosure of Invention

However, when a P and L circuit is constructed using an up-Z down counter and a D-to-D converter, the control accuracy and processing speed of the frequency to be locked are limited by the number of bits of the counter. In other words, when the D / A converter is used to enter a steady state, the mouth cycle is left open and there is no response for a certain period of time. In such an insensitive range, the oscillation frequency cannot be controlled successfully. Increasing the number of bits in the up-counter counter and DZA converter can increase the control accuracy, but the processing speed will slow down and the circuit scale will also increase. Yeah. Conversely, if the number of bits is reduced by a small δ, the processing speed will be faster, but the control accuracy will be reduced.

The present invention has been made in order to solve such a problem, and without imitating both the control accuracy of the frequency to be squeezed and the processing speed.

The purpose is to be able to integrate the P and L circuit configurations on a single semiconductor chip.

In order to solve the above-described problems, in the present invention, an up Z down force counter that performs a force count operation based on an oscillation control signal output from a phase comparator, and an up Z down count. The voltage value is obtained by D / A converting the count value output from the counter, and the local oscillation frequency is roughly adjusted by the DZA converter that supplies the voltage value to the local oscillation circuit. In addition, a non-stationary signal generation circuit that generates a non-stationary signal having a waveform in which the voltage value constantly changes in a constant cycle, and a pulse generation that generates a sampling pulse based on the comparison signal output from the variable frequency divider The voltage value of the unsteady signal is sampled and held by the circuit and the sampling pulse. The local oscillation frequency is fine-tuned by the sample and hold circuit that supplies to the local oscillation circuit.

In another aspect of the present invention, the frequency of the local oscillation signal output from the local oscillation circuit is compared with the target frequency, and the range of oscillation frequencies that the local oscillation circuit can take is determined. n (where n is an integer greater than or equal to 2) Of the divided frequency ranges, the frequency at the boundary of the frequency range to which the target frequency belongs and the frequency of the local oscillation signal counted by the frequency counter The capacitance value of the varactor diode that constitutes the local oscillation circuit is determined by the frequency comparator that compares the magnitude and the control circuit that switches the switch selection state based on the comparison result of the frequency comparator. Change the frequency to the coarsest and adjust the local oscillation frequency most coarsely. Then, as described above, the local oscillation frequency is coarsely adjusted by the up-Z down counter and the DZA converter, and the local signal is generated by the non-stationary signal generation circuit, the pulse generation circuit, and the sample hold circuit. Fine adjustment of the oscillation frequency.

According to the present invention configured as described above, since the frequency synthesizer is configured using the up-Z down counter and the DA converter, the phase difference between the reference signal and the comparison signal is taken into account. There is no need to charge or pump the capacitor accordingly. As a result, the LPF using a large-capacity capacitor can be omitted from the frequency synthesizer, and the frequency synthesizer can be integrated on one semiconductor chip. Further, according to the present invention, the local oscillation frequency is adjusted roughly using the up / down counter, and the local oscillation frequency is finely adjusted using the sample hold circuit. Therefore, it is not necessary to increase the number of bits of the up / down counter in order to increase the control accuracy of the frequency to be locked, and the local oscillation frequency can be spoken to the desired frequency at high speed. You can Moreover, the local oscillation frequency can be adjusted by fine adjustment using the sample hold circuit. The wave number can be locked with high accuracy. Capacitance for the sample hold circuit can be several p F (pico farad), and can be easily integrated on a semiconductor chip. Brief Description of Drawings

Fig. 1 shows an example of the overall configuration of a conventional frequency synthesizer. FIG. 2 is a diagram illustrating a configuration example of the charge pump circuit.

FIG. 3 is a diagram showing an example of the overall configuration of the frequency synthesizer according to the first embodiment.

Figure 4 is a waveform diagram for explaining the generation of a triangular wave signal from the reference signal by the non-stationary wave generation circuit.

FIG. 5 is a diagram illustrating a configuration example of the pulse generation circuit. --'-' · Fig. 6 is a timing chart for explaining the operation of the pulse generator configured as shown in Fig. 5.

Fig. 7 is a diagram for explaining the operation of the frequency synthesizer according to the first embodiment. Fig. 7 (a) shows the operation by the first mouth loop, and Fig. 7 (b) shows the second lock loop. FIG.

FIG. 8 is a diagram showing an example of the overall configuration of a frequency synthesizer according to the second embodiment.

FIG. 9 is a diagram showing an example of dividing the frequency used in the third loop loop according to the second embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment)

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram illustrating an overall configuration example of the frequency synthesizer according to the first embodiment. As shown in Fig. 3, the frequency synthesizer of this embodiment includes a crystal oscillator circuit 1, a reference frequency divider 2, a programmable counter (PC) 3, a phase comparator 4, an up-down counter 5, a DZA converter 6, and an adder. 7, voltage controlled oscillator (VCO) 8, unsteady wave generation circuit 9, pulse generation circuit 10, sample hold (S ZH) circuit 11 1 and buffer 12

These-each configuration :! To 1 2, even if ί or, CMO S (Complementary Metal Oxide Semiconductor ) process, ^Oh: Rui all of which are integrated on the same semiconductor chip at B i CMO S (Bipolar- CM0 S ) process. In the present embodiment, it is not essential to integrate all of these configurations 1 to 12 on one chip.

The crystal oscillation circuit 1 generates a signal having a predetermined frequency. The reference divider 2 divides the frequency of the signal output from the crystal oscillation circuit 1 by a fixed division ratio to generate a reference signal having a reference frequency. The crystal oscillator circuit 1 and the reference frequency divider 2 constitute the reference generator of the present invention. PC 3 corresponds to the variable frequency divider of the present invention, which divides the frequency of the local oscillation signal output from VC 08 by a specified division ratio and compares the result with the variable frequency. Output to phase comparator 4 as signal f _v .

The phase comparator 4 detects the phase difference between the reference signal f _r output from the reference frequency divider 2 and the comparison signal f _v output from the PC 3, and according to the detected phase difference, VC 08 Outputs the oscillation control signal from the Up pin and D own pin. The oscillation control signal output from the U p and D own terminals is a logic “L” or Γ H signal.

That is, when the phase of the comparison signal f _v is delayed from the phase of the reference signal f _r , the phase comparator 4 outputs a control signal of logic “H” having a pulse width corresponding to the phase difference from the U p terminal. To do. At this time, the phase comparator 4 is connected to the D own terminal. Outputs a logic “L” control signal. On the other hand, when the phase of the comparison signal f _v advances from the phase of the reference signal f _f , the phase comparator 4 outputs a logic “H” control signal having a pulse width corresponding to the phase difference from the D own terminal. . At this time, the phase comparator 4 outputs a logic “shi” control signal from the U p terminal. When the phase of the comparison signal f _{v and} the phase of the reference signal f _r are synchronized, the phase comparator 4 outputs a logic “L” control signal from both the U p terminal and the D own terminal.

The up / down counter 5 performs a counting operation based on a logic “H” signal output from the Up and Dow n terminals of the phase comparator 4. That is, while the logic “H” control signal is output from the Up pin of the phase comparator 4, the up-down counter 5 performs the count-up operation. On the other hand, the Do W input terminal of the phase comparator 4; ^ et al. “The up-counter 5 performs a count-down operation while the HJ control signal is being output. Force Kanta 5 does not need to increase the number of bits for the purpose of improving the control accuracy of the oscillation frequency.

The D / A converter 6 obtains a voltage value by DA-converting the count value output from the up-Z down counter 5 and supplies the obtained voltage value to the VCO 8 via the adder 7. To do. V C O 8 corresponds to the local oscillation circuit of the present invention, and oscillates at a frequency proportional to the voltage value supplied from the adder 7, and a local oscillation frequency signal obtained as a local oscillation signal f. As well as being output to the outside of the frequency synthesizer, it is output to PC3.

Non stationary wave generating circuit 9, which corresponds to a non-stationary signal generating circuit of the present invention integrates example by Uni shown in FIG. 4 (a), the reference signal f _r outputted Ri good reference divider 2 To generate a triangular wave. The triangular wave generated here is This is a non-stationary signal having a waveform in which the voltage value constantly changes at a constant rate in time. In this embodiment, an example of generating a triangular wave is described. However, a signal having a waveform whose voltage value constantly changes in time with a constant period may be used. ,. For example, as shown in Fig. 4 (b), a sawtooth wave may be generated instead. In this embodiment, the non-stationary signal is generated by integrating the reference signal f, but the method of generating the non-stationary signal is not limited to this.

The pulse generation circuit 10 includes the comparison signal f _v output from the PC 3 and the VCO

Local oscillation signal f output from 8. Based on and, a sampling pulse SP is generated for sampling the S ZH circuit 1 1. FIG. 5 is a diagram illustrating a configuration example of the pulse generation circuit 10. FIG. 6 is a timing chart for explaining the operation of the pulse generation circuit 10 configured as shown in FIG.

As shown in FIG. 5 (a), the pulse generation circuit 10 includes, for example, a D-type flip-flop 21 and an AND circuit 22. The D-type flip-flop 21 receives the comparison signal f _v from PC 3 at the data input terminal D, and the local oscillation signal f from VC 0 8 at the clock CK. Enter

. As shown in Figure 6, the local oscillation signal f. Is a signal having a shorter period than the comparison signal f _v , and is used as the operation clock of the D-type flip-flop 21. Thus, the comparison signal f _v input to the data input terminal D is the local oscillation signal f. Is output from the positive output terminal Q with a delay of 1 cycle. The inverted signal is output from the negative output terminal Q bar. AN D circuit 22 calculates the logical product of the comparison signal f _v output from PC 3 and the signal output from the negative output terminal Q bar of D-type flip-flop 21. Therefore, the local oscillation signal f during the period when the comparison signal f _v is “H”. Generates a sampling pulse SP of one shot that is logic “H” only once in a period. To do. Here, the local oscillation signal f is used as the operation clock for the D-type flip-flop 21. Although the example using is described, it is not limited to this. If the signal is synchronized with the comparison signal f _v and has a shorter cycle than the comparison signal f _v , the local oscillation signal f. Other signals may be used. For example, such a signal may be generated by another timing generation circuit (not shown).

In addition, the pulse generation circuit 10 has a comparison signal f _v output from PC 3 and

Local oscillation signal f output from V C O 8. A signal that is being divided by P C 3 (for example, 1 prescaler provided by P C 3 (where n is 1 6 3 2

The sampling pulse S P may be generated based on the output signal of 6). If the frequency division ratio at P C 3 is large, the sampling pulse SP will have a smaller duty, and will be as thin as Λ Norres φ 畐. As a result, the less signal may become invisible, so the use of a prescaler output with a small division ratio will increase the sampling pulse SP's no-less Φ 畐 to some extent. You can.

In addition, instead of using the signal in the middle of frequency division by PC 3, as shown in Fig. 5 (b), multiple D-type flip-flops 21 can be connected in cascade. good. In this way, α can be used to increase the sampling pulse S P's nores to some extent.

¾¾; Since the pulse width of the sampling pulse SP varies depending on the frequency division ratio, stabilization of the noiseless width and the multi-stage connection of the D-type flip-flop 21 at the point la However, since the frequency range is narrow whenever the pulse width changes depending on the division ratio, the amount of change in the pulse width is almost negligible.

Ό

The SZH circuit 1 1 is the sample generated by the pulse generation circuit 1 0. The voltage value of the square wave signal generated by the non-stationary wave generation circuit 9 is sampled by the gnos s P, and the held voltage value is converted to the knock 1

2 and adder 7 to supply V C O 8. The adder 7 adds the voltage value supplied from the DZA converter 6 and the voltage value supplied from the s H circuit 11 1 through the buffer 1 2, and the resulting voltage value is added. Supply to VCO 8.

In the frequency synthesizer as described above, the first lock loop is formed for the loop that passes through the phase comparator 4, the up-down counter 5 and the DZA converter 6, and the non-stationary wave generation circuit 9 and the Λ-Lus generation The second loop loop is formed by the loop that goes through circuit 1 0 and SH circuit 1 1 □

Next, the operation of the frequency synthesizer according to the first embodiment configured as described above will be described. FIG. 7 is a diagram for explaining the operation of the frequency synthesizer according to the first embodiment. FIG. 7 (a) shows the operation by the first lock loop, and FIG. 7 (b) shows the second synthesizer. Shows the operation of a locknore of Ό.

In the first lock replica, the phase comparison 4 detects the phase difference between the reference signal _r output from the reference frequency divider 2 and the comparison signal _v output from the PC 3. When the phase of the comparison signal is delayed from the phase of the reference signal, a logic “H” control signal having a pulse width corresponding to the phase difference is output from the Up terminal of the phase comparator 4. At this time, a logic “Shi” control signal is output to the D own terminal of the phase comparator 4.

The logic “H” control signal output from the U p terminal of the phase comparator 4 and the logic “L” control signal output from the D own terminal are input to the up / down force counter 5. The up / down counter 5 is synchronized with the logic “H” control signal input from the Up pin of the phase comparator 4 and counts down. Execute the pop-up operation. Then, the counted up count value is DZA converted by the DZ A converter 6 and the voltage value obtained by this is output to the VC 08 via the adder 7. Is done.

When the voltage value output from the DZA converter 6 increases due to the count-up operation of the up / down counter 5 in this way, the oscillation frequency of the VC 08 increases accordingly. Therefore, from 0 0 8? . Local oscillator signal f fed back to 3. Frequency increases, this frequency dividing ratio較信No. f _v is also increased. As a result, the frequency of the comparison signal f _v that is lower than the frequency of the reference signal f _r approaches the frequency of the reference signal f “. As a result, the local oscillation signal f output from the VC 08 frequency. is approaches the desired frequency proportional to the frequency of the reference signal f _r.

On the other hand, when the phase of the comparison signal f _v advances from the phase of the reference signal f _r , a logic “H” control signal having a pulse width corresponding to the phase difference is output from the D own terminal of the phase comparator 4. . At this time, a logical “L” control signal is output to the U p terminal of the phase comparator 4.

The logic “L” control signal output from the Up pin of the phase comparator 4 and the logic “H” control signal output from the Dow n terminal are input to the up-down force counter 5. The up-Z down counter 5 performs a count-down operation in synchronization with the logic “H” control signal input from the Dow n terminal of the phase comparator 4. Then, the counted down count value is D / A converted by the DZA converter 6, and the voltage value obtained by this is output to the VC 08 via the adder 7. The

When the voltage value output from the D / A converter 6 decreases due to the count-down operation of the up-counter 5 as described above, the oscillation frequency of the VC 08 decreases accordingly. Therefore, from 0 0 8? Local oscillation signal f fed back to 3 The frequency of The frequency of the comparison signal f _v also decreases. This ensures that the frequency of the reference signal f _r comparison signal f _v Ri was also high by frequency of, approaches the frequency of the reference signal f _r. As a result, the local oscillation signal f output from VCO 8. The frequency approaches the desired frequency proportional to the frequency of the reference signal f _r.

Ni will this Yo, frequency synthesizer, Remind as in FIG. 7 (a), be even lower high Ri by frequency frequency reference signal f "of the comparison signal f _v, the frequency of the comparison signal f _v It operates so as to approach the frequency of the reference signal f _F. Finally, the control signal output from the phase comparator 4 is logically “L” at both the Up and D own terminals. In other words, the count operation of Upno Down Counter 5 stops and a constant count value is output. However, in this embodiment, the number of bits of Up Z Down Counter 5 is not so large. It is not large and the frequency resolution is not very high. Therefore, although the processing speed of the oscillation frequency adjustment can be increased, it is difficult to accurately match the frequency of the comparison signal f _{v with} the frequency of the reference signal f “. In this embodiment, the comparison signal f _v In order to make the frequency coincide with the frequency of the reference signal fr with high accuracy, the oscillation frequency is finely adjusted in the second lock loop using the SZH circuit 11.

That is, the reference signal f output from the reference frequency divider 2 is integrated by the nonstationary wave generation circuit 9 to generate a triangular wave signal. Further, Ri by the pulse generating circuits 1 0, synchronized sampling Nguparusu SP is generated comparison signal f _v. Then, as shown in Fig. 7 (b), the voltage value of the triangular wave signal generated by the non-stationary wave generation circuit 9 by the sampling pulse SP generated by the pulse generation circuit 10 becomes S. Sampled and held by the / H circuit 11 1, the held voltage value is supplied to the VC 0 8 through the buffer 1 2 and the adder 7. When the voltage value output from the buffer 1 2 increases, for example, by such sample-hold operation, the oscillation frequency of the VCO 8 increases accordingly. Therefore, the local oscillation signal f fed back to PC 3 by VC 0 8 force. Frequency increases, and also increases the frequency of the comparison signal f _v of this by dividing. This ensures that the frequency of the reference signal f _r comparison signal f _v Ri also was lower by frequency of, approaches the frequency of the reference signal f _r. As a result, the local oscillation signal f output from VC 0 8. The frequency of becomes closer to the desired frequency proportional to the frequency of the reference signal f ^.

When the voltage value output from the buffer 1 2 decreases, the VC 0 8 oscillation frequency decreases accordingly. Therefore, from 0 0 8? Local oscillation signal f fed back to Frequency is lowered, and also lowered the frequency of the comparison signal f _v of this by dividing. This ensures that the frequency of the comparison signal f _v Ri was high by the frequency of the reference signal, will nearing the frequency of the reference signal fr. As a result, the local oscillation signal f output from VCO 8. The frequency of the signal approaches the desired frequency proportional to the frequency of the reference signal f “. Actually, the voltage value supplied from the up / down force motor 5 via the D / A converter 6 and S The voltage value supplied from the ZH circuit 1 1 through the buffer 1 2 is added by the adder 7 and the added voltage value is supplied to the VCO 8. That is, by the up / down counter 5 The voltage value finely adjusted by the S ZH circuit 1 1 is added to the roughly adjusted voltage value, and the oscillation frequency of VC 0 8 is controlled by the voltage value of the addition result.

Finally, the phase of the comparison signal f _v is completely synchronized with the phase of the reference signal f _r , and the oscillation frequency of VC O.8 is locked to a constant frequency. In the non-locked state, the voltage value V sampled and held every period of the comparison signal f _v

,, V ₂ , V 3, ... 'have different values, but when locked, This voltage value is constant. The sampling interval of SP is no constant.

As described above in detail, in the first embodiment, when the first lock loop is formed by using the key 5 and the S / H circuit is formed.

1 1 is used to form the second mouth-and-mouth zole. Then, the local oscillation frequency is coarsely adjusted by the first lock loop, and the local oscillation frequency is finely adjusted by the second lock loop. In addition, since the frequency synthesizer is configured using the up-down force Kunta 5, the capacitor is charged according to the phase difference between the reference signal f _r and the comparison signal f _v . This eliminates the need for pumping and eliminates LPFs that use large capacitors from frequency synthesizers.

Further, according to the first embodiment, it is not necessary to increase the number of bits of the cap Z down counter 5 in order to increase the control accuracy of the local oscillation frequency to be locked, and the local oscillation frequency is set to a desired frequency. Can be quickly spoken to. However, the local oscillation frequency can be accurately π-capped by fine adjustment using the s / H circuit 11 1. As described above, both the control accuracy and processing speed of the local oscillation frequency to be locked are imitated, and the configuration of the frequency synthesizer can be integrated on one semiconductor chip.

(Second embodiment)

Next, a second embodiment of the present invention will be described. FIG. 8 is a diagram showing an example of the overall configuration of a frequency synthesizer according to the second embodiment. Note that in FIG. 8, those with the same reference numerals as those shown in FIG. 3 have the same function, and therefore, redundant description thereof is omitted here. All the configurations shown in Fig. 8 are integrated on the same semiconductor chip by, for example, a CMOS process, or a BiCMOS process. However, in this embodiment, it is not essential to integrate all of the components shown in FIG. 8 on one chip.

In the second embodiment, VC 0 8 includes a plurality of varactor diodes 3 1 —, ˜3 1 _ ₈ having different capacitance values and a plurality of varactor diodes 3 1-, ˜3 1 — a plurality of sweep rate to select one of ₈ pitch 3 2 _, ~ 3 2 - ₈ and, capacitance values of a plurality of different resonant capacitors 3'3 -, ~ 3 3 - _8, the plurality of resonator Capacitors 3 3 ―, ~ 3 3 — Multiple switches for selecting one of 3 3 — ₈ , ~ 3 4 — ₈ , Resonance coin 35 and Buffer 3 6 are connected . A plurality of rose-click Thaddeus Hauts de 3 1 _, ~ 3 1 _ _8, a plurality of sweep rate pitch 3 2 _, when connected to the adder 7 via the ~ 3 2 _ ₈ crows I Tutsi SW 1 bets Furthermore, it is connected to a fixed voltage power source 40 through switch SW 2. The switch SW 1 and the switch SW 2 are controlled so that when one is turned on, the other is turned off by the control of a control circuit 39 described later. In other words, switch SW 2 is turned off when switch SW 1 is turned on, and switch SW 1 is turned off when switch SW 2 is turned on.

Multiple sweep rate pitch 3 2 -, - 3 2 - _8, the control of the control circuit 3 9, one of its is selectively turned on. Here, switch 3 2, and switch 3 2 _ ₅ , switch 3 2 — ₂ and switch 3 2 — ₆ , switch 3 2 _ ₃ and switch 3 2 — ₇ , Switch 3 2 — ₄ and Switch 3 2 — ₈ are turned on or off in synchronization with each other. Similarly ', a plurality of resonant capacitors 3 3 -, - 3 3 - ₈ and connected sweep rate Tutsi 3 4 _ between the grayed run de, a sweep rate Tutsi 3 4 - _5, sweep rate Tutsi 3 4 - ₂ sweep rate pitch 3 4 - _6, sweep rate pitch 3 4 - a ₃ and sweep rate pitch 3 4 _ _7, a set of Sui Tsu Chi 3 4 _ ₄ and sweep rate Tutsi 3 4 _ ₈ are each synchronously turned on or off . In the second embodiment, a plurality of varactor diodes with different capacitance values 3 1 — , ~ 3 1 - ₈ sweep rate pitch 3 2 out of the -, ~ 3 2 - application of the ₈ selects either Ri by the the monitor, from the adder 7 to the capacitance value of the selected rose click Tadaio de By changing the voltage according to the voltage, the local oscillation frequency of VC08 is changed. Specifically, a plurality of first rose Selector Selector die Hauts de 3 1 -, - 3 1 - ₈ roughly adjusted local oscillation frequency of the VC 0 8 Ri by the and this to select a suitable capacitance value among the To do. Thereafter, the local oscillation frequency of VC 0 8 is finely adjusted by changing the capacitance value of the selected varactor diode according to the voltage applied from the adder 7.

A plurality of rose Selector Selector diode 3 1 -, when selecting any of ~ 3 1 _ ₈ turns on the sweep rate pitch SW 2. When switch SW 2 is on, the voltage supplied to varactor diodes 3 1 —, ~ 3 1 _ ₈ via switches 3 2 —, ~ 3 2 — ₈ Fixed voltage, but multiple switches 3 2 _

, Ri by the and the child to be selectively turned on one of the ~ 3 2 _ _8, Ru can and child to a variable capacitance value of the rose-click Tadaio de繫is that the VC 0 8. As a result, the local oscillation frequency of VC 0 8 changes.

In addition, a plurality of Barack Thaddeus Hauts de 3 1 -, after you select either from in ~ 3 1 _ _8, and turns on the sweep rate pitch SW 1. When switch SW 1 is turned on, the voltage output from adder 7 is applied to varactor diodes 3 1-, ~ 3 1 _ ₈ via switches 3 2-, ~ 3 2 _ ₈ On the other hand, it is applied in the opposite direction, and the capacitor capacity (junction capacity) of the diode changes. Here, the voltage output from adder 7 is changing except when locked. By changing this voltage, the capacitance values of varactor diodes 3 1-, ~ 3 _1-8 can be varied, and the oscillation frequency of VC 0 8 can be changed.

In the second embodiment, the first lock loop using the up / down counter 5 described in the first embodiment and the second mouth loop using the S ZH circuit 11 are used. In addition, the following third package is provided. The third lock loop includes a frequency counter 3 7, a frequency comparator 3 8, and a control circuit 3 9.

The frequency counter 37 is a local oscillation signal f that can be output from VC 08 via the buffer 36. The frequency (hereinafter referred to as local oscillation frequency f) is counted. The frequency comparator 3 8 is the local oscillation frequency f counted by the frequency counter 3 7. Is compared with the target frequency f _p to be finally converged by the frequency synthesizer, and the comparison result is transmitted to the control circuit 39. Here, the target frequency f _p is supplied to the frequency comparator 3 8 from a microcomputer (not shown) or a DSP (Digital Signal Processor).

The frequency comparator 38 is a frequency range obtained by dividing the oscillation frequency range that can be taken by VC 08 by n (n is an integer of 2 or more), and the frequency range to which the target frequency f _p belongs. The frequency f _mi „, f _max hitting the boundary is compared with the local oscillation frequency f counted by the frequency counter 37, and the comparison result is transmitted to the control circuit 39. The frequencies f _min and f _max corresponding to the boundary of the frequency range to which the target frequency f _p belongs are also supplied to the frequency comparator 38 from a microcomputer or DSP (not shown).

For example, when the frequency synthesizer of this embodiment is applied to an FM radio receiver, the FM reception frequency range (76 to 108 MHz) is divided into four frequency ranges f as shown in FIG. , ~ F ₄ into 4 equal parts. Here, assuming that the target frequency f _p is 85 MHz, the frequency comparator 3 8 uses the local oscillation frequency f. Is compared with the target frequency f _p (= 85 MHz) and the comparison result is transmitted to the control circuit 39. In addition, the frequency comparator 3 8 includes the frequency f _min (= 8 4 MHz) and f _max (= 9 2 MHz) corresponding to the boundary of the frequency range f ₂ to which the target frequency f _p belongs and local oscillation. Frequency f. Compare the size of and and pass the comparison result to the control circuit 39.

The control circuit 39 receives the comparison result signal supplied from the frequency comparator 38. Based on this, switch 3 2 —! 3 2 _ ₈ , 3 4 —! 3 4 — ₈ , SW 1, SW 2 selection is switched. Initially, the control circuit 3 9 turns on the switch SW 2 and turns on the switch 3 2 3 2 — ₅ , 3 4 _,, 3 4 _ ₅ , etc. Turn off the switch. In this state, the lowest frequency range f, is selected.

In this state, the frequency comparator 3 8 has the local oscillation frequency f. And the target frequency fp (= 8 5 MHz) and the wave number f _mi „(= 8 4 MHz), f that falls on the boundary of the frequency range f ₂ to which the target frequency f _p belongs _{The magnitude of nax} (= 9 2 MHz) and the local oscillation frequency f are compared, and the comparison result is transmitted to the control circuit _39. Here, the control circuit ₃₉ has f _rai „<f. If the condition of f _max is satisfied, if not, switch SW 2 remains on and local oscillation frequency f. Switch the selected state of switches 3 2-, 3 2 _ ₈₎ 3 4-, 3 4 — ₈ according to the magnitude relationship between and the target frequency f _p .

Here, f. F _p so that the local oscillation frequency f. To a by rather large close to the frequency f _p of the goal, sweep rate pitch 3 2 3 2 - _5, 3 4 - 3 4 _ ₅ to clear the sweep rate pitch 3 2 _ _2, 3 2 _ _6, 3 4 - _2, 3 4 - toggle ₆ on. The state after this switching is the state in which the second frequency range f ₂ is selected. As a result, the capacitance value of the varactor diode connected to VCO 8 changes greatly, and the local oscillation frequency f of VC 0 8 changes. In this state, the frequency comparator 3 8 has a local oscillation frequency f. And the target frequency f _p are compared, and the frequency f _mi „. F _ma , which hits the boundary of the frequency range f ₂ , is compared with the local oscillation frequency f, and the comparison result is controlled. The control circuit 3 9 determines whether or not f _min <f and f _nax is _satisfied , because this condition is _satisfied . Switch 3 2 — ₂ , 3 2 — ₆ , 3 4 — ₂ , 3 4-6 With switch ₆ turned on, switch SW 2 is turned off and switch SW 1 is turned on. As a result, character diodes 3 _1-2 and 3 _1-6 are selected.

When switch SW 1 is on and varactor diode 3 1 — ₂ , 3 1 _ ₆ is selected, the voltage output from adder 7 is switched to switch SW 1, 3 2 _ ₂ , 3 Applied to varactor diodes 3 _1-2 and 3 1 _ ₆ via 2 _ ₆ . This ensures that the adder 7 rose pin definition by the change in voltage output from the die Hauts de 3 1 - _2, 3 1 - ₆ of capacitance艟changes, VC 0 8 of the local oscillation frequency f. Changes little by little.

In this example, the example of switching from the lowest frequency range f to the largest frequency range f ₂ , f 3, f ₄ has been described, but this switching order is merely an example. . Moreover, this Kodewa FM reception frequency range of four frequency ranges f, although the ~ f ₄ 4 are equal, not necessarily a equal.

In the frequency synthesizer according to the second embodiment configured as described above, the local oscillation frequency is most roughened by the third lock loop using the frequency counter 37, the frequency comparator 38, and the control circuit 39. Make adjustments. In other words, one of the divided frequency ranges ί, ˜ ί ₄ is specified, and a plurality of varactor diodes 3 1 _, ˜ 3 1 are set so that the VCO 8 oscillates within the specified frequency range. sweep rate pitch 3 2 _ one from among the _ _8, to select Ri by the ~ 3 2 _ _8.

The junction capacitance of the varactor diode selected in the third mouth loop can be roughly changed by the first mouth loop using the up / down counter 5. And local oscillation frequency f. Coarse adjustment (finer adjustment than the third lock loop adjustment) and the second lock loop using the S / H circuit 11 1 Selection By finely changing the junction capacitance of the selected varactor diode. Local oscillation frequency f. Make fine adjustments.

As explained in detail above, according to the second embodiment, since a method of configuring a frequency synthesizer using the up-down force counter 5 and the frequency force counter 3 7 is used, There is no need to charge or pump the capacitor according to the phase difference between the quasi signal f _r and the comparison signal f _v.

O LPF, which uses a large-capacity capacitor, can be omitted from the frequency synthesizer.

Further, according to the second embodiment, it is not necessary to increase the number of bits of the counters 5 and 37 to increase the control accuracy of the local oscillation frequency to be clocked, and the local oscillation frequency is set to a desired value. The frequency can be spoken at high speed.

. In the second embodiment, the rough range of the local oscillation frequency is specified by the third loop loop, and the local oscillation frequency is roughly adjusted by the first loop by focusing on the range. Therefore, it can be made π-clicked higher than in the first embodiment. However, the local oscillation frequency can be made to be highly accurate <D y by fine adjustment by the second lock loop using the SH circuit 11.

As described above, the configuration of the frequency synthesizer can be integrated into one semiconductor chip without imitating both the control accuracy and processing speed of the local oscillation frequency to be locked. In particular, the second embodiment relates to a frequency synthesizer that adjusts the local oscillation frequency using a node diode and a resonator diode, and a frequency synthesizer including a node diode K. This configuration can be integrated on a single semiconductor chip.

Although an example in which the frequency is divided into four has been described here, this is merely an example. When the number of divisions is 1 (when it is not divided a), it is substantially the same as in the first embodiment, so the number of divisions is 2 or more. It is preferable that the number of divisions should not be too large in view of the purpose of adjusting the frequency in the loop loop more coarsely than in the first lock loop. In addition, a plurality of varactor diodes 3 1 _, ~ 3 1 _ ₈ having different capacitance values are connected to VC 0 8, and one pair of varactor diodes is connected to switch 3.

2 _, an example has been described for selecting Ri by the ~ 3 2 _8, the present invention this is not limited constant. The capacitance values of varactor diodes 3 1 — i to 3 1 — ₈ may all be the same. In this case, instead of selecting only one pair of varactor diodes using switches 3 2 _ to 3 3 ₈ , it is possible to select one or more pairs of varactor diodes. As a result, the total capacity value of the varactor diodes connected to VC08 can be made variable.

Similarly, a plurality of resonant capacitors connected to V C 0 8 3 3 _, ~

3 be about to 3 _ _8, and the capacitance value with all the same, Ri by the and the child to select one or more pairs of co-fucoxanthin capacitor, the total capacity of Shigeru wants resonance capacitor to the VCO 8 The value can be made variable. In this way, it is possible to increase the total capacitance value that propagates in VCO 8 without increasing the capacitance value of each varactor diode or resonant capacitor. Therefore, it can be easily integrated on a semiconductor chip.

In the first and second embodiments, when the voltage supplied to VC 0 8 increases, the oscillation frequency of VC 0 8 increases, and when the voltage supplied to VC 0 8 decreases, VC 0 The example of the frequency synthesizer in which the oscillation frequency of 8 is decreased has been explained. Conversely, when the voltage supplied to VCO 8 increases, the oscillation frequency of VC 0 8 decreases and is supplied to VC 0 8 The present invention can also be applied to a frequency synthesizer in which the oscillation frequency of VC 0 8 increases as the voltage decreases.

In addition, each of the first and second embodiments described above is merely an example of actualization in carrying out the present invention. The clear technical scope should not be interpreted in a limited way. In other words, the present invention can be implemented in various forms without departing from the spirit or the main features thereof. Industrial applicability

The present invention is useful for a frequency synthesizer using a phase loop loop.

Claims

1. a local oscillation circuit that outputs a local oscillation signal at a local oscillation frequency, a variable frequency divider that divides the local oscillation signal output from the local oscillation circuit by a specified division ratio,

The variable frequency comparison signal output from the variable frequency divider and the reference generator

2 of phase comparison that outputs a signal for oscillation control of the local oscillation circuit according to the detected phase difference.

And 4

Based on the oscillation control signal output from the phase comparator.

Up / down counters that perform

A D Z A converter that obtains a voltage value by D / A converting the count value output from the up / down counter and supplies the voltage value to the local oscillation circuit;

A non-stationary signal generation circuit for generating a non-stationary signal having a waveform in which the voltage value constantly changes at a constant period in time;

Based on the comparison signal output from the variable frequency divider, a pulse generation circuit that generates a sampling pulse, and the sampling pulse generated by the pulse generation circuit generates the unsteady signal. A frequency synthesizer comprising: a sample hold circuit that samples and holds the voltage value of the unsteady signal generated by the circuit and supplies the held voltage value to the local oscillation circuit.

2. The frequency synthesizer according to claim 1, wherein the non-stationary signal generation circuit generates the non-stationary signal using the reference signal.

3. The pulse generation circuit is based on the comparison signal output from the variable frequency divider and the local oscillation signal output from the local oscillation circuit or a signal in the middle of frequency division by the variable frequency divider. The frequency synthesizer according to claim 1, wherein the sampling pulse is generated.

4. The local oscillation circuit includes a plurality of varactor diodes and a switch for selecting one of the plurality of varactor diodes, and the plurality of varactor diodes. This circuit is configured to change the local oscillation frequency by selecting one or more of these and changing their capacitance values.

A frequency force counter for counting the frequency of the local oscillation signal output from the local oscillation circuit;

The frequency of the local oscillation signal counted by the frequency counter is compared with the target frequency, and the range of oscillation frequencies that the local oscillation circuit can take is defined as n (n is (An integer greater than or equal to 2) Of the divided frequency ranges, the frequency that falls on the boundary of the frequency range to which the target frequency belongs and the frequency of the local oscillation signal counted by the frequency counter are large or small A frequency comparator for comparing

The frequency synthesizer according to claim 1, further comprising: a control circuit that switches a selection state of the switch based on a result of comparison by the frequency comparator.