WO2007066564A1 - 部品実装用ピンを形成したプリント基板 - Google Patents

部品実装用ピンを形成したプリント基板 Download PDF

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Publication number
WO2007066564A1
WO2007066564A1 PCT/JP2006/323914 JP2006323914W WO2007066564A1 WO 2007066564 A1 WO2007066564 A1 WO 2007066564A1 JP 2006323914 W JP2006323914 W JP 2006323914W WO 2007066564 A1 WO2007066564 A1 WO 2007066564A1
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WIPO (PCT)
Prior art keywords
circuit board
printed circuit
component mounting
component
electronic device
Prior art date
Application number
PCT/JP2006/323914
Other languages
English (en)
French (fr)
Inventor
Takashi Kariya
Toshiki Furutani
Takeshi Kawanishi
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Priority to EP06833717A priority Critical patent/EP1959717A4/en
Publication of WO2007066564A1 publication Critical patent/WO2007066564A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10265—Metallic coils or springs, e.g. as part of a connection element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10287—Metal wires as connectors or conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
    • Y10T29/49142—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal including metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture

Definitions

  • the Shina C chip is usually equipped with a C (chip) device.
  • a C (chip) device As an example, there is a description of the up-chip type that continues using technology such as solder bumps.
  • the mounted slave device is soldered to a huge size (for example, a semiconductor chip) of the solder pad in a chip-on-chip manner, and when the ambient temperature is lowered or lowered, the number of expansions of the electronic product and the Due to the difference, the soldering place may be damaged.
  • a huge size for example, a semiconductor chip
  • the purpose is to provide a product.
  • the pin may be made of a metal wire. Further, in the above-mentioned punt, it is a conductor chip used in an up-chip type in which an electron and an electrode pad are mounted. You can also
  • the pin may be made of an electric resistance material.
  • the hee can also be formed by using a wiring technique.
  • the pin may have an arbitrary shape selected from the group consisting of ,,,,,,,,,,,,.
  • the pin may be covered with a protective film.
  • the electronic device according to the present invention is an electronic device including a component pin-formed print and an electronic product, and the heater is a pad of the product.
  • the electronic device according to the present invention is an electronic device including a pin having a component pin formed therein and an electronic product, wherein the heater is soldered to the pad of the product via a solder. I am doing it.
  • the pin may be a mechanical element capable of elastically deforming mechanical springs in both the semiconductor device and the punch.
  • the pon- to plate and the adhesive may be used to fix each other.
  • steps () to (9) may be repeated.
  • step (c) may be performed by an ultrasonic method.
  • 024 is a view showing a part of a component forming a component.
  • 2A 2 is a diagram showing a law of an electronic device in which a pendant is a pad of a semiconductor chip.
  • 2B 2 is a diagram showing a method of an electronic device in which a solder of a pendant is soldered to a pad of a semiconductor chip in a solder pad.
  • 3 3 is a diagram for explaining the shape of the pit.
  • FIG. 4A 4 is a diagram showing a transfer step in the method of the mount that formed the component.
  • 4B 4 is a diagram showing a step in the law of the punt that formed the component.
  • 4C 4C is a diagram showing a bonding step of the ground of the surface of the surface where the component pin is formed.
  • 4D 4 is the gold of the law of the punt that formed the part
  • 4E 4 is a diagram showing a gold wire step in the method of the punt that formed the component.
  • 4 4 is a diagram showing the boss step in the method of the punt that formed the component.
  • FIG. 4 is a diagram showing a part of a component forming a component pin.
  • the plant 4 according to the embodiment has the following for connecting an electronic product such as a semiconductor chip. This can be done, for example, using the wiring technique.
  • the component pin is formed, the component pin is formed on the land of the plant, and the semiconductor chip pad is connected (2, mounting is changed to solder on the upper chip) for electrical connection.
  • Punt 4 on which the component pin according to the embodiment is formed is
  • Punt 4 is optional. In practice, because of the characteristics of the body, the sheet 4 is divided into 2 for convenience of forming a maximum of 5 and a predetermined layer and the other layer 3 of layers. If desired, a dust layer may be provided on the surface of the insulation 2.
  • Punt 4 is connected to the semiconductor by using this.
  • the 003 122 is an electronic device that includes a Punt 4 semiconductor chip on which parts are formed, and the mounting method has been clarified.
  • the component pins are on the semiconductor plate of the semiconductor chip, while the latter is different in that the component pins are connected to the semiconductor plate of the semiconductor chip by using the solder pin 2.
  • the pin of Punt 4 mechanically contacts the electrode tray formed on the semiconductor chip to secure the electrical connection.
  • Punt 4 semiconductor chips done in any manner. However, for example, both may be fixed to the electronic device. , And can be fixed to each other.
  • the interposition for connecting to the semiconductor plant 4 is changed to a component pin from the conventional one.
  • the component pins can be attached to both of the semiconductor plants 4 (mechanical thread) by elastic deformation. It is a possible mechanical element. For this reason, the quality of life due to the difference in the expansion number from the semiconductor plant 4 can be reduced.
  • the size of the component is very short, for example, in the case of impedance, electrical characteristics in terms of the degree of electric signal can be obtained.
  • the component pins are made of an electric resistance material, unnecessary voltage drop can be avoided. For example, C or any of these pins made of gold, or a component pin surface-treated with these metals.
  • the parts have a raised shape, the surroundings are taken up by the air, which enables signal transmission. Furthermore, when mechanical contact is made using the force of component pins, electrical connection with the semiconductor chip plant 4 can be ensured.
  • the plant 4 having the component pins according to the present embodiment is characterized by the components electrically connected to the land pan, the other parts of the plant 4 are optional and can be of a small size. It can also be applied to associative and warp-susceptible ass. Furthermore, since the connection with the semiconductor chip plant 4 was changed to mechanical contact by parts rather than half-pad, there is a met with a history of heat such as solder.
  • 00372 is a diagram showing a mounting structure in which the semiconductor chip of the mount 4 is secured by soldering. If desired, solder pin 2 is provided at the end of pin 4 and solder is performed in the state where the semiconductor chip is in mechanical contact with the semiconductor chip as shown in 2 to solder the component pin to the semiconductor chip pad. I am doing it. Further, if desired, the Pt 4 semiconductor chip and the Pt 4 semiconductor chip may be bound to each other by the method described above.
  • . 003383 is a diagram for explaining the shape of a part.
  • the component pins have the following shapes.
  • Pin 2 is shaped like.
  • Pin 3 of part 3 (3) is shaped in a curved shape.
  • Pin 4 of 3 (4) is shaped like a peg.
  • Pin 5 of 3 (5) is shaped like a rod.
  • Part 6 of 3 (6) is shaped like a circle. Note that, in these examples, the component pins may have any shape as long as they can be used as a tray for semiconductor chips.
  • the don bonding method (1) the conductor chip is sent in the form of a dome, and (2) the tanning mechanism recognizes the position of the semiconductor chip's bonding pad, and (3) Conduct bonding on the conductor chip side, (4) Ping (), (5) Pound conductor land area, (6) Wire, and (7) Wire end to form a void. And (8) move to the next semiconductor chip bonding pad.
  • Punt 4 is attached to the proper position (z). Twenty-five feeds through pits in spouts 26, athletes 27, clan 24, and capy 23 onto lands 5 on ponts 4. It's 25 out of 25.
  • the bonder structure is used to measure the positions of Punt 4 and 5 and calculate the landing position of Land 5.
  • the cap 23 is used to crimp the metal 22 to the land 5 landing area, and the metal is dispersed to join them.
  • the ultrasonic type is preferred because it reduces the damage of Punt4.
  • Shape metal 25 while pulling up capy 23. In order to shape it into the shape you desire, you may need to make left, right, top, and bottom operations.

Abstract

　本発明は、高集積化した半導体チップを実装しても、半導体チップとプリント基板(4)との熱膨張係数の差に起因した接続不良の発生を減少し得るプリント基板を提供することを目的とする。 　本発明に係るピリンと基板は、半導体チップ(10)と接続するため、金属線から成る部品実装用ピン(1)を備えたプリント基板(4)であって、半導体チップ(10)は、実装面に電極パッドを有するフリップチップ方式で使用される面実装型の半導体チップであり、部品実装用ピン(1)は、ワイヤボンディング技術を利用して形成されている。

Description

明 細 書
部品実装用ピンを形成したプリント基板
技術分野
[0001] 本発明は、導電性の部品実装用ピンを形成したプリント基板に関する。
背景技術
[0002] 特許文献 1：特開 2005-183466「多層プリント基板」（公開日： 2005年 7月 7日） 特許文 献 1の背景技術に、「該バイァホール 160及び導体回路 158の上層にはソルダーレ ジスト層 70が形成されており、該ソルダーレジスト層 70の開口部 71を介して、バイァ ホール 160及び導体回路 158にノ ンプ 76U、 76Dが形成されている。図示しない IC チップは、バンプ 76Uに C4 (フリップチップ)実装を行うことにより電気的な接続が取 られる。」として、半田バンプ等の技術を用いて接続したフリップチップ方式の記載が ある。
[0003] しかし、本願で開示する部品実装用ピンを形成したプリント基板に関する記載はな い。
発明の開示
発明が解決しょうとする課題
[0004] 一方、近年、半導体装置は一層高集積化しており、そのためチップサイズも巨大化 している。フリップチップ方式により、巨大サイズの電子部品（例えば半導体チップ） の電極パッドとプリント基板のランドが半田付けされた実装状態の電子機器が、周囲 温度の上昇'下降に曝されると、電子部品とプリント基板との熱膨張係数の差に起因 して、半田付け箇所が損壊することがある。
[0005] このため、従来より、高集積ィ匕した半導体を実装しても、電子部品とプリント基板と の熱膨張係数の差に起因した接続不良の発生を減少し得るプリント基板の開発が望 まれていた。
課題を解決するための手段
[0006] 従って、本発明は、高集積ィ匕した電子部品（例えば半導体チップ)を実装しても、電 子部品とプリント基板との熱膨張係数の差に起因した接続不良の発生を減少し得る プリント基板を提供することを目的とする。
[0007] 上記目的に鑑みて、本発明に係るプリント基板は、電子部品と接続するため、導電 性の部品実装用ピンを備えている。
[0008] 更に、上記プリント基板では、前記部品実装用ピンは、金属線力も成ることもできる
[0009] 更に、上記プリント基板では、電子部品は、実装面に電極パッドを有する、フリップ チップ方式で使用される面実装型の半導体チップとすることもできる。
[0010] 更に、上記プリント基板では、前記部品実装用ピンは、可撓性，弾性，屈曲性等を 有することちでさる。
[0011] 更に、上記プリント基板では、前記部品実装用ピンは、電気抵抗の低い物質から成 ることちでさる。
[0012] 更に、上記プリント基板では、前記部品実装用ピンは、ワイヤボンディング技術を利 用して形成することもできる。
[0013] 更に、上記プリント基板では、前記部品実装用ピンは、縦 S字状、横 S字状、湾曲形 状、ループ状、螺旋状、パネ状、円形状及び楕円形状から成る群から選択された任 意の形状とすることもできる。
[0014] 更に、上記プリント基板では、前記部品実装用ピンは、保護皮膜で覆われていても よい。
[0015] 更に、本発明に係る電子機器は、部品実装用ピンを形成したプリント基板と、電子 部品とを備えた電子機器であって、前記部品実装用ピンは、前記電子部品のパッド に圧接している。
[0016] 更に、本発明に係る電子機器は、部品実装用ピンを形成したプリント基板と、電子 部品とを備えた電子機器であって、前記部品実装用ピンは、前記電子部品のパッド に対して、半田バンプを介して半田接続している。
[0017] 更に、上記電子機器では、前記部品実装用ピンは、半導体装置及びプリント基板 の一方又は両方に力かる機械的エネルギを、弾性又は変形により吸収し得る機械要 素とすることちでさる。
[0018] 更に、上記電子機器では、前記プリント基板及び前記電子部品は、前記電子機器 の筐体に対して固定してもよい。
[0019] 更に、上記電子機器では、前記プリント基板及び前記電子部品は、接着剤を用い て相互に固定してもよい。
[0020] 更に、本発明に係るプリント基板の製造方法は、部品実装用ピンを形成したプリント 基板の製造方法であって、（a)適当な位置決め装置に取り付けられたプリント基板の 電極ランドの上に、金属線が搬送されるステップと、（b)プリント基板のランドのボンディ ング箇所を認識するステップと、（c)前記金属線の先端を前記ランドのボンディング箇 所に圧着し、接合するステップと、（d)前記金属線のルービングするステップと、（e)前 記金属線のワイヤカットを行うステップと、（£)切れた前記金属線の先端部溶融してボ ールを形成するステップと、（g)前記プリント基板の次のランドの上に移動するステップ とを含む。
[0021] 更に、上記プリント基板の製造方法では、ステップ (a)〜(g)を繰り返してもよ 、。
[0022] 更に、上記プリント基板の製造方法では、ステップ (c)は、超音波併用熱圧着方式で 行ってもよい。
発明の効果
[0023] 本発明によれば、高集積ィ匕した電子部品を実装しても、電子部品とプリント基板と の熱膨張係数の差に起因した接続不良の発生を減少し得るプリント基板を提供する ことができる。
図面の簡単な説明
[0024] [図 1]図 1は、部品実装用ピンを形成したプリント基板の構成の一部を示す図である。
[図 2A]図 2Aは、プリント基板の部品実装用ピンが半導体チップのパッドに圧接して V、る電子機器の実装方法を示す図である。
[図 2B]図 2Bは、プリント基板の部品実装用ピンが半導体チップのパッドに対して半 田バンプで半田接続している電子機器の実装方法を示す図である。
[図 3]図 3は、プリント基板の部品実装用ピンの種々の形状について説明する図であ る。
[図 4A]図 4Aは、部品実装用ピンを形成したプリント基板の製造方法の内の搬送ステ ップを示す図である。 [図 4B]図 4Bは、部品実装用ピンを形成したプリント基板の製造方法の内の位置認識 ステップを示す図である。
[図 4C]図 4Cは、部品実装用ピンを形成したプリント基板の製造方法の内のプリント 基板のランドへのボンディングステップを示す図である。
[図 4D]図 4Dは、部品実装用ピンを形成したプリント基板の製造方法の内の金属線 のルービング (整形)ステップを示す図である。
[図 4E]図 4Eは、部品実装用ピンを形成したプリント基板の製造方法の内の金属線の ワイヤカットステップを示す図である。
[図 4F]図 4Fは、部品実装用ピンを形成したプリント基板の製造方法の内のボール形 成ステップを示す図である。
符号の説明
[0025] 1 :部品実装用ピン、 2 :絶縁層、 4 :プリント基板、 5 :ランド，電極ランド、 6 :フ ィルドビア、 10 :半導体チップ、 11 :パッド，電極パッド、 12 :半田バンプ、 21 : 電気トーチ、 22 :ボール、 23 :キヤビラリ、 24 :クランパ、 25 :金属線、 26 :スプ ール、 27 :エアテンション、 28 :位置確認用カメラ、
発明を実施するための最良の形態
[0026] 以下、本発明に係る部品実装用ピンを形成したプリント基板の実施形態に関し、添 付の図面を参照しながら詳細に説明する。なお、図面の同じ要素に対しては同じ符 号を付して、重複した説明を省略する。
品実装用ピンを形成したプリント基板]
図 1は、部品実装用ピンを形成したプリント基板の構成の一部を示す図である。本 実施形態に係るプリント基板 4は、電子部品、例えば、半導体チップ（図示せず。）と 接続するため、導電性の部品実装用ピン 1を備えている。このピンは、例えば、ワイヤ ボンディング技術を利用して形成することができる。
[0027] 本実施形態に係る部品実装用ピンを形成したプリント基板は、予めプリント基板の 電極ランドに部品実装用ピンを形成し、半導体チップの電極パッドとを面実装（2次 元実装、フリップチップ実装における接合部材を半田力 ピンに変更した実装)で電 気的接続を行う点に特徴がある。 [0028] 本実施形態に係る部品実装用ピン 1を形成したプリント基板 4は、ランド (最外層導 体) 5に電気的に接続した、導電性の部品実装用ピン 1が形成されたことを特徴とす る。ランド 5は、フィルドビアホール 6の上に形成されていてもよい。プリント基板 4のそ の他の構成に関しては任意である。本実施形態は、最外層導体に特徴を有するため 、 1枚のプリント基板 4を、便宜的に最外層導体 5が形成された絶縁層 2と、所定の絶 縁層及び導体層力もなるその他の層 3とに分けて説明する。なお、絶縁層 2の上面に 、所望によりソルダーレジスト層を設けてもよい。
[0029] 部品実装用ピン 1の一端は、ランド 5に電気的に接続し、他端はプリント基板 4から 立ち上がつている。部品実装用ピン 1は、所望により、導電性の保護被膜 (図示せず 。）で覆っていてもよい。プリント基板 4は、この部品実装用ピン 1を利用して、半導体 装置 (図示せず。）と接続される。
[0030] 部品実装用ピン 1は、可撓性，弾性，屈曲性等を有し、好ましくは電気抵抗の低い 物質から成る。典型的には、金属線が用いられる。
[0031] 図 2A及び図 2Bは、部品実装用ピン 1を形成したプリント基板 4と半導体チップ 10と を備えた電子機器であり、実装方法を明らかにしている。前者は、部品実装用ピン 1 が半導体チップ 10のノッド 11に圧接しているのに対して、後者は、部品実装用ピン 1が半導体チップ 10のパッド 11に対してピン半田バンプ 12を用いて半田接続してい る点で相違する。
[0032] 図 2Aは、プリント基板 4の部品実装用ピン 1は、半導体チップ 10に形成された電極 ノッド 11に対して機械的に接触し、電気的接続を確保している。プリント基板 4と半導 体チップ 10との相互間の固定は、任意の方法で行われる。図示していないが、例え ば、電子機器の筐体に対して両者を固定してもよい。或いは、榭脂等の接着剤を用 V、て両者を相互に固定してもよ 、。
[0033] 図 2Aに示す実装構造は、半導体装置 10とプリント基板 4との間を接続する介在物 を、従来の半田バンプ力 部品実装用ピン 1に変更したことを特徴とする。部品実装 用ピン 1は、可撓性，弾性，屈曲性等を有しているため、電極パッド 11に押圧されて 、電気的接続を確実にしている。更に、部品実装用ピン 1は、半導体装置 10及びプリ ント基板 4の一方又は両方にカゝかる力（機械的エネルギ）を、弾性又は変形により吸 収し得る機械的要素となっている。このため、半導体装置 10とプリント基板 4との熱膨 張係数の差に起因した接続不良の発生を減少することが出来る。
[0034] 更に、部品実装用ピン 1の長さは非常に短いので、例えば特性インピーダンス Zの
0 整合、電気信号の伝搬速度の高速化の面で良好な電気的特性が得られる。同様に
、部品実装用ピン 1が、電気抵抗の低い物質から形成された場合、無用な電圧降下 が回避できる。例えば、 Cu, Au, Ag又はこれらの任意の合金製の部品実装用ピン、 これらの金属で表面処理した部品実装用ピンとした場合である。
[0035] 更に、部品実装用ピン 1は立ち上がった形状であるため、周囲を空気に取り囲まれ 、信号伝送の高速ィ匕を図ることができる。更に、部品実装用ピン 1の反発力を利用し て機械的接触を行っている場合、半導体チップ 10とプリント基板 4との良好な電気的 接続が確保できる。
[0036] 更に、本実施形態に係る部品実装用ピン 1を有するプリント基板 4は、ランド 11に電 気的に接続した部品実装用ピン 1に特徴があるため、プリント基板 4のその他の部分 に関しては任意であり、サイズの大きなプリント配線板や、反りの発生しやすいコアレ ス基板等にも適用できる。更に、半導体チップ 10とプリント基板 4との間の接続を、半 田付けでなぐ部品実装用ピン 1による機械的接触に変更したので、半田リフロー等 の熱履歴が残らな 、メリットがある。
[0037] 図 2Bは、プリント基板 4の部品実装用ピン 1と半導体チップ 10とを半田付けにより 電気的接続を確保した実装構造を示す図である。所望により、プリント基板 4の部品 実装用ピン 1の先端に半田バンプ 12を設け、図 2Aに示すように半導体チップ 10と 機械的に接触した状態で半田リフロー処理することにより、部品実装用ピン 1と半導 体チップ 10の電極パッド 11とを半田接続している。更に、所望により、上述したような 方法で、プリント基板 4と半導体チップ 10との相互の固定を行ってもよい。
[0038] 図 3は、部品実装用ピン 1の種々の形状について説明する図である。部品実装用ピ ン 1は、可撓性，弾性，屈曲性等を有し、図 2Aで示したように半導体チップ 10の電 極パッド 11に圧接している。この実装構造を実現するため、部品実装用ピン 1の形状 は次のようなものがある。
[0039] 図 3(1)の部品実装用ピン 1-1は、縦 S字状の形状に整形されている。図 3(2)の部品 実装用ピン 1-2は、横 S字状の形状に整形されている。図 3(3)の部品実装用ピン 1-3 は、湾曲形状に整形されている。図 3(4)の部品実装用ピン 1-4は、ループ状に整形さ れている。図 3(5)の部品実装用ピン 1-5は、螺旋状又はパネ状に整形されている。図 3(6)の部品実装用ピン 1-6は、円形又は楕円形に整形されている。なお、これらの形 状は例示であって、部品実装用ピン 1は、半導体チップ 10の電極パッド 11に圧接し 得る形状であれば、任意の形状であってよい。
品実装用ピンを形成したプリント基板の製造方法]
図 4A〜図 4Dを用いて、部品実装用ピンを形成したプリント基板の製造方法につ いて、従来のワイヤボンディング技術と比較しながら、説明する。
[0040] 先ず、従来のワイヤボンディング技術は、例えばネイルヘッドボンディング法では、（ 1)半導体チップがリードフレームに搭載されて搬送され、（2)パターン認識機構により 半導体チップのボンディングパッドの位置を認識し、（3)半導体チップ側のボンディン グを行い、（4)金属線のルービング (整形)を行い、（5)プリント基板の搭載半導体チッ プ隣接領域のランドへボンディングし、（6)金属線のワイヤカットを行い、（7)切れたワイ ャ先端を溶力しボールを形成し、（8)次の半導体チップのボンディングパッドに移動す る、諸ステップ力 なる。
[0041] 本実施形態に係るの部品実装用ピン 1を形成したプリント基板 4の製造方法では、 上記の (1)搬送、（2)位置認識、（5)プリント基板のランドへのボンディング、（4)金属線の ルービング (整形）、（6)金属線のワイヤカット、（7)ボール形成、（8)移動、をこの順序で 利用している。
[0042] なお、部品搭載面に電極ランド 5が形成されたプリント基板 4は製造されているもの とする。このプリント基板 4を使用して、次の各工程の処理を行う。
[0043] (a)搬送（図 4A参照）：
プリント基板 4は適当な位置決め装置（図示せず。）に取り付けられている。金属線 25 は、スプール 26カゝらエアテンション 27、クランパ 24、キヤビラリ 23の中の穴を通って、 プリント基板 4のランド 5の上に供給される。金属線 25の先端は、溶融したボール状 2 2になっている。
[0044] (b)位置認識 (図 4B参照）： 位置確認用カメラ 28を利用した、ボンダの位置認識機構により、プリント基板 4のラ ンド 5の位置を計測し、ランド 5のボンディング箇所を計算する。
[0045] (c)プリント基板のランドへのボンディング（図 4C参照）：
キヤビラリ 23で金属線 25のボール 22をランド 5のボンディング箇所に圧着し、金属 の拡散により接合する。プリント基板 4への熱ダメージを少なくするため、超音波併用 熱圧着方式が好ましい。
[0046] (d)金属線のルービング (整形）（図 4D参照）：
キヤビラリ 23を引き上げながら、金属線 25の整形を行う。所望の形状に整形するた めには、左右上下のリバース動作を行うこともある。
[0047] (e)金属線のワイヤカット（図 4E参照）：
キヤビラリ 23が上昇したときにクランパ 24で金属線のワイヤカットを行う。
[0048] (Dボール形成 (図 4F参照）：
切れた金属線 25の先端部に向けて電気トーチ 21から放電を飛ばすことにより先端 部を溶融してボールを形成する。この段階で、金属線 25は、部品実装用ピン 1となる
[0049] (g)移動（図示せず。）：
次のプリント基板 4のランド 5の上に移動する。
[0050] 上記工程 (a)〜(g)を高速で繰り返すことにより、部品実装用ピンを形成したプリント 基板を製造することができる。なお、（f)の工程は削除することも可能である。
[その他]
以上により、部品実装用ピンを形成したプリント基板の実施形態について説明した 力 これらは例示であって、本発明はこれに限定されない。当業者が容易になしえる 付加'削除 '変換'改良等は、本発明の範囲に含まれる。
[0051] 本発明の技術的範囲は、添付の特許請求の範囲の記載によって定められる。

Claims

請求の範囲
[I] 電子部品と接続するため、導電性の部品実装用ピンを備えたプリント基板。
[2] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、金属線から成る、プリント基板。
[3] 請求項 1に記載のプリント基板において、
電子部品は、実装面に電極パッドを有する、フリップチップ方式で使用される面実 装型の半導体チップである、プリント基板。
[4] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、可撓性，弾性，屈曲性等を有する、プリント基板。
[5] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、電気抵抗の低い物質から成る、プリント基板。
[6] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、ワイヤボンディング技術を利用して形成される、プリント基 板。
[7] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、縦 S字状、横 S字状、湾曲形状、ループ状、螺旋状、パネ 状、円形状及び楕円形状から成る群から選択された任意の形状である、プリント基板
[8] 請求項 1に記載のプリント基板において、
前記部品実装用ピンは、保護皮膜で覆われている、プリント基板。
[9] 部品実装用ピンを形成したプリント基板と、
電子部品とを備えた電子機器であって、
前記部品実装用ピンは、前記電子部品のパッドに圧接している、電子機器。
[10] 部品実装用ピンを形成したプリント基板と、
電子部品とを備えた電子機器であって、
前記部品実装用ピンは、前記電子部品のパッドに対して、半田バンプを介して半 田接続している、電子機器。
[II] 請求項 9又は 10に記載の電子機器において、 前記部品実装用ピンは、半導体装置及びプリント基板の一方又は両方に力かる機 械的エネルギを、弾性又は変形により吸収し得る機械要素である、電子機器。
[12] 請求項 9又は 10に記載の電子機器において、
前記プリント基板及び前記電子部品は、前記電子機器の筐体に対して固定されて いる、電子機器。
[13] 請求項 9又は 10に記載の電子機器において、
前記プリント基板及び前記電子部品は、接着剤を用 Vヽて相互に固定されて ヽる、 電子機器。
[14] 部品実装用ピンを形成したプリント基板の製造方法に於いて、
(a)適当な位置決め装置に取り付けられたプリント基板の電極ランドの上に、金属線 が搬送されるステップと、
(b)プリント基板のランドのボンディング箇所を認識するステップと、
(c)前記金属線の先端を前記ランドのボンディング箇所に圧着し、接合するステップ と、
(d)前記金属線のルービングするステップと、
(e)前記金属線のワイヤカットを行うステップと、
(£)切れた前記金属線の先端部溶融してボールを形成するステップと、
(g)前記プリント基板の次のランドの上に移動するステップとを含む、製造方法。
[15] 請求項 14に記載の部品実装用ピンを形成したプリント基板の製造方法に於いて、 ステップ (a)〜(g)を繰り返す、製造方法。
[16] 請求項 14に記載の部品実装用ピンを形成したプリント基板の製造方法に於いて、 ステップ (c)は、超音波併用熱圧着方式で行われる、製造方法。
PCT/JP2006/323914 2005-12-09 2006-11-30 部品実装用ピンを形成したプリント基板 WO2007066564A1 (ja)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US8602593B2 (en) * 2009-10-15 2013-12-10 Cree, Inc. Lamp assemblies and methods of making the same
RU2554892C2 (ru) * 2009-11-09 2015-06-27 Конинклейке Филипс Электроникс Н.В. Криволинейный преобразователь высокоинтенсивного фокусированного ультразвука с деформируемыми электрическими соединениями
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US8491315B1 (en) * 2011-11-29 2013-07-23 Plastronics Socket Partners, Ltd. Micro via adapter socket
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US9818734B2 (en) 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US9385052B2 (en) 2012-09-14 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
WO2014109014A1 (ja) * 2013-01-09 2014-07-17 株式会社日立製作所 半導体装置およびその製造方法
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
TWI712220B (zh) * 2015-08-20 2020-12-01 美商Ｒ＆Ｄ電路公司 無論何處的跡線互連
EP3190400A1 (en) 2016-01-08 2017-07-12 Openfield A downhole fluid properties analysis probe, tool and method
WO2020235211A1 (ja) * 2019-05-20 2020-11-26 株式会社新川 ピン状ワイヤ成形方法及びワイヤボンディング装置
US20220162058A1 (en) * 2020-11-24 2022-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Wire-bond damper for shock absorption

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11506829A (ja) * 1995-06-07 1999-06-15 ゼロックス コーポレイション フォトリソグラフィーでパターニングしたスプリング・コンタクト
JP2000512437A (ja) * 1997-05-15 2000-09-19 フォームファクター，インコーポレイテッド リソグラフ的に画定される超小型電子接触構造体
JP2001502851A (ja) * 1997-05-06 2001-02-27 フォームファクター，インコーポレイテッド 対応する端子から離れた領域に弾性接触要素を有する電子部品

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2049976A (en) * 1935-05-15 1936-08-04 Gen Engineering Co Method and apparatus for controlling combustion in multiple and single retort stokers
US4828346A (en) * 1985-10-08 1989-05-09 The Boc Group, Inc. Transparent article having high visible transmittance
US5476211A (en) * 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
JPH02218143A (ja) 1989-02-20 1990-08-30 Hitachi Ltd 半導体装置およびその製造方法
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
WO1991013533A1 (en) * 1990-03-01 1991-09-05 Motorola, Inc. Selectively releasing conductive runner and substrate assembly
JP2948039B2 (ja) 1992-12-28 1999-09-13 株式会社日立製作所 回路基板
JPH077263A (ja) 1993-06-14 1995-01-10 Nippon Avionics Co Ltd ジャンパ布線のボンディング方法およびその装置
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
WO1996015458A1 (en) * 1994-11-15 1996-05-23 Formfactor, Inc. Probe card assembly and kit, and methods of using same
JP2986677B2 (ja) 1994-06-02 1999-12-06 富士通株式会社 超音波熱圧着装置
DE4437260C1 (de) 1994-10-18 1995-10-19 Siemens Ag Mikromechanisches Relais
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
EP0774888B1 (en) 1995-11-16 2003-03-19 Matsushita Electric Industrial Co., Ltd Printed wiring board and assembly of the same
US6245444B1 (en) 1997-10-02 2001-06-12 New Jersey Institute Of Technology Micromachined element and method of fabrication thereof
JPH11326379A (ja) * 1998-03-12 1999-11-26 Fujitsu Ltd 電子部品用コンタクタ及びその製造方法及びコンタクタ製造装置
EP1135690B1 (en) * 1998-12-02 2003-06-04 Formfactor, Inc. Lithographic contact elements
JP4458582B2 (ja) 1999-01-04 2010-04-28 イビデン株式会社 パッケージ基板
KR100502222B1 (ko) 1999-01-29 2005-07-18 마츠시타 덴끼 산교 가부시키가이샤 전자부품의 실장방법 및 그 장치
US6287126B1 (en) * 1999-06-25 2001-09-11 International Business Machines Corporation Mechanical attachment means used as electrical connection
US6229683B1 (en) 1999-06-30 2001-05-08 Mcnc High voltage micromachined electrostatic switch
US6827584B2 (en) 1999-12-28 2004-12-07 Formfactor, Inc. Interconnect for microelectronic structures with enhanced spring characteristics
US6396677B1 (en) * 2000-05-17 2002-05-28 Xerox Corporation Photolithographically-patterned variable capacitor structures and method of making
US6392524B1 (en) * 2000-06-09 2002-05-21 Xerox Corporation Photolithographically-patterned out-of-plane coil structures and method of making
KR20010112575A (ko) 2000-06-09 2001-12-20 송길봉 자동 밸브
US6290510B1 (en) * 2000-07-27 2001-09-18 Xerox Corporation Spring structure with self-aligned release material
JP4508380B2 (ja) 2000-08-23 2010-07-21 イビデン株式会社 多層プリント配線板の製造方法
JP2003013247A (ja) * 2001-04-24 2003-01-15 Murata Mfg Co Ltd 無電解銅めっき浴及び高周波用電子部品
US6560861B2 (en) 2001-07-11 2003-05-13 Xerox Corporation Microspring with conductive coating deposited on tip after release
JP3860000B2 (ja) 2001-09-07 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
JP2003198068A (ja) 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造
JP2004198352A (ja) 2002-12-20 2004-07-15 Yamaha Corp 導通試験方法及びそれに用いるプローブユニット
JP2004311919A (ja) 2003-02-21 2004-11-04 Shinko Electric Ind Co Ltd スルーホールフィル方法
JP2004040138A (ja) 2003-10-27 2004-02-05 Ibiden Co Ltd ビルドアップ多層プリント配線板
US7160121B2 (en) * 2003-12-15 2007-01-09 Palo Alto Research Center Incorporated Stressed metal contact with enhanced lateral compliance
JP2005183466A (ja) 2003-12-16 2005-07-07 Ibiden Co Ltd 多層プリント配線板
US6935867B1 (en) 2004-05-24 2005-08-30 Alps Electric Co., Ltd. Connection unit between substrated and component and method for fabricating connection unit
US7459795B2 (en) 2004-08-19 2008-12-02 Formfactor, Inc. Method to build a wirebond probe card in a many at a time fashion
US7230440B2 (en) 2004-10-21 2007-06-12 Palo Alto Research Center Incorporated Curved spring structure with elongated section located under cantilevered section
JP4559936B2 (ja) * 2004-10-21 2010-10-13 アルプス電気株式会社 無電解めっき方法およびこの方法を用いた回路形成方法
JP2006208358A (ja) * 2004-12-28 2006-08-10 Tdk Corp センサ
US7449779B2 (en) * 2005-03-22 2008-11-11 Tessera, Inc. Wire bonded wafer level cavity package
JP2007165383A (ja) * 2005-12-09 2007-06-28 Ibiden Co Ltd 部品実装用ピンを形成したプリント基板
JP4848752B2 (ja) * 2005-12-09 2011-12-28 イビデン株式会社 部品実装用ピンを有するプリント配線板及びこれを使用した電子機器
JP4654897B2 (ja) * 2005-12-09 2011-03-23 イビデン株式会社 部品実装用ピンを有するプリント配線板の製造方法
US7530814B2 (en) * 2007-09-25 2009-05-12 Intel Corporation Providing variable sized contacts for coupling with a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11506829A (ja) * 1995-06-07 1999-06-15 ゼロックス コーポレイション フォトリソグラフィーでパターニングしたスプリング・コンタクト
JP2001502851A (ja) * 1997-05-06 2001-02-27 フォームファクター，インコーポレイテッド 対応する端子から離れた領域に弾性接触要素を有する電子部品
JP2000512437A (ja) * 1997-05-15 2000-09-19 フォームファクター，インコーポレイテッド リソグラフ的に画定される超小型電子接触構造体

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1959717A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US7731504B2 (en) 2005-12-09 2010-06-08 Ibiden Co., Ltd. Printed board with component mounting pin
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US7891089B2 (en) 2005-12-09 2011-02-22 Ibiden Co., Ltd. Printed board with component mounting pin
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin

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EP1959717A4 (en) 2010-10-06
KR20070100385A (ko) 2007-10-10
US7731504B2 (en) 2010-06-08
CN101147435A (zh) 2008-03-19
US7891089B2 (en) 2011-02-22
US20090053911A1 (en) 2009-02-26
US7497694B2 (en) 2009-03-03
TWI351244B (ja) 2011-10-21
US20070190819A1 (en) 2007-08-16
TW200746958A (en) 2007-12-16
JP2007165383A (ja) 2007-06-28
EP1959717A1 (en) 2008-08-20
US20090053910A1 (en) 2009-02-26

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