WO2007067684A3 - Method of producing and operating a low power junction field effect transistor - Google Patents

Method of producing and operating a low power junction field effect transistor Download PDF

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Publication number
WO2007067684A3
WO2007067684A3 PCT/US2006/046666 US2006046666W WO2007067684A3 WO 2007067684 A3 WO2007067684 A3 WO 2007067684A3 US 2006046666 W US2006046666 W US 2006046666W WO 2007067684 A3 WO2007067684 A3 WO 2007067684A3
Authority
WO
WIPO (PCT)
Prior art keywords
inverter
cjfet
field effect
junction field
producing
Prior art date
Application number
PCT/US2006/046666
Other languages
French (fr)
Other versions
WO2007067684A2 (en
Inventor
Ashok Kumar Kapoor
Original Assignee
Dsm Solutions Inc
Ashok Kumar Kapoor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsm Solutions Inc, Ashok Kumar Kapoor filed Critical Dsm Solutions Inc
Priority to CA002631032A priority Critical patent/CA2631032A1/en
Priority to JP2008544504A priority patent/JP2009518870A/en
Priority to EP06844945A priority patent/EP1961120A4/en
Publication of WO2007067684A2 publication Critical patent/WO2007067684A2/en
Publication of WO2007067684A3 publication Critical patent/WO2007067684A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
    • H03K19/0941—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors of complementary type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Abstract

A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
PCT/US2006/046666 2005-12-07 2006-12-07 Method of producing and operating a low power junction field effect transistor WO2007067684A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002631032A CA2631032A1 (en) 2005-12-07 2006-12-07 Method of producing and operating a low power junction field effect transistor
JP2008544504A JP2009518870A (en) 2005-12-07 2006-12-07 Manufacturing method and operating method of low power junction field effect transistor
EP06844945A EP1961120A4 (en) 2005-12-07 2006-12-07 Method of producing and operating a low power junction field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74808905P 2005-12-07 2005-12-07
US60/748,089 2005-12-07

Publications (2)

Publication Number Publication Date
WO2007067684A2 WO2007067684A2 (en) 2007-06-14
WO2007067684A3 true WO2007067684A3 (en) 2008-04-10

Family

ID=38123487

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/046666 WO2007067684A2 (en) 2005-12-07 2006-12-07 Method of producing and operating a low power junction field effect transistor

Country Status (8)

Country Link
US (2) US7474125B2 (en)
EP (1) EP1961120A4 (en)
JP (1) JP2009518870A (en)
KR (1) KR20080086484A (en)
CN (1) CN101326719A (en)
CA (1) CA2631032A1 (en)
TW (1) TW200805882A (en)
WO (1) WO2007067684A2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745301B2 (en) 2005-08-22 2010-06-29 Terapede, Llc Methods and apparatus for high-density chip connectivity
US8957511B2 (en) 2005-08-22 2015-02-17 Madhukar B. Vora Apparatus and methods for high-density chip connectivity
US7592841B2 (en) * 2006-05-11 2009-09-22 Dsm Solutions, Inc. Circuit configurations having four terminal JFET devices
EP1961120A4 (en) * 2005-12-07 2008-12-31 Dsm Solutions Inc Method of producing and operating a low power junction field effect transistor
US7633101B2 (en) * 2006-07-11 2009-12-15 Dsm Solutions, Inc. Oxide isolated metal silicon-gate JFET
US7764137B2 (en) * 2006-09-28 2010-07-27 Suvolta, Inc. Circuit and method for generating electrical solutions with junction field effect transistors
US7400172B2 (en) * 2006-10-16 2008-07-15 Freescale Semiconductor, Inc. Miller capacitance tolerant buffer element
US7525163B2 (en) * 2006-10-31 2009-04-28 Dsm Solutions, Inc. Semiconductor device, design method and structure
US20080099796A1 (en) * 2006-11-01 2008-05-01 Vora Madhukar B Device with patterned semiconductor electrode structure and method of manufacture
US20080265936A1 (en) * 2007-04-27 2008-10-30 Dsm Solutions, Inc. Integrated circuit switching device, structure and method of manufacture
US7629812B2 (en) * 2007-08-03 2009-12-08 Dsm Solutions, Inc. Switching circuits and methods for programmable logic devices
US8035139B2 (en) * 2007-09-02 2011-10-11 Suvolta, Inc. Dynamic random access memory having junction field effect transistor cell access device
US20090168508A1 (en) * 2007-12-31 2009-07-02 Dsm Solutions, Inc. Static random access memory having cells with junction field effect and bipolar junction transistors
KR101015847B1 (en) * 2008-01-18 2011-02-23 삼성모바일디스플레이주식회사 Thin film transistor and fabricating for the same and organic light emitting diode device display comprising the same
US20090201075A1 (en) * 2008-02-12 2009-08-13 Yannis Tsividis Method and Apparatus for MOSFET Drain-Source Leakage Reduction
US8207784B2 (en) 2008-02-12 2012-06-26 Semi Solutions, Llc Method and apparatus for MOSFET drain-source leakage reduction
US7710148B2 (en) * 2008-06-02 2010-05-04 Suvolta, Inc. Programmable switch circuit and method, method of manufacture, and devices and systems including the same
US8120072B2 (en) 2008-07-24 2012-02-21 Micron Technology, Inc. JFET devices with increased barrier height and methods of making same
EP2605407A1 (en) * 2011-12-13 2013-06-19 Soitec Tristate gate
TWI566328B (en) 2013-07-29 2017-01-11 高效電源轉換公司 Gan transistors with polysilicon layers for creating additional components
JP7009033B2 (en) * 2018-02-06 2022-01-25 エイブリック株式会社 Reference voltage generator
US11271108B2 (en) 2020-04-08 2022-03-08 International Business Machines Corporation Low-noise gate-all-around junction field effect transistor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307223B1 (en) * 1998-12-11 2001-10-23 Lovoltech, Inc. Complementary junction field effect transistors
US6496034B2 (en) * 2001-02-09 2002-12-17 Micron Technology, Inc. Programmable logic arrays with ultra thin body transistors

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038563A (en) * 1975-10-03 1977-07-26 Mcdonnell Douglas Corporation Symmetrical input nor/nand gate circuit
US4700461A (en) * 1986-09-29 1987-10-20 Massachusetts Institute Of Technology Process for making junction field-effect transistors
US6026011A (en) * 1998-09-23 2000-02-15 Intel Corporation CMOS latch design with soft error immunity
US20050104132A1 (en) * 2001-01-23 2005-05-19 Tsutomu Imoto Semiconductor device and manufacturing method thereof
US6624663B2 (en) * 2001-10-31 2003-09-23 Hewlett-Packard Development Company, L.P. Low threshold voltage silicon-on-insulator clock gates
FR2853474B1 (en) * 2003-04-02 2005-07-08 Soisic TRIGGER CIRCUIT FROM SCHMITT IN
US7038515B2 (en) * 2003-12-19 2006-05-02 Intel Corporation Soft-error rate hardened pulsed latch
US20060103442A1 (en) * 2004-11-18 2006-05-18 Krueger Daniel W Memory element with improved soft-error rate
US7569873B2 (en) * 2005-10-28 2009-08-04 Dsm Solutions, Inc. Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
EP1961120A4 (en) * 2005-12-07 2008-12-31 Dsm Solutions Inc Method of producing and operating a low power junction field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307223B1 (en) * 1998-12-11 2001-10-23 Lovoltech, Inc. Complementary junction field effect transistors
US6496034B2 (en) * 2001-02-09 2002-12-17 Micron Technology, Inc. Programmable logic arrays with ultra thin body transistors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WILSON ET AL.: "Process Optimization of High Performance Ion Implanted GaAs JFETs", GALLIUM ARSENIDE INTEGRATED CIRCUIT (GAAS IC) SYMPOSIUM. 1992. TECHNICAL DIGEST. 1992. 14TH ANNUAL IEEE, 4 October 1992 (1992-10-04) - 7 October 1992 (1992-10-07), pages 169 - 172, XP010066793 *

Also Published As

Publication number Publication date
EP1961120A4 (en) 2008-12-31
CA2631032A1 (en) 2007-06-14
EP1961120A2 (en) 2008-08-27
US7474125B2 (en) 2009-01-06
TW200805882A (en) 2008-01-16
US20070126478A1 (en) 2007-06-07
CN101326719A (en) 2008-12-17
JP2009518870A (en) 2009-05-07
WO2007067684A2 (en) 2007-06-14
KR20080086484A (en) 2008-09-25
US20090184734A1 (en) 2009-07-23

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