WO2007067739A1 - Memory access request arbitration - Google Patents
Memory access request arbitration Download PDFInfo
- Publication number
- WO2007067739A1 WO2007067739A1 PCT/US2006/046877 US2006046877W WO2007067739A1 WO 2007067739 A1 WO2007067739 A1 WO 2007067739A1 US 2006046877 W US2006046877 W US 2006046877W WO 2007067739 A1 WO2007067739 A1 WO 2007067739A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory access
- memory
- access request
- page
- interval
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
- G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- one or both of the arbiters 106 and 108 perform this comparison.
- one or both of the arbiters 106 and 108 can store a subset of the most significant bits (MSBs) of the address associated with the immediately previous processed memory access request (e.g., ADDRp[MSB n :MSB n . x ]) in a register or other memory location (not shown) and the devices 130, 132, 134, 136, 138 and 140 can provide a corresponding subset of the most significant bits (MSBs) of the memory address associated with their memory access request (e.g., ADDR,[MSB n :MSB n .
- MSBs most significant bits
- the sequential selection of memory access requests from the same device may be interrupted if a higher priority memory access request is received from another device. In other embodiments, the sequential selection of memory access requests from the same device can supercede a higher-priority memory access request from another device. Moreover, the predetermined maximum number of repeated selections may vary depending on the priority of the memory access request from another device.
- another implementation of the preferential memory access request selection at block 208 can include determining whether a number of buffered memory access requests from any of the devices meets or exceeds a pi edetermined threshold at block 502. If not, at block 504 a memory access request is selected from the devices using, for example, round robin selection or another selection scheme. Otherwise, at block 506 some or all of the buffered memory access requests are provided to the memory controller by the arbiter for processing during sequential memory access intervals.
- an exemplary arbiter 700 for implementing one or more of the arbitration techniques disclosed herein is illustrated in accordance with at least one embodiment of the present disclosure.
- the arbiter 700 c include a request selector module 702, an indicator analysis module 704, multiplexers 706 and 708, and registers 710, 712, 714, 716, 718 and 720.
- the modules 702 and 708 may be implemented as software, hardware, firmware, or combinations thereof.
- the register 710 stores a value identifying the device associated with the memory access request selected for the previous memory access interval.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0811767A GB2446997B (en) | 2005-12-09 | 2006-12-08 | Memory access request arbitration |
CN2006800462409A CN101326504B (en) | 2005-12-09 | 2006-12-08 | Memory access request arbitration |
JP2008544532A JP2009518753A (en) | 2005-12-09 | 2006-12-08 | Arbitration of memory access requests |
DE112006003358.1T DE112006003358B4 (en) | 2005-12-09 | 2006-12-08 | Distribution of memory access requests |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/297,856 | 2005-12-09 | ||
US11/297,856 US7426621B2 (en) | 2005-12-09 | 2005-12-09 | Memory access request arbitration |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007067739A1 true WO2007067739A1 (en) | 2007-06-14 |
Family
ID=37865831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/046877 WO2007067739A1 (en) | 2005-12-09 | 2006-12-08 | Memory access request arbitration |
Country Status (8)
Country | Link |
---|---|
US (1) | US7426621B2 (en) |
JP (1) | JP2009518753A (en) |
KR (1) | KR20080075910A (en) |
CN (1) | CN101326504B (en) |
DE (1) | DE112006003358B4 (en) |
GB (1) | GB2446997B (en) |
TW (1) | TW200728983A (en) |
WO (1) | WO2007067739A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018013157A1 (en) * | 2016-07-15 | 2018-01-18 | Advanced Micro Devices, Inc. | Command arbitration for high speed memory interfaces |
Families Citing this family (15)
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US7353317B2 (en) * | 2004-12-28 | 2008-04-01 | Intel Corporation | Method and apparatus for implementing heterogeneous interconnects |
JP5261993B2 (en) * | 2007-06-15 | 2013-08-14 | 富士通セミコンダクター株式会社 | Display control circuit and display device |
TWI385634B (en) * | 2008-04-02 | 2013-02-11 | Novatek Microelectronics Corp | Microprocessor device and related method for an lcd controller |
US8266393B2 (en) * | 2008-06-04 | 2012-09-11 | Microsoft Corporation | Coordination among multiple memory controllers |
JP5380322B2 (en) * | 2010-02-17 | 2014-01-08 | 京セラドキュメントソリューションズ株式会社 | Memory master device |
US8572322B2 (en) * | 2010-03-29 | 2013-10-29 | Freescale Semiconductor, Inc. | Asynchronously scheduling memory access requests |
US8560796B2 (en) * | 2010-03-29 | 2013-10-15 | Freescale Semiconductor, Inc. | Scheduling memory access requests using predicted memory timing and state information |
KR101292309B1 (en) * | 2011-12-27 | 2013-07-31 | 숭실대학교산학협력단 | Semiconductor chip and control method of memory, and recording medium storing program for executing method of the same in computer |
CN104067309A (en) * | 2011-12-28 | 2014-09-24 | 英特尔公司 | Pipelined image processing sequencer |
US8751830B2 (en) * | 2012-01-23 | 2014-06-10 | International Business Machines Corporation | Memory address translation-based data encryption/compression |
WO2014147769A1 (en) * | 2013-03-19 | 2014-09-25 | 富士通株式会社 | Control apparatus, device access method, device access program, and information processing apparatus |
GB2522653A (en) | 2014-01-31 | 2015-08-05 | Ibm | Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system |
TWI553483B (en) * | 2014-10-13 | 2016-10-11 | 瑞昱半導體股份有限公司 | Processor and method for accessing memory |
US10402937B2 (en) | 2017-12-28 | 2019-09-03 | Nvidia Corporation | Multi-GPU frame rendering |
CN110729006B (en) | 2018-07-16 | 2022-07-05 | 超威半导体(上海)有限公司 | Refresh scheme in a memory controller |
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EP0901080A1 (en) * | 1997-09-08 | 1999-03-10 | STMicroelectronics Ltd. | Arbitration system |
US6088772A (en) * | 1997-06-13 | 2000-07-11 | Intel Corporation | Method and apparatus for improving system performance when reordering commands |
US6145065A (en) * | 1997-05-02 | 2000-11-07 | Matsushita Electric Industrial Co., Ltd. | Memory access buffer and reordering apparatus using priorities |
US6272583B1 (en) * | 1997-12-26 | 2001-08-07 | Mitsubishi Denki Kabushiki Kaisha | Microprocessor having built-in DRAM and internal data transfer paths wider and faster than independent external transfer paths |
US20030061459A1 (en) * | 2001-09-27 | 2003-03-27 | Nagi Aboulenein | Method and apparatus for memory access scheduling to reduce memory access latency |
US20040243768A1 (en) * | 2003-05-27 | 2004-12-02 | Dodd James M. | Method and apparatus to improve multi-CPU system performance for accesses to memory |
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US5822772A (en) | 1996-03-22 | 1998-10-13 | Industrial Technology Research Institute | Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties |
JPH11165454A (en) * | 1997-12-04 | 1999-06-22 | Canon Inc | Image processing device and image processing system |
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JP2002049580A (en) * | 2000-08-02 | 2002-02-15 | Mitsubishi Electric Corp | Bus managing device, bus use request transmitter, method of bus managing, and bus use request transmission method |
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-
2005
- 2005-12-09 US US11/297,856 patent/US7426621B2/en active Active
-
2006
- 2006-12-06 TW TW095145295A patent/TW200728983A/en unknown
- 2006-12-08 GB GB0811767A patent/GB2446997B/en not_active Expired - Fee Related
- 2006-12-08 JP JP2008544532A patent/JP2009518753A/en active Pending
- 2006-12-08 DE DE112006003358.1T patent/DE112006003358B4/en active Active
- 2006-12-08 KR KR1020087016731A patent/KR20080075910A/en not_active Application Discontinuation
- 2006-12-08 CN CN2006800462409A patent/CN101326504B/en active Active
- 2006-12-08 WO PCT/US2006/046877 patent/WO2007067739A1/en active Application Filing
Patent Citations (6)
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US6145065A (en) * | 1997-05-02 | 2000-11-07 | Matsushita Electric Industrial Co., Ltd. | Memory access buffer and reordering apparatus using priorities |
US6088772A (en) * | 1997-06-13 | 2000-07-11 | Intel Corporation | Method and apparatus for improving system performance when reordering commands |
EP0901080A1 (en) * | 1997-09-08 | 1999-03-10 | STMicroelectronics Ltd. | Arbitration system |
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Publication number | Priority date | Publication date | Assignee | Title |
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WO2018013157A1 (en) * | 2016-07-15 | 2018-01-18 | Advanced Micro Devices, Inc. | Command arbitration for high speed memory interfaces |
US10684969B2 (en) | 2016-07-15 | 2020-06-16 | Advanced Micro Devices, Inc. | Command arbitration for high speed memory interfaces |
Also Published As
Publication number | Publication date |
---|---|
JP2009518753A (en) | 2009-05-07 |
US20070136545A1 (en) | 2007-06-14 |
CN101326504B (en) | 2012-04-25 |
US7426621B2 (en) | 2008-09-16 |
GB2446997B (en) | 2010-11-10 |
DE112006003358B4 (en) | 2022-08-04 |
GB2446997A (en) | 2008-08-27 |
GB0811767D0 (en) | 2008-07-30 |
DE112006003358T5 (en) | 2008-10-02 |
TW200728983A (en) | 2007-08-01 |
CN101326504A (en) | 2008-12-17 |
KR20080075910A (en) | 2008-08-19 |
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