WO2007067982A3 - Flip chip mlp with conductive ink - Google Patents

Flip chip mlp with conductive ink Download PDF

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Publication number
WO2007067982A3
WO2007067982A3 PCT/US2006/061799 US2006061799W WO2007067982A3 WO 2007067982 A3 WO2007067982 A3 WO 2007067982A3 US 2006061799 W US2006061799 W US 2006061799W WO 2007067982 A3 WO2007067982 A3 WO 2007067982A3
Authority
WO
WIPO (PCT)
Prior art keywords
mlp
flip chip
electrical paths
conductive ink
printed
Prior art date
Application number
PCT/US2006/061799
Other languages
French (fr)
Other versions
WO2007067982A2 (en
Inventor
Seung-Young Choi
Ti-Ching Shian
Maria Cristina B Estacio
Original Assignee
Fairchild Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/364,014 external-priority patent/US7638861B2/en
Application filed by Fairchild Semiconductor filed Critical Fairchild Semiconductor
Priority to KR1020087013404A priority Critical patent/KR101135828B1/en
Priority to CN2006800459980A priority patent/CN101385134B/en
Priority to KR1020117029367A priority patent/KR101363463B1/en
Publication of WO2007067982A2 publication Critical patent/WO2007067982A2/en
Publication of WO2007067982A3 publication Critical patent/WO2007067982A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped Ieadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the ieads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.
PCT/US2006/061799 2005-12-08 2006-12-08 Flip chip mlp with conductive ink WO2007067982A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020087013404A KR101135828B1 (en) 2005-12-08 2006-12-08 Flip chip mlp with conductive ink
CN2006800459980A CN101385134B (en) 2005-12-08 2006-12-08 Flip chip MLP with conductive ink
KR1020117029367A KR101363463B1 (en) 2005-12-08 2006-12-08 Flip chip mlp with conductive ink

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US74843505P 2005-12-08 2005-12-08
US60/748,435 2005-12-08
US11/364,014 2006-02-28
US11/364,014 US7638861B2 (en) 2005-12-08 2006-02-28 Flip chip MLP with conductive ink

Publications (2)

Publication Number Publication Date
WO2007067982A2 WO2007067982A2 (en) 2007-06-14
WO2007067982A3 true WO2007067982A3 (en) 2008-07-24

Family

ID=38123652

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/061799 WO2007067982A2 (en) 2005-12-08 2006-12-08 Flip chip mlp with conductive ink

Country Status (3)

Country Link
KR (2) KR101135828B1 (en)
CN (1) CN101385134B (en)
WO (1) WO2007067982A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700055987A1 (en) 2017-05-23 2018-11-23 St Microelectronics Srl PROCEDURE FOR MANUFACTURING SEMICONDUCTOR AND CORRESPONDING PRODUCT DEVICES

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172213A (en) * 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5641996A (en) * 1995-01-30 1997-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package
US6492737B1 (en) * 2000-08-31 2002-12-10 Hitachi, Ltd. Electronic device and a method of manufacturing the same
US20020184754A1 (en) * 1999-08-17 2002-12-12 Jicheng Yang Coupling spaced bond pads to a contact
US6624006B2 (en) * 1999-06-18 2003-09-23 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip
US6630372B2 (en) * 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US6661084B1 (en) * 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0155843B1 (en) * 1995-07-07 1998-12-01 이대원 A semiconductor equipment
TWI317991B (en) 2003-12-19 2009-12-01 Advanced Semiconductor Eng Semiconductor package with flip chip on leadframe

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172213A (en) * 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
US5641996A (en) * 1995-01-30 1997-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6630372B2 (en) * 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6624006B2 (en) * 1999-06-18 2003-09-23 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip
US20020184754A1 (en) * 1999-08-17 2002-12-12 Jicheng Yang Coupling spaced bond pads to a contact
US6661084B1 (en) * 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
US6492737B1 (en) * 2000-08-31 2002-12-10 Hitachi, Ltd. Electronic device and a method of manufacturing the same
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package

Also Published As

Publication number Publication date
CN101385134A (en) 2009-03-11
WO2007067982A2 (en) 2007-06-14
KR101135828B1 (en) 2012-04-16
CN101385134B (en) 2011-04-06
KR20080075142A (en) 2008-08-14
KR20110137405A (en) 2011-12-22
KR101363463B1 (en) 2014-02-14

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