WO2007074351A1 - Substrate with contact studs of improved quality - Google Patents

Substrate with contact studs of improved quality Download PDF

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Publication number
WO2007074351A1
WO2007074351A1 PCT/IB2005/003905 IB2005003905W WO2007074351A1 WO 2007074351 A1 WO2007074351 A1 WO 2007074351A1 IB 2005003905 W IB2005003905 W IB 2005003905W WO 2007074351 A1 WO2007074351 A1 WO 2007074351A1
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WO
WIPO (PCT)
Prior art keywords
contact
stud
contact structure
coating
base material
Prior art date
Application number
PCT/IB2005/003905
Other languages
French (fr)
Inventor
Teng Chuan Tee
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to PCT/IB2005/003905 priority Critical patent/WO2007074351A1/en
Publication of WO2007074351A1 publication Critical patent/WO2007074351A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to a substrate with contact studs for a semiconductor chip.
  • a known concern in the electronic industry is the failure of a good semiconductor chip of the flip chip type after mounting onto a substrate.
  • US 6 930 032 addresses an intermetallic connection between a contact bump and a contact region of the substrate.
  • the object of the invention is to provide a substrate with contact studs of an improved quality and an electronic component with a substrate that has a high reliability.
  • the invention provides a base material comprising a plurality of contact areas on the top surface of a base material.
  • a contact stud is located on top of each contact area.
  • One or more layers of material cover the surface of each contact stud.
  • a layer of solder resist with openings for the contact pads covers the top surface of the base material.
  • Both the contact stud and the contact area comprise the same material to avoid corrosion arising from intermetallics formation at the joint between the contact stud and the contact area.
  • the contact studs may be cylindrical in shape or partly spherical in shape. Molten solder is provided at the contact stud when the contact stud is connecting to an external contact region such as the contact pad of a semiconductor chip.
  • the spherical shape of the contact stud facilitates the gathering of molten solder around the connecting area between the contact stud and the external contact region.
  • One or more layers of material cover the contact studs .
  • the coating material enhances the quality of the contact stud by resisting the formation of oxide on the contact stud, improving the solderability of the contact stud, and preventing the formation of intermetallics between the contact stud and the material surrounding the contact stud, such as solder.
  • One application of this invention is to coat a copper contact stud with a layer of solder. Solder enhances solderability of the contact stud and prevents the contact stud from forming an oxide layer.
  • Another application of this invention is to coat the copper contact stud with a layer of nickel and a layer of gold enclosing the layer of nickel.
  • the inner coat of nickel material prevents the copper contact stud from interacting with solder.
  • the solder is applied to the contact stud when the contact stud is connected to an external contact region.
  • An electronic component according to the invention comprises a substrate and one or more semiconductor chips.
  • the substrate comprises a base material.
  • the top surface of the base material includes a plurality of contact areas.
  • On top of each contact area is formed a contact stud.
  • the contact stud has according the invention one or more layers of coating material.
  • the semiconductor chip comprises contact pads on one surface of the semiconductor chip.
  • the semiconductor chip is placed on the substrate with the contact pads facing downwards.
  • the contact pads of the semiconductor chip are connected to the contact studs of the substrate.
  • the coating layer of the contact stud improves the quality of the contact stud.
  • the coating layer enhances the contact stud by resisting oxidation of the contact stud, improves sol- derability of the contact stud, and resists interaction between the contact stud and the material surrounding the contact stud, such as solder.
  • These enhancing features of the coating material enable the contact stud to form a high quality joint between the contact stud and the contact pads of the semiconductor chip. This is of particular importance when the electronic component experiences extreme temperature. Then, the contact stud undergoes stress and fatigue due to different rate of thermal expansion between the semiconductor chip and the substrate. This may happen during electronic component testing and end-user application when heat is applied to the component.
  • the base material is provided with contact pads using a deposition method.
  • a contact pad of the same material as the contact stud is next formed on the contact stud.
  • a layer of solder resist is grown on the top surface of the base material around the contact stud.
  • one or more layers of material are deposited on the surface of the contact studs .
  • One method for growing the coating material on the contact stud is electroplating where a layer of metal is deposited by passing of electrical current through a conductive medium.
  • Electroless plating is another deposition method where there is no application of electrical current. This process uses chemical reaction to deposit material onto the contact stud.
  • Chemical vapour deposition is another method of deposition. It uses glow discharge to produce a non-equilibrium and reactive plasma by decomposing a raw material gas.
  • Another deposition method is physical vapour deposition
  • PVD Physical Vapor Deposition
  • Figure 1 shows a cross section of a contact structure according to the invention
  • Figure 2 shows a further cross section of a contact structure according to the invention
  • Figure 3 shows a further cross section of a contact structure according to the invention
  • Figure 4 shows a cross section of an electronic component according to the invention.
  • Figure 1 shows a cross section of a contact structure 14 that includes a base material 6 that has good insulation and low dielectric property. On the top surface 8 of the base material 6, a plurality of contact terminals 1 are provided. On top of each contact terminal 1 is located a contact stud 3. Each contact stud 3 is covered with a layer of coating material 5. A layer of solder resist 4 covers the top surface of the base material 8 and leaves openings for the contact terminals 1.
  • the contact studs 3 and the contact terminals 1 comprise copper material.
  • the use of the same material for the contact stud 3 and the contact terminal 1 avoids corrosion arising from the formation of intermetallics at the joint between the contact stud 3 and the contact terminal 1.
  • the contact stud 3 is of cylindrical shape with a height h of about 50 microme- ters and a width d of about 40 micrometers.
  • the coating material 5 comprises, among other materials, tin and has a thickness of about 2 micrometers.
  • the contact stud 3 and the coating material 5 are formed using a combination of sputtering and electroplating processes.
  • FIG 2 shows a further cross section of a contact structure 14' that is similar with the contact structure 14 disclosed in figure 1. Similar components have the same reference number with a prime symbol.
  • the contact structure 14' has a contact stud 3 ' of a partly spherical shape of 40 micrometers diameter.
  • the contact stud 3' provides an electrical connection between the contact structure 14' and an external component such a semiconductor chip, which is not shown in the figure.
  • the spherical shape of the contact stud 3' facilitates wetting of the solder between the contact stud 3 ' and an external contact region of the external device.
  • Figure 3 displays a further cross section of a contact structure 15 that has the same structure as the contact structure 14 in figure 1 but with a different coating structure 12, 13. Similar features have the same reference number.
  • the contact stud 3 and the contact terminal 1 comprise copper material.
  • Two layers of coating material 12, 13 cover the contact stud 3.
  • the inner coating layer 12 comprises mainly nickel and it has a thickness of 1 micrometer.
  • the outer coating layer 13 comprises mainly gold and it has a thickness of 600 angstroms.
  • the gold material enhances solderability of the contact stud 3 and inhibits oxidation of the contact stud 3.
  • Solder is applied to the contact stud 3 when the contact stud is connecting with an external contact region.
  • the external contact region is not displayed in figure 3.
  • the layer of nickel acts to prevent copper and solder interdiffusion.
  • Figure 4 discloses a cross section of an electronic component
  • the lowest part of the electronic component 11 discloses a contact structure 16 similar to the contact structure 14 in figure 1. Similar components have the same reference number.
  • a semiconductor chip 10 placed with its active surface 17 facing downwards .
  • a plurality of contact pads 9 are provided on the active surface 17 of the semicon- ductor chip 10. Each contact pad 9 has a contact stud 3 attached to it.
  • the space between the semiconductor chip 10 and the base material 6 is filled with an encapsulating material 2.
  • solder resist 4 hinders solder from adhering to the top of the base material 8. Solder residue can result from the connection of the contact studs 3 to the contact pads 9 of the semiconductor chip.
  • the encapsulating material 2 provides a layer of protection for the semiconductor chip and binds the semiconductor chip 10 and the contact structure 16 together.
  • the contact structure 14 is placed with the contact stud 3 facing upward.
  • a layer of solder paste is deposited, by direct printing, on the top surface of the coating material 5.
  • Direct printing is a method where a piston-driven printing head deposits the solder paste directly onto the soldering area.
  • the contact pad 9 of the semiconductor chip 10 is then placed over the contact stud 3.
  • the entire assembly of contact structure 16 and semiconductor chip 10 is then subjected to a high temperature process called reflow. The high temperature causes the solder to melt and connects the contact pads 9 of the semiconductor chip to the coating material 5 of the conduct stud 3.

Abstract

A contact structure (14) comprises a base material (6). On the top surface of the base material (6) is provided with a plurality of contact areas (1) and on each contact area (1) is formed a contact stud (3) having the same material as the contact area (9). One or more layers of electrically conductive coating material (5) covers the contact stud (3).

Description

Description
Substrate with contact studs of improved quality
This invention relates to a substrate with contact studs for a semiconductor chip.
A known concern in the electronic industry is the failure of a good semiconductor chip of the flip chip type after mounting onto a substrate.
Current efforts, such as JP 2000-269269, address the electrical conductivity between bumps of the substrate and contact pads of a semiconductor chip.
US 6 930 032 addresses an intermetallic connection between a contact bump and a contact region of the substrate.
The object of the invention is to provide a substrate with contact studs of an improved quality and an electronic component with a substrate that has a high reliability.
The invention provides a base material comprising a plurality of contact areas on the top surface of a base material. A contact stud is located on top of each contact area. One or more layers of material cover the surface of each contact stud. A layer of solder resist with openings for the contact pads covers the top surface of the base material.
Both the contact stud and the contact area comprise the same material to avoid corrosion arising from intermetallics formation at the joint between the contact stud and the contact area.
The contact studs may be cylindrical in shape or partly spherical in shape. Molten solder is provided at the contact stud when the contact stud is connecting to an external contact region such as the contact pad of a semiconductor chip. The spherical shape of the contact stud facilitates the gathering of molten solder around the connecting area between the contact stud and the external contact region.
One or more layers of material cover the contact studs . The coating material enhances the quality of the contact stud by resisting the formation of oxide on the contact stud, improving the solderability of the contact stud, and preventing the formation of intermetallics between the contact stud and the material surrounding the contact stud, such as solder.
One application of this invention is to coat a copper contact stud with a layer of solder. Solder enhances solderability of the contact stud and prevents the contact stud from forming an oxide layer.
Another application of this invention is to coat the copper contact stud with a layer of nickel and a layer of gold enclosing the layer of nickel. The inner coat of nickel material prevents the copper contact stud from interacting with solder. The solder is applied to the contact stud when the contact stud is connected to an external contact region.
The outer coat of gold inhibits oxide formation on the contact stud and enhances solderability of the contact stud. An electronic component according to the invention comprises a substrate and one or more semiconductor chips. The substrate comprises a base material. The top surface of the base material includes a plurality of contact areas. On top of each contact area is formed a contact stud. The contact stud has according the invention one or more layers of coating material. The semiconductor chip comprises contact pads on one surface of the semiconductor chip. The semiconductor chip is placed on the substrate with the contact pads facing downwards. The contact pads of the semiconductor chip are connected to the contact studs of the substrate.
The coating layer of the contact stud improves the quality of the contact stud. The coating layer enhances the contact stud by resisting oxidation of the contact stud, improves sol- derability of the contact stud, and resists interaction between the contact stud and the material surrounding the contact stud, such as solder. These enhancing features of the coating material enable the contact stud to form a high quality joint between the contact stud and the contact pads of the semiconductor chip. This is of particular importance when the electronic component experiences extreme temperature. Then, the contact stud undergoes stress and fatigue due to different rate of thermal expansion between the semiconductor chip and the substrate. This may happen during electronic component testing and end-user application when heat is applied to the component.
For fabricating the contact structure according to the invention, the base material is provided with contact pads using a deposition method. A contact pad of the same material as the contact stud is next formed on the contact stud. After this, a layer of solder resist is grown on the top surface of the base material around the contact stud. Then one or more layers of material are deposited on the surface of the contact studs .
There are several methods for growing the coating material on the contact stud. One method is electroplating where a layer of metal is deposited by passing of electrical current through a conductive medium.
Electroless plating is another deposition method where there is no application of electrical current. This process uses chemical reaction to deposit material onto the contact stud.
Chemical vapour deposition is another method of deposition. It uses glow discharge to produce a non-equilibrium and reactive plasma by decomposing a raw material gas.
Another deposition method is physical vapour deposition
(PVD) . PVD involves a deposition of a thin film by physical means. One form of PVD is sputtering.
Figure 1 shows a cross section of a contact structure according to the invention,
Figure 2 shows a further cross section of a contact structure according to the invention,
Figure 3 shows a further cross section of a contact structure according to the invention, Figure 4 shows a cross section of an electronic component according to the invention.
Figure 1 shows a cross section of a contact structure 14 that includes a base material 6 that has good insulation and low dielectric property. On the top surface 8 of the base material 6, a plurality of contact terminals 1 are provided. On top of each contact terminal 1 is located a contact stud 3. Each contact stud 3 is covered with a layer of coating material 5. A layer of solder resist 4 covers the top surface of the base material 8 and leaves openings for the contact terminals 1.
The contact studs 3 and the contact terminals 1 comprise copper material. The use of the same material for the contact stud 3 and the contact terminal 1 avoids corrosion arising from the formation of intermetallics at the joint between the contact stud 3 and the contact terminal 1. The contact stud 3 is of cylindrical shape with a height h of about 50 microme- ters and a width d of about 40 micrometers. The coating material 5 comprises, among other materials, tin and has a thickness of about 2 micrometers. The contact stud 3 and the coating material 5 are formed using a combination of sputtering and electroplating processes.
Figure 2 shows a further cross section of a contact structure 14' that is similar with the contact structure 14 disclosed in figure 1. Similar components have the same reference number with a prime symbol. The contact structure 14' has a contact stud 3 ' of a partly spherical shape of 40 micrometers diameter. The contact stud 3' provides an electrical connection between the contact structure 14' and an external component such a semiconductor chip, which is not shown in the figure. The spherical shape of the contact stud 3' facilitates wetting of the solder between the contact stud 3 ' and an external contact region of the external device.
Figure 3 displays a further cross section of a contact structure 15 that has the same structure as the contact structure 14 in figure 1 but with a different coating structure 12, 13. Similar features have the same reference number. The contact stud 3 and the contact terminal 1 comprise copper material. Two layers of coating material 12, 13 cover the contact stud 3. The inner coating layer 12 comprises mainly nickel and it has a thickness of 1 micrometer. The outer coating layer 13 comprises mainly gold and it has a thickness of 600 angstroms. The gold material enhances solderability of the contact stud 3 and inhibits oxidation of the contact stud 3. Solder is applied to the contact stud 3 when the contact stud is connecting with an external contact region. The external contact region is not displayed in figure 3. The layer of nickel acts to prevent copper and solder interdiffusion. There is a plurality of contact studs 3 with this coating structure 12, 13 on the top surface of the base material 8, which is not shown here.
Figure 4 discloses a cross section of an electronic component
11 according to the invention. The lowest part of the electronic component 11 discloses a contact structure 16 similar to the contact structure 14 in figure 1. Similar components have the same reference number. Above the contact structure 16 is a semiconductor chip 10 placed with its active surface 17 facing downwards . A plurality of contact pads 9 are provided on the active surface 17 of the semicon- ductor chip 10. Each contact pad 9 has a contact stud 3 attached to it. The space between the semiconductor chip 10 and the base material 6 is filled with an encapsulating material 2.
The solder resist 4 hinders solder from adhering to the top of the base material 8. Solder residue can result from the connection of the contact studs 3 to the contact pads 9 of the semiconductor chip. The encapsulating material 2 provides a layer of protection for the semiconductor chip and binds the semiconductor chip 10 and the contact structure 16 together.
To provide the electronic component 11 in figure 4, the contact structure 14 is placed with the contact stud 3 facing upward. A layer of solder paste is deposited, by direct printing, on the top surface of the coating material 5. Direct printing is a method where a piston-driven printing head deposits the solder paste directly onto the soldering area. The contact pad 9 of the semiconductor chip 10 is then placed over the contact stud 3. The entire assembly of contact structure 16 and semiconductor chip 10 is then subjected to a high temperature process called reflow. The high temperature causes the solder to melt and connects the contact pads 9 of the semiconductor chip to the coating material 5 of the conduct stud 3. Reference numbers
1, 1' contact terminal
2 encapsulating material
3, 3 ' contact stud.
4, 4' solder resist
5, 51 coating material
6, 6' base material
7, 7 ' rear surface of base material 8 8,, 8 8'1 top surface of base material
9 contact pad
10 semiconductor chip
11 electronic component
12 inner coating material 1 133 outer coating material
14, 14 15 contact structure
17 active surface of semiconductor chip

Claims

Patent claims
1. A contact structure (14; 14'; 15) comprising of the following features : - a base material (6; 6') comprising a plurality of contact areas (1; 1') on the top surface (8; 8') of the base material (6; 6'), a plurality of contact studs (3; 3') comprising the same material as the contact area (9; 9') and being located at the contact area (9; 9'), one or more layers of electrically conductive coating material (5; 5') covering the contact stud (3; 3') •
2. A contact structure (14; 14'; 15) according to the previous claim, characterized in that at least one of the coating layers (5, 5', 12, 13) (inhibits oxide formation) comprises noble material such as gold.
3. A contact structure (14; 14'; 15) according to previous claims , characterized in that at least one of the coating layers (5, 5', 12, 13) in a molten state enhances solder adhesion.
4. A contact structure (14; 14'; 15) according to claim 3, characterized in that the coating layer (5, 5', 12, 13) comprises solder.
5. A contact structure (14; 14'; 15) according to claim 4, characterized in that the contact stud (3; 3') comprises copper material and that the coating material (5, 5') comprises tin and/or lead.
6. A contact structure (14; 14'; 15) according to one of claims 1 to 5, characterised in that the contact stud (3; 3') comprises copper material, an inner coating layer (12) comprises nickel material and an outer coating layer (13) comprises gold material.
7. An electronic component (11) comprising: a contact structure (14; 14'; 15) according to one of the previous claims, one or more semiconductor chips (10) comprising contact regions (9) on its active surface, the contact regions (9) being connected to the contact studs (3; 3') of the contact structure (14; 14' ; 15) .
8. A method for fabricating a contact structure (14; 14'; 15), the method comprising the following steps: providing an base material (6, 6') with a plurality of contact areas (1, 1') on its top surface (8, 8'), forming the contact stud (3, 3') on each contact area (1, I1) of the base material (6, 6'), coating the contact stud (3, 3') with one or more layers of conductive material (5, 5') .
9. A method for fabricating a contact structure according to claim 1, characterised in that the step of providing an coating layer of material on the contact stud comprises one or more of the following steps : electroplating, electroless plating, chemical vapour deposition, physical vapour deposition.
PCT/IB2005/003905 2005-12-29 2005-12-29 Substrate with contact studs of improved quality WO2007074351A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
PCT/IB2005/003905 WO2007074351A1 (en) 2005-12-29 2005-12-29 Substrate with contact studs of improved quality

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Publication Number Publication Date
WO2007074351A1 true WO2007074351A1 (en) 2007-07-05

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0168287A1 (en) * 1984-06-08 1986-01-15 AEROSPATIALE Société Nationale Industrielle Process for making printed circuits, and printed circuit obtained by this method
JPH05226502A (en) * 1992-02-13 1993-09-03 Casio Comput Co Ltd Wiring board and connection structure thereof
US6223429B1 (en) * 1995-06-13 2001-05-01 Hitachi Chemical Company, Ltd. Method of production of semiconductor device
US6390356B1 (en) * 2000-06-15 2002-05-21 Orient Semiconductor Electronics Limited Method of forming cylindrical bumps on a substrate for integrated circuits
US20040046264A1 (en) * 2002-09-09 2004-03-11 Ho Kwun Yao High density integrated circuit packages and method for the same
US20040102028A1 (en) * 2002-11-25 2004-05-27 Han-Kun Hsieh Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US20040157450A1 (en) * 2001-12-21 2004-08-12 Bojkov Christo P. Waferlevel method for direct bumping on copper pads in integrated circuits
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20050221635A1 (en) * 2004-03-30 2005-10-06 International Business Machines Corporation Micro-bumps to enhance lga interconnections

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0168287A1 (en) * 1984-06-08 1986-01-15 AEROSPATIALE Société Nationale Industrielle Process for making printed circuits, and printed circuit obtained by this method
JPH05226502A (en) * 1992-02-13 1993-09-03 Casio Comput Co Ltd Wiring board and connection structure thereof
US6223429B1 (en) * 1995-06-13 2001-05-01 Hitachi Chemical Company, Ltd. Method of production of semiconductor device
US6390356B1 (en) * 2000-06-15 2002-05-21 Orient Semiconductor Electronics Limited Method of forming cylindrical bumps on a substrate for integrated circuits
US20040157450A1 (en) * 2001-12-21 2004-08-12 Bojkov Christo P. Waferlevel method for direct bumping on copper pads in integrated circuits
US20040046264A1 (en) * 2002-09-09 2004-03-11 Ho Kwun Yao High density integrated circuit packages and method for the same
US20040102028A1 (en) * 2002-11-25 2004-05-27 Han-Kun Hsieh Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20050221635A1 (en) * 2004-03-30 2005-10-06 International Business Machines Corporation Micro-bumps to enhance lga interconnections

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