WO2007078521A3 - Clock-free activation circuit - Google Patents

Clock-free activation circuit Download PDF

Info

Publication number
WO2007078521A3
WO2007078521A3 PCT/US2006/046341 US2006046341W WO2007078521A3 WO 2007078521 A3 WO2007078521 A3 WO 2007078521A3 US 2006046341 W US2006046341 W US 2006046341W WO 2007078521 A3 WO2007078521 A3 WO 2007078521A3
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
signal
voltage
node
reference voltage
Prior art date
Application number
PCT/US2006/046341
Other languages
French (fr)
Other versions
WO2007078521A2 (en
Inventor
Jyn-Bang Shyu
Robert Olah
Rohit Mittal
Original Assignee
Intelleflex Corp
Jyn-Bang Shyu
Robert Olah
Rohit Mittal
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intelleflex Corp, Jyn-Bang Shyu, Robert Olah, Rohit Mittal filed Critical Intelleflex Corp
Priority to JP2008545640A priority Critical patent/JP5355092B2/en
Priority to EP06838981A priority patent/EP1961129A4/en
Publication of WO2007078521A2 publication Critical patent/WO2007078521A2/en
Publication of WO2007078521A3 publication Critical patent/WO2007078521A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.
PCT/US2006/046341 2005-12-15 2006-12-04 Clock-free activation circuit WO2007078521A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008545640A JP5355092B2 (en) 2005-12-15 2006-12-04 Clock-free start-up circuit
EP06838981A EP1961129A4 (en) 2005-12-15 2006-12-04 Clock-free activation circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/305,648 US8548098B2 (en) 2005-12-15 2005-12-15 Clock-free activation circuit
US11/305,648 2005-12-15

Publications (2)

Publication Number Publication Date
WO2007078521A2 WO2007078521A2 (en) 2007-07-12
WO2007078521A3 true WO2007078521A3 (en) 2007-12-13

Family

ID=38174283

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/046341 WO2007078521A2 (en) 2005-12-15 2006-12-04 Clock-free activation circuit

Country Status (5)

Country Link
US (1) US8548098B2 (en)
EP (1) EP1961129A4 (en)
JP (1) JP5355092B2 (en)
CN (1) CN101361285A (en)
WO (1) WO2007078521A2 (en)

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US9608742B2 (en) * 2012-06-18 2017-03-28 Alstom Transport Technologies Methods and systems for signal fingerprinting
CN102801517B (en) * 2012-08-31 2014-12-03 华为技术有限公司 CDR (Clock Data Recovery) circuit and terminal
WO2015163886A1 (en) * 2014-04-24 2015-10-29 Empire Technology Development, Llc Broadcasting a message using modulated power
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DE102016216066A1 (en) * 2016-08-26 2018-03-01 Robert Bosch Gmbh Subscriber for a digital communication system and associated communication system
DE102018200931A1 (en) * 2018-01-22 2019-07-25 Robert Bosch Gmbh Method for activating a computing unit by means of a circuit arrangement in response to an activation signal

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Also Published As

Publication number Publication date
JP2009520400A (en) 2009-05-21
US8548098B2 (en) 2013-10-01
JP5355092B2 (en) 2013-11-27
CN101361285A (en) 2009-02-04
EP1961129A4 (en) 2012-04-04
US20070141983A1 (en) 2007-06-21
EP1961129A2 (en) 2008-08-27
WO2007078521A2 (en) 2007-07-12

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