WO2007078672A2 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction - Google Patents
Performing a cyclic redundancy checksum operation responsive to a user-level instruction Download PDFInfo
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- WO2007078672A2 WO2007078672A2 PCT/US2006/047234 US2006047234W WO2007078672A2 WO 2007078672 A2 WO2007078672 A2 WO 2007078672A2 US 2006047234 W US2006047234 W US 2006047234W WO 2007078672 A2 WO2007078672 A2 WO 2007078672A2
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Classifications
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
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- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/093—CRC update after modification of the information word
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/095—Error detection codes other than CRC and single parity bit codes
- H03M13/096—Checksums
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/157—Polynomial evaluation, i.e. determination of a polynomial sum at a given value
Definitions
- Embodiments of the present invention relate to data processing, and more particularly to determining checksums such as cyclic redundancy checks (CRCs).
- CRCs cyclic redundancy checks
- a data packet will be transmitted with a checksum attached.
- a CRC sum can be generated by a transmitting source and appended to data to be transmitted.
- This checksum which may be calculated according to one of many different algorithms, can then be compared to a similar checksum generated at the receiving end from the received data. If the two checksums are identical, the transmitted data is correct. If however the generated checksum varies from the transmitted checksum, an error is indicated.
- checksums are used throughout networking technologies to detect transmission errors.
- CRC calculations can be performed in either hardware or software.
- a dedicated hardware engine is provided within a system to perform the CRC calculation.
- data to be subjected to such a CRC calculation is sent to the hardware engine for calculation of the CRC, which is then appended to the data, e.g., for transmission from the system.
- Various drawbacks exist to using such an offload engine including the overhead of sending data to the engine.
- CRC calculations are often performed in software.
- To implement CRC calculations in software typically lookup table schemes are used.
- Such software calculations of CRC values are notoriously slow, compute-intensive operations.
- the memory footprint of the lookup table can be large, impacting performance. Accordingly, these slow calculations can degrade network performance, and further consume processing resources. As an example, it can take between 5 and 15 cycles to perform a CRC calculation per byte of data. As a result, software CRC performance is too low for general use in high-speed networks.
- FIG. 1 is a flow diagram of a method in accordance with one embodiment of the present invention..
- FIG. 2 is a block diagram of a processor in accordance with one embodiment of the present invention.
- FIG. 3 is a block diagram of a portion of a processor to perform a checksum operation in accordance with an embodiment of the present invention.
- FIG. 4 is a block diagram of another portion of a processor in accordance with an embodiment of the present invention.
- FIG. 5 is a block diagram of a system in accordance with an embodiment of the present invention.
- checksum operations may be effected using an instruction set architecture (ISA) extension to compute checksum values.
- ISA instruction set architecture
- a user-level instruction may be provided within an ISA to enable a programmer to directly perform a desired checksum operation such as a CRC operation in a general-purpose processor (e.g., a central processor unit (CPU)) via the instruction.
- the CRC operation may be a 32-bit CRC operation (i.e., a CRC32 operation generating a 32-bit running reminder, discussed further, below), and in different embodiments may, for example, correspond to the CRC used in an Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet protocol (published 2002) or other protocols.
- IEEE Institute of Electrical and Electronics Engineers
- various opcode instructions may be provided to perform CRC computations on different groupings of data.
- CRC computations may be supported on groups of 8, 16, 32 and 64 bits using different opcodes, although the scope of the present invention is not so limited.
- CRC calculations may be rapidly performed in hardware without the need for lookup tables or the like.
- the computations may be performed using generic, architecturally visible processor registers via integer operations performed according to the different opcodes.
- CRCs may be computed in a processor without the need for the overhead and complexity of offload hardware, such as network offload hardware.
- Method 100 may be used to obtain a checksum using a user-level instruction implemented on processor hardware, e.g., an execution unit of a CPU.
- method 100 may begin by performing a series of exclusive-OR (XOR) operations on data in source and destination registers (block 110).
- XOR exclusive-OR
- the data in the source register may correspond, e.g., to data present in a processor pipeline that has been received by the processor or is to be transmitted therefrom.
- a group of data in a buffer corresponding to a desired group size may be provided to the source register, which may be a general-purpose register of the processor.
- the source data may be obtained from a memory, in some embodiments.
- the destination register may correspond to a storage location for a running remainder obtained from the XOR operations.
- the destination register also may be a general-purpose register of the processor.
- the XOR operations may be performed in dedicated hardware within a processor pipeline.
- an execution unit of a processor e.g., an integer execution unit may be extended with circuitry to implement a series of XOR operations.
- this circuitry may correspond to a XOR tree to handle polynomial division by a desired polynomial.
- a polynomial for use in the XOR operations may be hard-wired into the logic gates of the XOR tree.
- the XOR tree may be configured to implement desired pre-processing and post-processing via the XOR operations, e.g., bit reflections and the like.
- the XOR tree logic may include multiple partitions, each configured to handle operations on different data sizes.
- a result which may correspond to a running remainder obtained from the XOR operations, may be stored in the destination register (block 120).
- the destination register may, upon initialization of a system, be set to a predetermined value, e.g., all ones, all zeros or another such value. Then during execution of checksum operations, this running remainder is continually updated with the result of the current checksum operation. More specifically, the remainder of the polynomial division implemented by the current checksum operation may be stored in the destination register.
- a buffer may include data that has been received by a system and is to have a checksum verified. The data may be fed in chunks into the source register to effect the checksum operation. Accordingly, it may be determined in diamond 130 if additional source data is present in this buffer. If so, the next data chunk may be provided to the source register, and control passes back to block 110, discussed above.
- the result of the checksum operation may be provided as the current value (e.g., running remainder) that is stored in the destination register (block 140).
- this checksum value may be used in many different manners. For example, in the case of received data, the computed checksum may be compared to a received checksum to confirm that the data was accurately received. In a transmission situation, the checksum may be appended to data to be transmitted so that the data may be verified on a receiving end. Of course other uses of checksums, such as for hash functions or generation of numbers pursuant to a pseudo random numbering scheme may also occur.
- a processor to implement checksum operations in accordance with an embodiment of the present invention may take many different forms depending on a desired architecture.
- FIG. 2 shown is a block diagram of a processor in accordance with one embodiment of the present invention.
- processor 200 includes a data path 205.
- Data path 205 may be controlled by front end control stages that may include a register alias table (RAT) 270, which may receive decoded instructions from a front end of the processor (not shown in FIG. 2).
- RAT 270 may be used to receive microoperations ( ⁇ ops) from the front end and rename the ⁇ ops for the resources of the data path.
- ⁇ ops microoperations
- ROB 250 may act as a register file to store ⁇ ops and corresponding source operands until the ⁇ op is ready for passing to a reservation station (RS) 230.
- RS reservation station
- ROB 250 may also store corresponding results of ⁇ ops that have already executed. These results may be held in ROB 250 until the ⁇ ops are retired (at which point the ROB entry is freed).
- Reservation station 230 may be used to store ⁇ ops until their corresponding source operands are present and/or until the ⁇ op is ready for execution in one of a plurality of execution units of data path 205.
- Reservation station 230 may include a plurality of dispatch ports to couple instructions and data to selected ones of execution units of data path 205. In some embodiments, multiple dispatch ports may be used in each cycle.
- the execution units in data path 205 include an address generation unit (AGU) 220, an integer (INT) execution unit 222, a store data (STD) unit 224, a floating point (FP) execution unit 226, and a single instruction multiple data (SIMD) execution unit 228.
- AGU address generation unit
- INT integer
- STD store data
- FP floating point
- SIMD single instruction multiple data
- integer execution unit 222 further includes logic 221.
- Logic 221 may include one or more hardware engines to perform checksum operations in accordance with an embodiment of the present invention. More specifically, logic 221 may include a plurality of exclusive-OR (XOR) logic trees to implement polynomial arithmetic and related data manipulations. In various embodiments, logic 221 may include different hardware engines to implement CRC operations on differently sized data chunks.
- XOR exclusive-OR
- a plurality of user- level instructions of an ISA each may define a CRC operation for a particular data size.
- Logic 221 may include a corresponding number of separate hardware engines, also referred to herein as XOR trees, to effect these different CRC operations.
- execution units may be present in different embodiments. After execution of a ⁇ op in one of the execution units, result data may be passed back to RS 230 and ROB 250 for storage, e.g., until retirement. Thus in one embodiment, both source and data registers for performing a CRC operation may be located in RS 230 or ROB 250. While not shown in FIG. 2, it is to be understood that additional buffers such as a memory order buffer (MOB) and other resources may be present within processor 200.
- MOB memory order buffer
- a write back stage may be coupled to the execution units to receive result data for later delivery to a memory hierarchy.
- one or. more other buffers such as store buffers, load buffers and the like may be coupled to RS 230.
- one or more retirement buffers may be coupled to RS 230 for storage of ⁇ ops and associated result data until retirement of the associated instruction.
- FIG. 3 shown is a block diagram of a portion of a processor to perform a checksum operation in accordance with an embodiment of the present invention.
- processor 300 includes an XOR tree 310, a first register 320 and a second register 330, all of which may be part of a processor pipeline.
- XOR tree 310 may be configured differently in various embodiments.
- XOR tree 310 may be implemented using a plurality of 3- input XOR gates in a first level, outputs of which are coupled to similar XOR gates of a second level, and so forth. Ln such an embodiment, each level of the XOR tree may be a third as large as the previous level.
- other configurations are possible.
- processor 300 includes a buffer 340, which also may be within the processor pipeline (e.g., as a buffer, queue or the like). Alternately, buffer 340 may be a cache memory associated with processor 300. In the embodiment of FIG. 3, first register 320 may correspond to a source register, while second register 330 may correspond to a destination register. In various embodiments, these registers may be general-purpose registers within processor 300. Of course, processor 300 may include many other registers, logic, functional units and the like, and the portion shown in FIG. 3 is for ease of illustration.
- first register 320 is provided to XOR tree 310, along with a portion of second register 330.
- second register 330 is provided to XOR tree 310.
- This 4-byte portion may correspond to the running remainder of a CRC32 operation.
- XOR tree 310 may perform data manipulations via XOR operations to generate a result that includes a remainder portion.
- This remainder portion may be the running remainder that is stored back in second register 330, as shown in FIG. 3.
- CRC operations can be efficiently performed in minimal cycle time and using minimal processor resources.
- additional portions of first register 320 may be provided incrementally to XOR tree 310 along with the current contents of second register 330 (i.e., the 32-bit running remainder).
- XOR tree 310 eight iterations of XOR operations in XOR tree 310 may be performed, each using a single byte of data from first register 320, along with the current running remainder in second register 330. If additional data is present in buffer 340 to be validated via a checksum, the additional data may be loaded into first register 320 so that it may then be processed in XOR tree 310.
- FIG. 4 shown is a block diagram of another portion of a processor in accordance with an embodiment of the present invention.
- processor 300 includes a different XOR tree 410 (e.g., in addition to XOR tree 310 of FIG. 3) that is coupled to receive data from first register 320 and second register 330.
- buffer 340 is present and may be used to provide data for CRC computations.
- XOR tree 410 is configured to handle a 64-bit CRC accumulation.
- first register 320 i.e., bytes Bo-B 7
- XOR tree 410 for manipulation in XOR operations with data in second register 330.
- the result data is stored back in second register 330. While described with these particular implementations in FIGS. 3 and 4, it is to be understood that the scope of the present invention is not so limited, and in other embodiments different hardware configurations for performing CRC operations may be present.
- Table 1 shown is a listing of example instructions of an instruction set architecture (ISA) to support CRC operations in accordance with various embodiments of the present invention.
- ISA instruction set architecture
- each instruction which may be referenced by an opcode, is used to perform a CRC32 operation using a source register and a destination register.
- differs flavors are possible, with each instruction to perform the CRC operation on a given size of destination operand and source operand.
- this instruction is used to perform a CRC32 operation on an 8-bit source operand and a 32-bit destination operand.
- the second line of Table 1 is used to perform a CRC32 operation on a 16-bit source operand and a 32-bit destination operand.
- the third line of Table 1 shows an instruction to perform a CRC32 operation on a 32-bit source operand and a 32-bit destination operand.
- these user-level instructions may be used by a programmer, e.g., as intrinsics to implement a CRC operation in accordance with the flow diagram of FIG. 1, for example.
- a user-level CRC instruction may be implemented in the following manner. Starting with an initial value in a first operand (i.e., a destination operand), a CRC32 value for a second operand (i.e., a source operand) may be accumulated and the result stored back in the destination operand.
- the source operand can be a register or a memory location.
- the destination operand may be a 32 or 64-bit register. If the destination is a 64-bit register, then the 32-bit result may be stored in the least significant double word and 00OOO0OOH stored in the most significant double word of the register.
- the initial value supplied in the destination operand may be a double word integer stored in a 32-bit register, or the least significant double word of a 64-bit register.
- software retains the result of the previous CRC operation in the destination operand, and then executes the CRC operation again with new input data in the source operand. Accordingly, each instruction takes a running CRC value in the first operand and updates the CRC value based on the second operand. In this manner, a CRC can be generated over any desired amount of data by performing the operation in a loop, until all desired data is subjected to the CRC operation.
- data contained in the source operand is processed in reflected bit order. This means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and so on, for all the bits of the source operand.
- the result of the CRC operation can be stored in the destination register in reflected bit order. This means that the most significant bit of the resulting CRC (i.e., bit 31) is stored in the least significant bit of the destination register (bit 0), and so on, for all the bits of the CRC.
- Tables 2-6 below show example pseudocode representations of a hardware implementation for each of the user-level instructions of Table 1.
- the remainder of this polynomial division (i.e., the remainder from the polynomial division modulus 2) is stored back into the low order bits of the destination operand in a bit-reflected order (e.g., bits 0-31 of either a 32-bit or 64-bit register).
- a bit-reflected order e.g., bits 0-31 of either a 32-bit or 64-bit register.
- MSBs most significant bits
- Embodiments of the present invention may be used to enable processing of various storage protocols, for example, an Internet Small Computer System Interface (iSCSI) protocol at rates greater than 10 gigabits per second.
- iSCSI Internet Small Computer System Interface
- Embodiments of the present invention further allow the use of data present in a processor or closely coupled thereto, reducing the need for on-cache data.
- data in a processor buffer may be fed to an XOR tree to enable rapid, on-the-fly CRC calculations.
- FIG. 5 shown is a block diagram of a multiprocessor system in accordance with an embodiment of the present invention.
- the multiprocessor system is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450.
- each of processors 470 and 480 may be multicore processors, including first and second processor cores (i.e., processor cores 474a and 474b and processor cores 484a and 484b).
- first processor 470 and second processor 480 may include XOR tree logic within their execution units to execute user-level CRC instructions in accordance with an embodiment of the present invention.
- First processor 470 further includes a memory controller hub (MCH) 472 and point-to-point (P-P) interfaces 476 and 478.
- second processor 480 includes a MCH 482 and P-P interfaces 486 and 488.
- MCH's 472 and 482 couple the processors to respective memories, namely a memory 432 and a memory 434, which may be portions of main memory locally attached to the respective processors.
- First processor 470 and second processor 480 may be coupled to a chipset 490 via P-P interconnects 452 and 454, respectively.
- chipset 490 includes P-P interfaces 494 and 498.
- chipset 490 includes an interface 492 to couple chipset 490 with a high performance graphics engine 438.
- an Advanced Graphics Port (AGP) bus 439 may be used to couple graphics engine 438 to chipset 490.
- AGP bus 439 may conform to the Accelerated Graphics Port Interface Specification, Revision 2.0, published May 4, 1998, by Intel Corporation, Santa Clara, California. Alternately, a point-to-point interconnect 439 may couple these components.
- chipset 490 may be coupled to a first bus 416 via an interface 496.
- first bus 416 may be a Peripheral Component Interconnect (PCI) bus, as defined by the PCI Local Bus Specification, Production Version, Revision 2.1, dated June 1995 or a bus such as the PCI Express bus or another third generation input/output (I/O) interconnect bus, although the scope of the present invention is not so limited.
- PCI Peripheral Component Interconnect
- I/O input/output
- various I/O devices 414 may be coupled to first bus 416, along with a bus bridge 418 which couples first bus 416 to a second bus 420.
- second bus 420 may be a low pin count (LPC) bus.
- Various devices may be coupled to second bus 420 including, for example, a keyboard/mouse 422, communication devices 426 and a data storage unit 428 which may include code 430, in one embodiment.
- an audio I/O 424 may be coupled to second bus 420.
- a system may implement a multi-drop bus or another such architecture.
- Embodiments may be implemented in code and may be stored on a storage medium having stored thereon instructions which can be used to program a system to perform the instructions.
- the storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk readonly memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto- optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
- ROMs read-only memories
- RAMs random access memories
- DRAMs dynamic random access memories
- SRAMs static random access memories
- EPROMs erasable programmable read-only memories
- flash memories electrically eras
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JP2008547301A JP5269610B2 (en) | 2005-12-23 | 2006-12-07 | Perform cyclic redundancy check operations according to user level instructions |
DE112006003298.4T DE112006003298B4 (en) | 2005-12-23 | 2006-12-07 | 06/02/2008 Performing a cyclic redundancy checksum operation responsive to a user-level command |
CN2006800422420A CN101305349B (en) | 2005-12-23 | 2006-12-07 | Performing a cyclic redundancy checksum operation responsive to a user-level instruction |
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US11/316,772 US7958436B2 (en) | 2005-12-23 | 2005-12-23 | Performing a cyclic redundancy checksum operation responsive to a user-level instruction |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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