WO2007078672A3 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction - Google Patents

Performing a cyclic redundancy checksum operation responsive to a user-level instruction Download PDF

Info

Publication number
WO2007078672A3
WO2007078672A3 PCT/US2006/047234 US2006047234W WO2007078672A3 WO 2007078672 A3 WO2007078672 A3 WO 2007078672A3 US 2006047234 W US2006047234 W US 2006047234W WO 2007078672 A3 WO2007078672 A3 WO 2007078672A3
Authority
WO
WIPO (PCT)
Prior art keywords
user
level instruction
cyclic redundancy
checksum operation
operation responsive
Prior art date
Application number
PCT/US2006/047234
Other languages
French (fr)
Other versions
WO2007078672A2 (en
Inventor
Steven R King
Frank Berry
Michael E Kounavis
Original Assignee
Intel Corp
Steven R King
Frank Berry
Michael E Kounavis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Steven R King, Frank Berry, Michael E Kounavis filed Critical Intel Corp
Priority to JP2008547301A priority Critical patent/JP5269610B2/en
Priority to DE112006003298.4T priority patent/DE112006003298B4/en
Priority to CN2006800422420A priority patent/CN101305349B/en
Publication of WO2007078672A2 publication Critical patent/WO2007078672A2/en
Publication of WO2007078672A3 publication Critical patent/WO2007078672A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/093—CRC update after modification of the information word
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/157—Polynomial evaluation, i.e. determination of a polynomial sum at a given value

Abstract

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
PCT/US2006/047234 2005-12-23 2006-12-07 Performing a cyclic redundancy checksum operation responsive to a user-level instruction WO2007078672A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008547301A JP5269610B2 (en) 2005-12-23 2006-12-07 Perform cyclic redundancy check operations according to user level instructions
DE112006003298.4T DE112006003298B4 (en) 2005-12-23 2006-12-07 06/02/2008 Performing a cyclic redundancy checksum operation responsive to a user-level command
CN2006800422420A CN101305349B (en) 2005-12-23 2006-12-07 Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/316,772 US7958436B2 (en) 2005-12-23 2005-12-23 Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US11/316,772 2005-12-23

Publications (2)

Publication Number Publication Date
WO2007078672A2 WO2007078672A2 (en) 2007-07-12
WO2007078672A3 true WO2007078672A3 (en) 2007-09-13

Family

ID=38195339

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/047234 WO2007078672A2 (en) 2005-12-23 2006-12-07 Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Country Status (6)

Country Link
US (17) US7958436B2 (en)
JP (1) JP5269610B2 (en)
CN (2) CN102708022B (en)
DE (1) DE112006003298B4 (en)
TW (1) TWI360047B (en)
WO (1) WO2007078672A2 (en)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7958436B2 (en) 2005-12-23 2011-06-07 Intel Corporation Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US8229109B2 (en) * 2006-06-27 2012-07-24 Intel Corporation Modular reduction using folding
US7827471B2 (en) * 2006-10-12 2010-11-02 Intel Corporation Determining message residue using a set of polynomials
US7852851B2 (en) * 2006-11-10 2010-12-14 Broadcom Corporation Method and system for hash table based routing via a prefix transformation
US8689078B2 (en) 2007-07-13 2014-04-01 Intel Corporation Determining a message residue
US8042025B2 (en) * 2007-12-18 2011-10-18 Intel Corporation Determining a message residue
US7886214B2 (en) * 2007-12-18 2011-02-08 Intel Corporation Determining a message residue
GB2458665B (en) * 2008-03-26 2012-03-07 Advanced Risc Mach Ltd Polynomial data processing operation
CN101527615A (en) * 2009-04-07 2009-09-09 华为技术有限公司 Implementation method of cyclic redundancy check (CRC) codes and device
US8543888B2 (en) * 2009-06-09 2013-09-24 Microchip Technology Incorporated Programmable cyclic redundancy check CRC unit
US8117496B2 (en) * 2009-06-18 2012-02-14 International Business Machines Corporation Detecting and recovering from silent data errors in application cloning systems
US8464125B2 (en) * 2009-12-10 2013-06-11 Intel Corporation Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
US8683307B2 (en) * 2011-05-27 2014-03-25 International Business Machines Corporation Checksum calculation, prediction and validation
CN103795502B (en) * 2014-02-28 2017-04-12 杭州华三通信技术有限公司 Data frame check code generating method and device
CN103984530B (en) * 2014-05-15 2016-08-17 中国航天科技集团公司第九研究院第七七一研究所 A kind of pipeline organization improving store instruction execution efficiency and method
CN104133736A (en) * 2014-07-29 2014-11-05 江苏宏云技术有限公司 Method for designing vector CRC commands
US9829899B2 (en) 2014-11-10 2017-11-28 Duke Energy Corporation Apparatuses including utility meter, power electronics, and communications circuitry, and related methods of operation
US20160191678A1 (en) * 2014-12-27 2016-06-30 Jesse C. Brandeburg Technologies for data integrity of multi-network packet operations
US10797722B2 (en) * 2016-06-10 2020-10-06 The Boeing Company System and method for providing hardware based fast and secure expansion and compression functions
US10255132B2 (en) * 2016-06-22 2019-04-09 Advanced Micro Devices, Inc. System and method for protecting GPU memory instructions against faults
CN107145334B (en) * 2017-04-26 2020-10-09 龙芯中科技术有限公司 Constant acquisition method, device, processor and computer readable storage medium
CN107544863B (en) * 2017-06-26 2021-07-20 新华三技术有限公司 Data storage method and device
DE102017212181A1 (en) * 2017-07-17 2019-01-17 Robert Bosch Gmbh Method and apparatus for determining checksums, buffer memory and processor
EP3667965A4 (en) 2017-09-08 2020-10-14 Huawei Technologies Co., Ltd. Coding method and device
US10594439B2 (en) 2017-09-08 2020-03-17 Huawei Technologies Co., Ltd. Channel encoding method and apparatus in wireless communications to output a polar encoded bit sequence
CN107943611B (en) * 2017-11-08 2021-04-13 天津国芯科技有限公司 Control device for quickly generating CRC
CN108540137B (en) * 2018-03-02 2021-09-03 江西清华泰豪三波电机有限公司 Cyclic redundancy check code generation method and device
US11468037B2 (en) * 2019-03-06 2022-10-11 Semiconductor Components Industries, Llc Memory device and data verification method
US11809382B2 (en) 2019-04-01 2023-11-07 Nutanix, Inc. System and method for supporting versioned objects
US11226905B2 (en) 2019-04-01 2022-01-18 Nutanix, Inc. System and method for mapping objects to regions
US11029993B2 (en) 2019-04-04 2021-06-08 Nutanix, Inc. System and method for a distributed key-value store
CN111800223B (en) * 2019-08-15 2023-06-23 北京京东尚科信息技术有限公司 Method, device and system for generating sending message and processing receiving message
CN112445525A (en) * 2019-09-02 2021-03-05 中科寒武纪科技股份有限公司 Data processing method, related device and computer readable medium
US11704334B2 (en) 2019-12-06 2023-07-18 Nutanix, Inc. System and method for hyperconvergence at the datacenter
KR20210084871A (en) 2019-12-30 2021-07-08 삼성전자주식회사 Integrity check device for safety sensitive data and electronic device including the same
US11609777B2 (en) 2020-02-19 2023-03-21 Nutanix, Inc. System and method for multi-cluster storage
US11436229B2 (en) 2020-04-28 2022-09-06 Nutanix, Inc. System and method of updating temporary bucket based on object attribute relationships or metadata relationships
US11487787B2 (en) 2020-05-29 2022-11-01 Nutanix, Inc. System and method for near-synchronous replication for object store
US11900164B2 (en) 2020-11-24 2024-02-13 Nutanix, Inc. Intelligent query planning for metric gateway
US11822370B2 (en) 2020-11-26 2023-11-21 Nutanix, Inc. Concurrent multiprotocol access to an object storage system
US20220385488A1 (en) 2021-05-31 2022-12-01 Nutanix, Inc. System and method for reconciling consumption data
US11899572B2 (en) 2021-09-09 2024-02-13 Nutanix, Inc. Systems and methods for transparent swap-space virtualization
US11748019B2 (en) * 2021-10-26 2023-09-05 EMC IP Holding Company LLC Method to efficiently transfer support and system logs from air-gapped vault systems to replication data sources by re-utilizing the existing replication streams
US20230140404A1 (en) * 2021-11-02 2023-05-04 Paul Tsyganko System, method, and computer program product for cataloging data integrity
CN115150024B (en) * 2022-09-02 2022-11-18 无锡沐创集成电路设计有限公司 Data processing method, device, equipment and medium
CN116861493B (en) * 2023-08-31 2024-03-29 上海芯联芯智能科技有限公司 Verification code generation method, processor and electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701316A (en) * 1995-08-31 1997-12-23 Unisys Corporation Method for generating an internet protocol suite checksum in a single macro instruction
US6631488B1 (en) * 2000-06-30 2003-10-07 Agilent Technologies, Inc. Configurable error detection and correction engine that has a specialized instruction set tailored for error detection and correction tasks
US20040243729A1 (en) * 2000-09-19 2004-12-02 Bbnt Solutions Llc Network processor having cyclic redundancy check implemented in hardware

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2253428A5 (en) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US3891974A (en) * 1973-12-17 1975-06-24 Honeywell Inf Systems Data processing system having emulation capability for providing wait state simulation function
US4351024A (en) * 1975-04-21 1982-09-21 Honeywell Information Systems Inc. Switch system base mechanism
US4130867A (en) * 1975-06-19 1978-12-19 Honeywell Information Systems Inc. Database instruction apparatus for determining a database record type
US4413319A (en) * 1981-03-09 1983-11-01 Allen-Bradley Company Programmable controller for executing block transfer with remote I/O interface racks
US4438512A (en) * 1981-09-08 1984-03-20 International Business Machines Corporation Method and apparatus for verifying storage apparatus addressing
JPH0822448B2 (en) 1987-06-26 1996-03-06 石川島播磨重工業株式会社 Carousel reel device
JP2818415B2 (en) * 1988-05-18 1998-10-30 日本電気株式会社 Buffer storage device
JPH0679276B2 (en) * 1990-08-31 1994-10-05 インターナショナル・ビジネス・マシーンズ・コーポレイション Method for increasing throughput of same-dependent process, process generation circuit, cyclic redundancy code generator, and controller system
US5369641A (en) * 1991-11-12 1994-11-29 Storage Technology Corporation Method and apparatus for detecting and correcting errors in data on magnetic tape media
EP0609595B1 (en) 1993-02-05 1998-08-12 Hewlett-Packard Company Method and apparatus for verifying CRC codes by combination of partial CRC codes
US5715278A (en) * 1993-05-11 1998-02-03 Ericsson Inc. Standby power saving in mobile phones
US5645159A (en) * 1994-03-30 1997-07-08 Lauener Engineering, Ltd. Method and apparatus for continuously casting metal
JP2814918B2 (en) * 1994-07-07 1998-10-27 株式会社デンソー Microcomputer
US6237074B1 (en) * 1995-05-26 2001-05-22 National Semiconductor Corp. Tagged prefetch and instruction decoder for variable length instruction set and method of operation
US5663952A (en) * 1995-07-07 1997-09-02 Sun Microsystems, Inc. Checksum generation circuit and method
US7301541B2 (en) * 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US5946467A (en) * 1996-09-20 1999-08-31 Novell, Inc. Application-level, persistent packeting apparatus and method
US5844923A (en) 1996-10-24 1998-12-01 At&T Corp Fast framing of nude ATM by header error check
US5960012A (en) 1997-06-23 1999-09-28 Sun Microsystems, Inc. Checksum determination using parallel computations on multiple packed data elements
US5974574A (en) * 1997-09-30 1999-10-26 Tandem Computers Incorporated Method of comparing replicated databases using checksum information
US7185266B2 (en) * 2003-02-12 2007-02-27 Alacritech, Inc. Network interface device for error detection using partial CRCS of variable length message portions
US6029186A (en) * 1998-01-20 2000-02-22 3Com Corporation High speed calculation of cyclical redundancy check sums
US6012063A (en) * 1998-03-04 2000-01-04 Starfish Software, Inc. Block file system for minimal incremental data transfer between computing devices
US7932911B2 (en) * 1998-08-24 2011-04-26 Microunity Systems Engineering, Inc. Processor for executing switch and translate instructions requiring wide operands
JP2000124811A (en) * 1998-10-12 2000-04-28 Hitachi Ltd Communication data processor and data receiving system
US6279140B1 (en) * 1999-01-07 2001-08-21 International Business Machines Corporation Method and apparatus for checksum verification with receive packet processing
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6565443B1 (en) 1999-09-14 2003-05-20 Innovative Gaming Corporation System and method for verifying the contents of a mass storage device before granting access to computer readable data stored on the device
US6550002B1 (en) * 1999-11-04 2003-04-15 International Business Machines Corporation Method and system for detecting a flush of an instruction without a flush indicator
US6964008B1 (en) * 1999-11-12 2005-11-08 Maxtor Corporation Data checksum method and apparatus
EP1260023A2 (en) 2000-02-17 2002-11-27 Analog Devices, Inc. Method, apparatus, and product for use in generating crc and other remainder based codes
US7292586B2 (en) * 2001-03-30 2007-11-06 Nokia Inc. Micro-programmable protocol packet parser and encapsulator
KR100434270B1 (en) * 2001-05-30 2004-06-04 엘지전자 주식회사 Control System for Home Appliance Network
US7310757B2 (en) 2001-10-11 2007-12-18 Altera Corporation Error detection on programmable logic resources
US6907466B2 (en) * 2001-11-08 2005-06-14 Extreme Networks, Inc. Methods and systems for efficiently delivering data to a plurality of destinations in a computer network
US7454601B2 (en) 2002-03-28 2008-11-18 Intel Corporation N-wide add-compare-select instruction
JP2003346432A (en) * 2002-05-22 2003-12-05 Internatl Business Mach Corp <Ibm> Data storage device and data processing method
US7627693B2 (en) * 2002-06-11 2009-12-01 Pandya Ashish A IP storage processor and engine therefor using RDMA
US6957321B2 (en) * 2002-06-19 2005-10-18 Intel Corporation Instruction set extension using operand bearing NOP instructions
US7103821B2 (en) * 2002-07-03 2006-09-05 Intel Corporation Method and apparatus for improving network router line rate performance by an improved system for error checking
US7036007B2 (en) 2002-09-09 2006-04-25 Intel Corporation Firmware architecture supporting safe updates and multiple processor types
US7313583B2 (en) * 2002-10-22 2007-12-25 Broadcom Corporation Galois field arithmetic unit for use within a processor
US7327781B2 (en) * 2002-12-17 2008-02-05 Invensys Systems, Inc. Universal intelligent modem
US7421637B1 (en) * 2003-01-16 2008-09-02 Cisco Technology, Inc. Generating test input for a circuit
TWI220962B (en) 2003-01-20 2004-09-11 Mediatek Inc Firmware updating method and related apparatus for checking content of replacing firmware before firmware updating
US7082563B2 (en) 2003-01-31 2006-07-25 Italtel S.P.A. Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets
US7392399B2 (en) 2003-05-05 2008-06-24 Sun Microsystems, Inc. Methods and systems for efficiently integrating a cryptographic co-processor
US7383428B2 (en) 2003-09-11 2008-06-03 International Business Machines Corporation Method, apparatus and computer program product for implementing atomic data tracing
US7826614B1 (en) 2003-11-05 2010-11-02 Globalfoundries Inc. Methods and apparatus for passing initialization vector information from software to hardware to perform IPsec encryption operation
TWI224729B (en) 2003-12-15 2004-12-01 Mediatek Inc Method for determining program code
US7360142B1 (en) * 2004-03-03 2008-04-15 Marvell Semiconductor Israel Ltd. Methods, architectures, circuits, software and systems for CRC determination
US8351468B2 (en) * 2004-04-05 2013-01-08 Broadcom Corporation Method and apparatus for downloading content using channel bonding
US7157944B1 (en) * 2004-04-27 2007-01-02 Altera Corporation Differential signal detector methods and apparatus
US7594124B2 (en) * 2004-06-09 2009-09-22 Intel Corporation Cross validation of data using multiple subsystems
US7676655B2 (en) 2004-06-30 2010-03-09 Sun Microsystems, Inc. Single bit control of threads in a multithreaded multicore processor
US7246191B2 (en) * 2005-03-31 2007-07-17 Intel Corporation Method and apparatus for memory interface
US7454667B2 (en) * 2005-04-26 2008-11-18 Intel Corporation Techniques to provide information validation and transfer
US7590930B2 (en) * 2005-05-24 2009-09-15 Intel Corporation Instructions for performing modulo-2 multiplication and bit reflection
US7805706B1 (en) * 2005-06-21 2010-09-28 Unisys Corporation Process for optimizing software components for an enterprise resource planning (ERP) application SAP on multiprocessor servers
US7646788B2 (en) 2005-08-03 2010-01-12 The Boeing Company TCP/IP tunneling protocol for link 16
US8335226B2 (en) * 2005-08-03 2012-12-18 Broadcom Corporation Systems and methods to transmit information among a plurality of physical upstream channels
US20070067698A1 (en) 2005-09-19 2007-03-22 King Steven R Techniques to perform prefetching of content in connection with integrity validation value determination
US7523378B2 (en) 2005-09-23 2009-04-21 Intel Corporation Techniques to determine integrity of information
DE102005061394A1 (en) * 2005-12-22 2007-06-28 Robert Bosch Gmbh Processor system e.g. control device, for controlling motor vehicle, has parity generator starting error handling routines in case of detection of bit errors, where routines are released to change different subsets of sets of variables
US7958436B2 (en) 2005-12-23 2011-06-07 Intel Corporation Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US7324913B2 (en) * 2006-02-01 2008-01-29 International Business Machines Corporation Methods and apparatus for testing a link between chips
US7925957B2 (en) 2006-03-20 2011-04-12 Intel Corporation Validating data using processor instructions
US7865704B2 (en) * 2006-03-29 2011-01-04 Freescale Semiconductor, Inc. Selective instruction breakpoint generation based on a count of instruction source events
US8024708B2 (en) 2006-06-20 2011-09-20 Google Inc. Systems and methods for debugging an application running on a parallel-processing computer system
US8209597B2 (en) 2009-03-23 2012-06-26 Cognitive Electronics, Inc. System and method for achieving improved accuracy from efficient computer architectures
US8612711B1 (en) 2009-09-21 2013-12-17 Tilera Corporation Memory-mapped data transfers
US8464125B2 (en) * 2009-12-10 2013-06-11 Intel Corporation Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
US8417961B2 (en) * 2010-03-16 2013-04-09 Oracle International Corporation Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)
US8910031B1 (en) * 2011-03-29 2014-12-09 Emc Corporation DIF-CRC based fast hashing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701316A (en) * 1995-08-31 1997-12-23 Unisys Corporation Method for generating an internet protocol suite checksum in a single macro instruction
US6631488B1 (en) * 2000-06-30 2003-10-07 Agilent Technologies, Inc. Configurable error detection and correction engine that has a specialized instruction set tailored for error detection and correction tasks
US20040243729A1 (en) * 2000-09-19 2004-12-02 Bbnt Solutions Llc Network processor having cyclic redundancy check implemented in hardware

Also Published As

Publication number Publication date
US9645884B2 (en) 2017-05-09
US20160224411A1 (en) 2016-08-04
US20120240016A1 (en) 2012-09-20
US8413024B2 (en) 2013-04-02
US8225184B2 (en) 2012-07-17
US8856627B2 (en) 2014-10-07
CN102708022A (en) 2012-10-03
US20130305016A1 (en) 2013-11-14
US9262159B2 (en) 2016-02-16
DE112006003298T5 (en) 2009-01-08
CN102708022B (en) 2015-07-08
US20070150795A1 (en) 2007-06-28
US8775912B2 (en) 2014-07-08
CN101305349A (en) 2008-11-12
WO2007078672A2 (en) 2007-07-12
US8775911B2 (en) 2014-07-08
US20110231744A1 (en) 2011-09-22
JP5269610B2 (en) 2013-08-21
US8775910B2 (en) 2014-07-08
US8793559B2 (en) 2014-07-29
US20130305117A1 (en) 2013-11-14
US20170242746A1 (en) 2017-08-24
US20150155883A1 (en) 2015-06-04
DE112006003298B4 (en) 2021-11-18
US8713416B2 (en) 2014-04-29
US10379938B2 (en) 2019-08-13
US20130305015A1 (en) 2013-11-14
TW200809488A (en) 2008-02-16
JP2009521059A (en) 2009-05-28
TWI360047B (en) 2012-03-11
US20130305011A1 (en) 2013-11-14
US11048579B2 (en) 2021-06-29
US11899530B2 (en) 2024-02-13
US20220091926A1 (en) 2022-03-24
US7958436B2 (en) 2011-06-07
US8769386B2 (en) 2014-07-01
US20200159614A1 (en) 2020-05-21
US20130191614A1 (en) 2013-07-25
US8769385B2 (en) 2014-07-01
US20140281798A1 (en) 2014-09-18
US9116684B2 (en) 2015-08-25
US20130305118A1 (en) 2013-11-14
CN101305349B (en) 2012-05-02
US20130305116A1 (en) 2013-11-14
US20130305115A1 (en) 2013-11-14

Similar Documents

Publication Publication Date Title
WO2007078672A3 (en) Performing a cyclic redundancy checksum operation responsive to a user-level instruction
WO2007011741A3 (en) Stable organic devices
EP1860554A4 (en) Communication system, information processing system, connection server, processing server, information processing device, information processing method, and program
WO2007054251A3 (en) Configurable circuit with configuration data protection features
WO2007067328A3 (en) Ion sources, systems and methods
WO2007022106A3 (en) Photovoltaic cells with interconnects to external circuit
EP1939738A4 (en) Policy processing system, method and program
EP1997267A4 (en) Communication system, communication device and processing method therefor
AU2003289274A1 (en) Wireless communication system, wireless communication device and wireless communication method, and computer program
NO20055468D0 (en) Computer communication system, communication device and associated communication program
WO2008019350A3 (en) A method and system for embedded group communication
EP1967964A4 (en) Information processing method, information processing system, and server
WO2007145875A3 (en) Data coding
WO2007075658A3 (en) System and method for processing composite trading orders
WO2010005661A3 (en) Efficient in-band reliability with separate cyclic redundancy code frames
BRPI0820268A2 (en) Mobile terminal, method on a mobile terminal, and, computer program product.
EP1936511A4 (en) Information communication system, information processing apparatus, and operating terminal
EP1732052A4 (en) Computer system, computer program, and addition method
GB2441475A (en) Techniques for reconfigurable decoder for a wireless system
EP1802047A4 (en) Communication method, communication message processing method, program for executing these methods on computer
MX2008000162A (en) Context-sensitive data handling.
EP1722571A4 (en) Data processor, data processing method and encoder
WO2008007802A3 (en) Lattice-reduction-aided detection applying a modified lenstra-lenstra-lovasz (lll) algorithm
WO2005040970A3 (en) Networked system and method for formulating, processing and managing challenges and solutions
WO2014011711A3 (en) Extensible content focus mode

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680042242.0

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 1120060032984

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 2008547301

Country of ref document: JP

RET De translation (de og part 6b)

Ref document number: 112006003298

Country of ref document: DE

Date of ref document: 20090108

Kind code of ref document: P

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 06845211

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 06845211

Country of ref document: EP

Kind code of ref document: A2