WO2007081642A3 - Flash devicewith shared word lines and manufacturing methods thereof - Google Patents

Flash devicewith shared word lines and manufacturing methods thereof Download PDF

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Publication number
WO2007081642A3
WO2007081642A3 PCT/US2006/062188 US2006062188W WO2007081642A3 WO 2007081642 A3 WO2007081642 A3 WO 2007081642A3 US 2006062188 W US2006062188 W US 2006062188W WO 2007081642 A3 WO2007081642 A3 WO 2007081642A3
Authority
WO
WIPO (PCT)
Prior art keywords
word lines
devicewith
flash
manufacturing methods
shared word
Prior art date
Application number
PCT/US2006/062188
Other languages
French (fr)
Other versions
WO2007081642A2 (en
Inventor
Masaaki Higashitani
Original Assignee
Sandisk Corp
Masaaki Higashitani
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/316,654 external-priority patent/US7495294B2/en
Priority claimed from US11/316,474 external-priority patent/US7655536B2/en
Application filed by Sandisk Corp, Masaaki Higashitani filed Critical Sandisk Corp
Priority to EP06849250A priority Critical patent/EP1964170A2/en
Publication of WO2007081642A2 publication Critical patent/WO2007081642A2/en
Publication of WO2007081642A3 publication Critical patent/WO2007081642A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.
PCT/US2006/062188 2005-12-21 2006-12-15 Flash devicewith shared word lines and manufacturing methods thereof WO2007081642A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06849250A EP1964170A2 (en) 2005-12-21 2006-12-15 Flash devices with shared word lines and manufacturing methods therefor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/316,654 2005-12-21
US11/316,654 US7495294B2 (en) 2005-12-21 2005-12-21 Flash devices with shared word lines
US11/316,474 2005-12-21
US11/316,474 US7655536B2 (en) 2005-12-21 2005-12-21 Methods of forming flash devices with shared word lines

Publications (2)

Publication Number Publication Date
WO2007081642A2 WO2007081642A2 (en) 2007-07-19
WO2007081642A3 true WO2007081642A3 (en) 2008-03-13

Family

ID=38256847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/062188 WO2007081642A2 (en) 2005-12-21 2006-12-15 Flash devicewith shared word lines and manufacturing methods thereof

Country Status (3)

Country Link
EP (1) EP1964170A2 (en)
TW (1) TWI318404B (en)
WO (1) WO2007081642A2 (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2433803A1 (en) * 1973-07-27 1975-02-13 Itt Ind Gmbh Deutsche FIELD EFFECT TRANSISTOR WITH INSULATED CONTROL ELECTRODE
US4185319A (en) * 1978-10-04 1980-01-22 Rca Corp. Non-volatile memory device
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays
US5712179A (en) * 1995-10-31 1998-01-27 Sandisk Corporation Method of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US6239500B1 (en) * 1999-02-05 2001-05-29 Fujitsu Limited Semiconductor device with common bit contact area
US20010005330A1 (en) * 1999-12-10 2001-06-28 Samsung. Nand-type flash memory device and method of operating the same
US20020109194A1 (en) * 2000-12-27 2002-08-15 Kazuteru Ishizuka Semiconductor device
US20030157436A1 (en) * 2002-02-20 2003-08-21 Dirk Manger Method for forming a hard mask in a layer on a planar device
US20050072999A1 (en) * 2003-10-06 2005-04-07 George Matamis Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US20050180186A1 (en) * 2004-02-13 2005-08-18 Lutze Jeffrey W. Shield plate for limiting cross coupling between floating gates

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2433803A1 (en) * 1973-07-27 1975-02-13 Itt Ind Gmbh Deutsche FIELD EFFECT TRANSISTOR WITH INSULATED CONTROL ELECTRODE
US4185319A (en) * 1978-10-04 1980-01-22 Rca Corp. Non-volatile memory device
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays
US5712179A (en) * 1995-10-31 1998-01-27 Sandisk Corporation Method of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6239500B1 (en) * 1999-02-05 2001-05-29 Fujitsu Limited Semiconductor device with common bit contact area
US20010005330A1 (en) * 1999-12-10 2001-06-28 Samsung. Nand-type flash memory device and method of operating the same
US20020109194A1 (en) * 2000-12-27 2002-08-15 Kazuteru Ishizuka Semiconductor device
US20030157436A1 (en) * 2002-02-20 2003-08-21 Dirk Manger Method for forming a hard mask in a layer on a planar device
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US20050072999A1 (en) * 2003-10-06 2005-04-07 George Matamis Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
US20050180186A1 (en) * 2004-02-13 2005-08-18 Lutze Jeffrey W. Shield plate for limiting cross coupling between floating gates

Also Published As

Publication number Publication date
TW200733116A (en) 2007-09-01
EP1964170A2 (en) 2008-09-03
TWI318404B (en) 2009-12-11
WO2007081642A2 (en) 2007-07-19

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