WO2007082199A3 - Structure and method for making high density mosfet circuits with different height contact lines - Google Patents
Structure and method for making high density mosfet circuits with different height contact lines Download PDFInfo
- Publication number
- WO2007082199A3 WO2007082199A3 PCT/US2007/060265 US2007060265W WO2007082199A3 WO 2007082199 A3 WO2007082199 A3 WO 2007082199A3 US 2007060265 W US2007060265 W US 2007060265W WO 2007082199 A3 WO2007082199 A3 WO 2007082199A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- high density
- mosfet circuits
- contact line
- different height
- making high
- Prior art date
Links
- 125000006850 spacer group Chemical group 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/92—Conductor layers on different levels connected in parallel, e.g. to reduce resistance
Abstract
Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line (500, 1300), a gate (310, 1210) situated proximate the contact line (500, 1300). The contact line (500, 1300) comprises a height that is less than the height of the gate (310, 1210). The MOSFET circuits further comprise gate spacers (710, 715, 1610, 1615) situated proximate the gate (310, 1210) and no contact line spacer situated proximate the contact line (500, 1300) and between the contact line (500, 1300) and the gate (310, 1210).
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT07710010T ATE535941T1 (en) | 2006-01-09 | 2007-01-09 | STRUCTURE AND METHOD FOR PRODUCING HIGH DENSITY MOSFET CIRCUITS WITH CONTACT LINES OF DIFFERENT HEIGHTS |
CN2007800016826A CN101361186B (en) | 2006-01-09 | 2007-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
EP07710010A EP1979941B1 (en) | 2006-01-09 | 2007-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
JP2008549683A JP5225102B2 (en) | 2006-01-09 | 2007-01-09 | Structure and method for manufacturing high density MOSFET circuits with different height contact lines |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/306,707 | 2006-01-09 | ||
US11/306,707 US7339230B2 (en) | 2006-01-09 | 2006-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007082199A2 WO2007082199A2 (en) | 2007-07-19 |
WO2007082199A3 true WO2007082199A3 (en) | 2007-11-29 |
Family
ID=38257099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/060265 WO2007082199A2 (en) | 2006-01-09 | 2007-01-09 | Structure and method for making high density mosfet circuits with different height contact lines |
Country Status (7)
Country | Link |
---|---|
US (2) | US7339230B2 (en) |
EP (1) | EP1979941B1 (en) |
JP (1) | JP5225102B2 (en) |
CN (1) | CN101361186B (en) |
AT (1) | ATE535941T1 (en) |
TW (1) | TWI409948B (en) |
WO (1) | WO2007082199A2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009111200A (en) * | 2007-10-31 | 2009-05-21 | Panasonic Corp | Semiconductor device and fabrication method for same |
US8692310B2 (en) | 2009-02-09 | 2014-04-08 | Spansion Llc | Gate fringing effect based channel formation for semiconductor device |
KR20100101446A (en) * | 2009-03-09 | 2010-09-17 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US8729627B2 (en) | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US8507375B1 (en) * | 2012-02-02 | 2013-08-13 | GlobalFoundries, Inc. | Alignment tolerant semiconductor contact and method |
US9786557B1 (en) * | 2016-04-12 | 2017-10-10 | International Business Machines Corporation | Two-dimensional self-aligned super via integration on self-aligned gate contact |
FR3069369B1 (en) * | 2017-07-21 | 2019-11-01 | Stmicroelectronics (Rousset) Sas | INTEGRATED CIRCUIT WITH SHARED MASK CONTACT |
KR20200085071A (en) | 2019-01-04 | 2020-07-14 | 주식회사 엘지화학 | Apparatus and Method for measuring current of battery |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6136649A (en) * | 1999-10-12 | 2000-10-24 | Advanced Micro Devices, Inc. | Method for removing anti-reflective coating layer using plasma etch process after contact CMP |
US20040023478A1 (en) * | 2002-07-31 | 2004-02-05 | Samavedam Srikanth B. | Capped dual metal gate transistors for CMOS process and method for making the same |
Family Cites Families (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5232863A (en) * | 1992-10-20 | 1993-08-03 | Micron Semiconductor, Inc. | Method of forming electrical contact between a field effect transistor gate and a remote active area |
JPH07321217A (en) * | 1994-05-19 | 1995-12-08 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
JP2606143B2 (en) * | 1994-07-22 | 1997-04-30 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
GB2292008A (en) * | 1994-07-28 | 1996-02-07 | Hyundai Electronics Ind | A split gate type flash eeprom cell |
KR960030440A (en) | 1995-01-12 | 1996-08-17 | 모리시다 요이치 | Semiconductor device and manufacturing method thereof |
US5668065A (en) * | 1996-08-01 | 1997-09-16 | Winbond Electronics Corp. | Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects |
JPH10308454A (en) * | 1997-05-02 | 1998-11-17 | Mitsubishi Electric Corp | Semiconductor device and manufacture of the same |
JP2964993B2 (en) * | 1997-05-28 | 1999-10-18 | 日本電気株式会社 | Semiconductor storage device |
US6420273B1 (en) * | 1997-06-30 | 2002-07-16 | Koninklijke Philips Electronics N.V. | Self-aligned etch-stop layer formation for semiconductor devices |
JP3239940B2 (en) * | 1997-09-10 | 2001-12-17 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JP3075351B2 (en) * | 1998-03-24 | 2000-08-14 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6127706A (en) * | 1998-04-23 | 2000-10-03 | Texas Instruments - Acer Incorporated | Trench-free buried contact for SRAM devices |
TW386283B (en) * | 1998-05-25 | 2000-04-01 | United Microelectronics Corp | A method of manufacturing the buried contact of an SRAM cell |
JP2000100964A (en) * | 1998-09-18 | 2000-04-07 | Seiko Epson Corp | Semiconductor device |
US6127216A (en) * | 1998-11-06 | 2000-10-03 | Advanced Micro Devices, Inc. | Heavily-doped polysilicon/germanium thin film formed by laser annealing |
TWI231969B (en) * | 1999-03-26 | 2005-05-01 | Mosel Vitelic Inc | Method for forming dual-gate MOS and interconnect with self-aligned contact |
US6281559B1 (en) * | 1999-03-03 | 2001-08-28 | Advanced Micro Devices, Inc. | Gate stack structure for variable threshold voltage |
JP2000294546A (en) * | 1999-03-25 | 2000-10-20 | Motorola Inc | Manufacture of semiconductor device |
US6518618B1 (en) * | 1999-12-03 | 2003-02-11 | Intel Corporation | Integrated memory cell and method of fabrication |
US6420752B1 (en) * | 2000-02-11 | 2002-07-16 | Advanced Micro Devices, Inc. | Semiconductor device with self-aligned contacts using a liner oxide layer |
JP2001338979A (en) | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
US6271087B1 (en) * | 2000-10-10 | 2001-08-07 | Advanced Micro Devices, Inc. | Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects |
US6552401B1 (en) * | 2000-11-27 | 2003-04-22 | Micron Technology | Use of gate electrode workfunction to improve DRAM refresh |
US6509253B1 (en) * | 2001-02-16 | 2003-01-21 | Advanced Micro Devices, Inc. | T-shaped gate electrode for reduced resistance |
US6734510B2 (en) * | 2001-03-15 | 2004-05-11 | Micron Technology, Ing. | Technique to mitigate short channel effects with vertical gate transistor with different gate materials |
JP2003007819A (en) * | 2001-06-27 | 2003-01-10 | Sharp Corp | Method of manufacturing semiconductor device |
US6596599B1 (en) * | 2001-07-16 | 2003-07-22 | Taiwan Semiconductor Manufacturing Company | Gate stack for high performance sub-micron CMOS devices |
JP4628644B2 (en) * | 2001-10-04 | 2011-02-09 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US6638861B1 (en) * | 2001-11-08 | 2003-10-28 | Advanced Micro Devices, Inc. | Method of eliminating voids in W plugs |
KR100790965B1 (en) * | 2002-03-09 | 2008-01-02 | 삼성전자주식회사 | Semiconductor device prevented ring defect and method for manufacturing the same |
TW533588B (en) * | 2002-04-24 | 2003-05-21 | Nanya Technology Corp | Flash memory and its manufacturing method |
KR100487525B1 (en) * | 2002-04-25 | 2005-05-03 | 삼성전자주식회사 | Semiconductor device using silicon-germanium gate and method for fabricating the same |
JP4102112B2 (en) | 2002-06-06 | 2008-06-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US20040004251A1 (en) * | 2002-07-08 | 2004-01-08 | Madurawe Raminda U. | Insulated-gate field-effect thin film transistors |
TW561506B (en) * | 2002-07-22 | 2003-11-11 | Taiwan Semiconductor Mfg | Method for forming MOSFET |
KR100481864B1 (en) * | 2002-10-29 | 2005-04-11 | 삼성전자주식회사 | Method of forming semiconductor devices |
AU2003283730A1 (en) * | 2002-12-19 | 2004-07-14 | Koninklijke Philips Electronics N.V. | Electric device comprising a layer of phase change material and method of manufacturing the same |
JP2004228231A (en) * | 2003-01-21 | 2004-08-12 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
KR100509948B1 (en) * | 2003-04-01 | 2005-08-24 | 한국전자통신연구원 | MOSFET device having nano-scale gate length and method for manufacturing the same |
DE10318283A1 (en) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Process for producing a strained layer on a substrate and layer structure |
US7129539B2 (en) | 2003-05-15 | 2006-10-31 | Sharp Kabushiki Kaisha | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card |
JP2005064127A (en) * | 2003-08-08 | 2005-03-10 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
DE10336876B4 (en) * | 2003-08-11 | 2006-08-24 | Infineon Technologies Ag | Memory cell with nanocrystals or nanodots and process for their preparation |
JP2005175090A (en) * | 2003-12-09 | 2005-06-30 | Toshiba Corp | Semiconductor memory device and its manufacturing method |
US7135731B2 (en) * | 2003-12-10 | 2006-11-14 | Nanya Technology Corp. | Vertical DRAM and fabrication method thereof |
KR100543471B1 (en) * | 2003-12-30 | 2006-01-20 | 삼성전자주식회사 | Method of forming contact structure of a nor-type flash memory cell |
JP2005347296A (en) * | 2004-05-31 | 2005-12-15 | Toshiba Corp | Semiconductor device and its manufacturing method |
KR100626383B1 (en) * | 2004-08-16 | 2006-09-20 | 삼성전자주식회사 | Transistor having a partially elevated source/drain structure and method of fabricating the same |
US7259083B2 (en) * | 2004-10-22 | 2007-08-21 | Lsi Corporation | Local interconnect manufacturing process |
JP2006165435A (en) * | 2004-12-10 | 2006-06-22 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
-
2006
- 2006-01-09 US US11/306,707 patent/US7339230B2/en active Active
-
2007
- 2007-01-03 TW TW096100169A patent/TWI409948B/en not_active IP Right Cessation
- 2007-01-09 AT AT07710010T patent/ATE535941T1/en active
- 2007-01-09 CN CN2007800016826A patent/CN101361186B/en not_active Expired - Fee Related
- 2007-01-09 JP JP2008549683A patent/JP5225102B2/en not_active Expired - Fee Related
- 2007-01-09 WO PCT/US2007/060265 patent/WO2007082199A2/en active Application Filing
- 2007-01-09 EP EP07710010A patent/EP1979941B1/en not_active Not-in-force
- 2007-10-19 US US11/874,963 patent/US7750415B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6136649A (en) * | 1999-10-12 | 2000-10-24 | Advanced Micro Devices, Inc. | Method for removing anti-reflective coating layer using plasma etch process after contact CMP |
US20040023478A1 (en) * | 2002-07-31 | 2004-02-05 | Samavedam Srikanth B. | Capped dual metal gate transistors for CMOS process and method for making the same |
Also Published As
Publication number | Publication date |
---|---|
EP1979941A4 (en) | 2011-03-23 |
WO2007082199A2 (en) | 2007-07-19 |
CN101361186A (en) | 2009-02-04 |
US20070170472A1 (en) | 2007-07-26 |
JP5225102B2 (en) | 2013-07-03 |
US7750415B2 (en) | 2010-07-06 |
US20080029836A1 (en) | 2008-02-07 |
EP1979941B1 (en) | 2011-11-30 |
ATE535941T1 (en) | 2011-12-15 |
TWI409948B (en) | 2013-09-21 |
TW200742074A (en) | 2007-11-01 |
CN101361186B (en) | 2012-07-18 |
EP1979941A2 (en) | 2008-10-15 |
US7339230B2 (en) | 2008-03-04 |
JP2009522819A (en) | 2009-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2007082199A3 (en) | Structure and method for making high density mosfet circuits with different height contact lines | |
TW200629422A (en) | Method of manufacturing a capaciotr and a metal gate on a semiconductor device | |
TW200741978A (en) | Stressor integration and method thereof | |
TW200746428A (en) | Tunneling transistor with sublithographic channel | |
TW200802811A (en) | Semiconductor structure and method for forming the same | |
TW200742045A (en) | Semiconductor device having a recess channel transistor | |
WO2009012276A3 (en) | Asymmetric field effect transistor structure and method | |
TW200742070A (en) | Method for forming a semiconductor device having a fin and structure thereof | |
TW200703437A (en) | Semiconductor device and manufacturing method thereof | |
GB0508407D0 (en) | Alignment of trench for MOS | |
TW200623772A (en) | Apparatus and method capable of network access | |
WO2007127503A3 (en) | Structure and method for mosfet gate electrode landing pad | |
SG165354A1 (en) | Integrated circuit system employing stress memorization transfer | |
WO2008076092A3 (en) | Semiconductor device and method for forming the same | |
EP1455330A4 (en) | Electro-optical device manufacturing method, electro-optical device manufactured by the manufacturing method, and electronic device | |
WO2007055863A3 (en) | Fine pitch interconnect and method of making | |
WO2005122731A3 (en) | Method to form a conductive structure | |
TW200731534A (en) | A high-voltage metal-oxide-semiconductor device and a double- diffused-drain metal-oxide-semiconductor device | |
WO2007018967A3 (en) | Methods of forming memory circuitry with different insulative sidewall spacers | |
TW200731538A (en) | Electronic device with a multi-gated electrode structure and a process for forming the electronic device | |
WO2007120291A3 (en) | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same | |
TW200731422A (en) | Semiconductor device structure having low and high performance devices of same conductive type on same substrate | |
WO2007041100A3 (en) | Pakaged electronic devices and process of manufacturing same | |
TW200633136A (en) | Pyramid-shaped capacitor structure | |
TW200739749A (en) | Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200780001682.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2008549683 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007710010 Country of ref document: EP |