WO2007089535A3 - Cross-architecture optimization - Google Patents

Cross-architecture optimization Download PDF

Info

Publication number
WO2007089535A3
WO2007089535A3 PCT/US2007/002044 US2007002044W WO2007089535A3 WO 2007089535 A3 WO2007089535 A3 WO 2007089535A3 US 2007002044 W US2007002044 W US 2007002044W WO 2007089535 A3 WO2007089535 A3 WO 2007089535A3
Authority
WO
WIPO (PCT)
Prior art keywords
cross
architecture optimization
computing machine
instruction associated
machine architecture
Prior art date
Application number
PCT/US2007/002044
Other languages
French (fr)
Other versions
WO2007089535A2 (en
Inventor
Bran Ferren
W Daniel Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood Jr
Original Assignee
Searete Llc
Bran Ferren
W Daniel Hillis
William Henry Mangione-Smith
Nathan P Myhrvold
Clarence T Tegreene
Lowell L Wood Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/343,745 external-priority patent/US8209524B2/en
Priority claimed from US11/343,927 external-priority patent/US8214191B2/en
Application filed by Searete Llc, Bran Ferren, W Daniel Hillis, William Henry Mangione-Smith, Nathan P Myhrvold, Clarence T Tegreene, Lowell L Wood Jr filed Critical Searete Llc
Publication of WO2007089535A2 publication Critical patent/WO2007089535A2/en
Publication of WO2007089535A3 publication Critical patent/WO2007089535A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware

Abstract

Embodiments include a device, apparatus, and a method. An apparatus includes a monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture. The apparatus also includes a generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture.
PCT/US2007/002044 2006-01-31 2007-01-22 Cross-architecture optimization WO2007089535A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/343,927 2006-01-31
US11/343,745 US8209524B2 (en) 2005-08-29 2006-01-31 Cross-architecture optimization
US11/343,927 US8214191B2 (en) 2005-08-29 2006-01-31 Cross-architecture execution optimization
US11/343,745 2006-01-31

Publications (2)

Publication Number Publication Date
WO2007089535A2 WO2007089535A2 (en) 2007-08-09
WO2007089535A3 true WO2007089535A3 (en) 2008-10-09

Family

ID=38327887

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/002044 WO2007089535A2 (en) 2006-01-31 2007-01-22 Cross-architecture optimization

Country Status (1)

Country Link
WO (1) WO2007089535A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199095B1 (en) * 1996-01-29 2001-03-06 Compaq Computer Corporation System and method for achieving object method transparency in a multi-code execution environment
US20020032718A1 (en) * 1996-01-29 2002-03-14 John S. Yates Method and apparatus for maintaining translated routine stack in a binary translation enviroment
US20050086650A1 (en) * 1999-01-28 2005-04-21 Ati International Srl Transferring execution from one instruction stream to another

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199095B1 (en) * 1996-01-29 2001-03-06 Compaq Computer Corporation System and method for achieving object method transparency in a multi-code execution environment
US20020032718A1 (en) * 1996-01-29 2002-03-14 John S. Yates Method and apparatus for maintaining translated routine stack in a binary translation enviroment
US20050086650A1 (en) * 1999-01-28 2005-04-21 Ati International Srl Transferring execution from one instruction stream to another

Also Published As

Publication number Publication date
WO2007089535A2 (en) 2007-08-09

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