WO2007100487A3 - Distributive scoreboard scheduling in an out-of-order processor - Google Patents
Distributive scoreboard scheduling in an out-of-order processor Download PDFInfo
- Publication number
- WO2007100487A3 WO2007100487A3 PCT/US2007/003752 US2007003752W WO2007100487A3 WO 2007100487 A3 WO2007100487 A3 WO 2007100487A3 US 2007003752 W US2007003752 W US 2007003752W WO 2007100487 A3 WO2007100487 A3 WO 2007100487A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- instruction
- distributive
- scoreboard
- operand availability
- availability bits
- Prior art date
Links
- 230000000644 propagated effect Effects 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
Abstract
A processor core and a method for distributive Scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive Scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0814234A GB2448276B (en) | 2006-02-28 | 2007-02-12 | Distributive scoreboard scheduling in an out-of-order processor |
CN200780007020.XA CN101395573B (en) | 2006-02-28 | 2007-02-12 | Distributive scoreboard scheduling in an out-of order processor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/362,764 US7721071B2 (en) | 2006-02-28 | 2006-02-28 | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US11/362,764 | 2006-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007100487A2 WO2007100487A2 (en) | 2007-09-07 |
WO2007100487A3 true WO2007100487A3 (en) | 2007-11-22 |
Family
ID=38265592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/003752 WO2007100487A2 (en) | 2006-02-28 | 2007-02-12 | Distributive scoreboard scheduling in an out-of-order processor |
Country Status (4)
Country | Link |
---|---|
US (1) | US7721071B2 (en) |
CN (1) | CN101395573B (en) |
GB (1) | GB2448276B (en) |
WO (1) | WO2007100487A2 (en) |
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- 2006-02-28 US US11/362,764 patent/US7721071B2/en active Active
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2007
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- 2007-02-12 WO PCT/US2007/003752 patent/WO2007100487A2/en active Application Filing
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6393550B1 (en) * | 1993-12-30 | 2002-05-21 | Intel Corporation | Method and apparatus for pipeline streamlining where resources are immediate or certainly retired |
US5546545A (en) * | 1994-12-09 | 1996-08-13 | International Business Machines Corporation | Rotating priority selection logic circuit |
GB2322718A (en) * | 1996-12-09 | 1998-09-02 | Ibm | Dynamic classification and dispatch of instructions out of order |
Also Published As
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GB2448276B (en) | 2011-06-15 |
GB0814234D0 (en) | 2008-09-10 |
US20070204135A1 (en) | 2007-08-30 |
GB2448276A (en) | 2008-10-08 |
WO2007100487A2 (en) | 2007-09-07 |
US7721071B2 (en) | 2010-05-18 |
CN101395573B (en) | 2012-06-06 |
CN101395573A (en) | 2009-03-25 |
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