WO2007100487A3 - Distributive scoreboard scheduling in an out-of-order processor - Google Patents

Distributive scoreboard scheduling in an out-of-order processor Download PDF

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Publication number
WO2007100487A3
WO2007100487A3 PCT/US2007/003752 US2007003752W WO2007100487A3 WO 2007100487 A3 WO2007100487 A3 WO 2007100487A3 US 2007003752 W US2007003752 W US 2007003752W WO 2007100487 A3 WO2007100487 A3 WO 2007100487A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
distributive
scoreboard
operand availability
availability bits
Prior art date
Application number
PCT/US2007/003752
Other languages
French (fr)
Other versions
WO2007100487A2 (en
Inventor
Xing Yu Jiang
Original Assignee
Mips Tech Inc
Xing Yu Jiang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Tech Inc, Xing Yu Jiang filed Critical Mips Tech Inc
Priority to GB0814234A priority Critical patent/GB2448276B/en
Priority to CN200780007020.XA priority patent/CN101395573B/en
Publication of WO2007100487A2 publication Critical patent/WO2007100487A2/en
Publication of WO2007100487A3 publication Critical patent/WO2007100487A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

A processor core and a method for distributive Scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive Scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.
PCT/US2007/003752 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor WO2007100487A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0814234A GB2448276B (en) 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor
CN200780007020.XA CN101395573B (en) 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of order processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/362,764 US7721071B2 (en) 2006-02-28 2006-02-28 System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US11/362,764 2006-02-28

Publications (2)

Publication Number Publication Date
WO2007100487A2 WO2007100487A2 (en) 2007-09-07
WO2007100487A3 true WO2007100487A3 (en) 2007-11-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/003752 WO2007100487A2 (en) 2006-02-28 2007-02-12 Distributive scoreboard scheduling in an out-of-order processor

Country Status (4)

Country Link
US (1) US7721071B2 (en)
CN (1) CN101395573B (en)
GB (1) GB2448276B (en)
WO (1) WO2007100487A2 (en)

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Also Published As

Publication number Publication date
GB2448276A (en) 2008-10-08
WO2007100487A2 (en) 2007-09-07
GB0814234D0 (en) 2008-09-10
CN101395573B (en) 2012-06-06
CN101395573A (en) 2009-03-25
GB2448276B (en) 2011-06-15
US20070204135A1 (en) 2007-08-30
US7721071B2 (en) 2010-05-18

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