WO2007100558A3 - Modeling for semiconductor fabrication process effects - Google Patents

Modeling for semiconductor fabrication process effects Download PDF

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Publication number
WO2007100558A3
WO2007100558A3 PCT/US2007/004414 US2007004414W WO2007100558A3 WO 2007100558 A3 WO2007100558 A3 WO 2007100558A3 US 2007004414 W US2007004414 W US 2007004414W WO 2007100558 A3 WO2007100558 A3 WO 2007100558A3
Authority
WO
WIPO (PCT)
Prior art keywords
adjusted
simulation
contour
layout
width
Prior art date
Application number
PCT/US2007/004414
Other languages
French (fr)
Other versions
WO2007100558A2 (en
Inventor
Jean-Marie Brunet
William S Graupp
Original Assignee
Mentor Graphics Corp
Jean-Marie Brunet
William S Graupp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/707,635 external-priority patent/US8015510B2/en
Application filed by Mentor Graphics Corp, Jean-Marie Brunet, William S Graupp filed Critical Mentor Graphics Corp
Publication of WO2007100558A2 publication Critical patent/WO2007100558A2/en
Publication of WO2007100558A3 publication Critical patent/WO2007100558A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined, such as a gate or interconnect. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates variation factors that may occur in the photolithographic process. One or more adjusted widths and adjusted lengths of the object are then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor or interconnect using the adjusted width and adjusted length.
PCT/US2007/004414 2006-02-17 2007-02-20 Modeling for semiconductor fabrication process effects WO2007100558A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US77451106P 2006-02-17 2006-02-17
US60/774,511 2006-02-17
US11/707,635 2007-02-16
US11/707,635 US8015510B2 (en) 2006-02-17 2007-02-16 Interconnection modeling for semiconductor fabrication process effects
US11/707,661 US7577932B2 (en) 2006-02-17 2007-02-16 Gate modeling for semiconductor fabrication process effects
US11/707,661 2007-02-16

Publications (2)

Publication Number Publication Date
WO2007100558A2 WO2007100558A2 (en) 2007-09-07
WO2007100558A3 true WO2007100558A3 (en) 2008-04-03

Family

ID=38459520

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/004414 WO2007100558A2 (en) 2006-02-17 2007-02-20 Modeling for semiconductor fabrication process effects

Country Status (1)

Country Link
WO (1) WO2007100558A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200811684A (en) 2006-02-17 2008-03-01 Mentor Graphics Corp Gate modeling for semiconductor fabrication process effects

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610833A (en) * 1992-06-02 1997-03-11 Hewlett-Packard Company Computer-aided design methods and apparatus for multilevel interconnect technologies
US6219630B1 (en) * 1995-12-07 2001-04-17 Matsushita Electronics Corporation Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist
US6562638B1 (en) * 1999-12-30 2003-05-13 Cypress Semiconductor Corp. Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
US20050251771A1 (en) * 2004-05-07 2005-11-10 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610833A (en) * 1992-06-02 1997-03-11 Hewlett-Packard Company Computer-aided design methods and apparatus for multilevel interconnect technologies
US6219630B1 (en) * 1995-12-07 2001-04-17 Matsushita Electronics Corporation Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist
US6562638B1 (en) * 1999-12-30 2003-05-13 Cypress Semiconductor Corp. Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
US20050251771A1 (en) * 2004-05-07 2005-11-10 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands

Also Published As

Publication number Publication date
WO2007100558A2 (en) 2007-09-07

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