WO2007103147A3 - U-shaped transistor and corresponding manufacturing method - Google Patents

U-shaped transistor and corresponding manufacturing method Download PDF

Info

Publication number
WO2007103147A3
WO2007103147A3 PCT/US2007/005305 US2007005305W WO2007103147A3 WO 2007103147 A3 WO2007103147 A3 WO 2007103147A3 US 2007005305 W US2007005305 W US 2007005305W WO 2007103147 A3 WO2007103147 A3 WO 2007103147A3
Authority
WO
WIPO (PCT)
Prior art keywords
region
trenches
over
etched
lines
Prior art date
Application number
PCT/US2007/005305
Other languages
French (fr)
Other versions
WO2007103147A2 (en
Inventor
Werner Juengling
Original Assignee
Micron Technology Inc
Werner Juengling
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Werner Juengling filed Critical Micron Technology Inc
Priority to JP2008557387A priority Critical patent/JP5282888B2/en
Priority to EP07752033.6A priority patent/EP2011147B1/en
Priority to KR1020087024116A priority patent/KR101364780B1/en
Priority to CN2007800071397A priority patent/CN101395714B/en
Publication of WO2007103147A2 publication Critical patent/WO2007103147A2/en
Publication of WO2007103147A3 publication Critical patent/WO2007103147A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Abstract

A method of forming a memory with U-shaped transistors (500) with source/drain regions (502, 504) and channels (506) comprises forming a plurality of parallel deep (400) and shallow (404) trenches in a first substrate region (308) wherein at least one shallow trench is positioned between two deep trenches. A layer of conductive material (454) is deposited over said first region (308) and a second substrate region (310) and is etched to define a plurality of lines (470) separated by gaps over the first region (308) and a plurality of active device elements (460) over the second region (310). Said plurality of lines is removed from said first region to create a plurality of exposed areas (476) into which a plurality of elongated trenches are etched, while the second region (310) is masked.
PCT/US2007/005305 2006-03-02 2007-03-01 U-shaped transistor and corresponding manufacturing method WO2007103147A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008557387A JP5282888B2 (en) 2006-03-02 2007-03-01 U-type transistor and related manufacturing method
EP07752033.6A EP2011147B1 (en) 2006-03-02 2007-03-01 U-shaped access transistor and corresponding manufacturing method
KR1020087024116A KR101364780B1 (en) 2006-03-02 2007-03-01 U-shaped transistor and corresponding manufacturing method
CN2007800071397A CN101395714B (en) 2006-03-02 2007-03-01 U-shaped transistor and corresponding manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/366,212 2006-03-02
US11/366,212 US7476933B2 (en) 2006-03-02 2006-03-02 Vertical gated access transistor

Publications (2)

Publication Number Publication Date
WO2007103147A2 WO2007103147A2 (en) 2007-09-13
WO2007103147A3 true WO2007103147A3 (en) 2007-11-01

Family

ID=38377328

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/005305 WO2007103147A2 (en) 2006-03-02 2007-03-01 U-shaped transistor and corresponding manufacturing method

Country Status (6)

Country Link
US (5) US7476933B2 (en)
EP (1) EP2011147B1 (en)
JP (1) JP5282888B2 (en)
KR (1) KR101364780B1 (en)
CN (1) CN101395714B (en)
WO (1) WO2007103147A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9184161B2 (en) 2006-03-02 2015-11-10 Micron Technology, Inc. Vertical gated access transistor

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7897058B2 (en) * 2006-02-13 2011-03-01 Asml Netherlands B.V. Device manufacturing method and computer program product
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7602001B2 (en) * 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
KR100791344B1 (en) * 2006-08-29 2008-01-03 삼성전자주식회사 Method of fabricating semiconductor integrated circuit device
US7825460B2 (en) * 2006-09-06 2010-11-02 International Business Machines Corporation Vertical field effect transistor arrays and methods for fabrication thereof
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7859050B2 (en) * 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device
KR100881513B1 (en) * 2007-05-18 2009-02-05 주식회사 동부하이텍 Method for forming semiconductor fine-pitch pattern
US7696040B2 (en) * 2007-05-30 2010-04-13 International Business Machines Corporation Method for fabrication of fin memory structure
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7856613B1 (en) 2008-01-30 2010-12-21 Cadence Design Systems, Inc. Method for self-aligned doubled patterning lithography
US8866254B2 (en) * 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US7800965B2 (en) 2008-03-10 2010-09-21 Micron Technology, Inc. Digit line equilibration using access devices at the edge of sub-arrays
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) * 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US7824983B2 (en) * 2008-06-02 2010-11-02 Micron Technology, Inc. Methods of providing electrical isolation in semiconductor structures
JP2009295785A (en) * 2008-06-05 2009-12-17 Toshiba Corp Method of manufacturing semiconductor device
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
CN101752225B (en) * 2008-12-04 2011-09-28 上海华虹Nec电子有限公司 Multistage etching and filling method of ultra-deep groove
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
KR101559063B1 (en) * 2009-02-02 2015-10-08 삼성전자주식회사 Method of manufacturing a semiconductor device
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
KR101561061B1 (en) * 2009-04-10 2015-10-16 삼성전자주식회사 Semiconductor device having a protrusion typed isolation layer
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
TW201126572A (en) * 2009-10-26 2011-08-01 Sandisk 3D Llc Methods of forming pillars for memory cells using sequential sidewall patterning
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
KR101723864B1 (en) * 2010-10-08 2017-04-07 삼성전자주식회사 Semiconductor Device With Vertical Channel Transistor And Method Of Fabricating The Same
US8921899B2 (en) 2010-11-19 2014-12-30 Micron Technology, Inc. Double gated 4F2 dram CHC cell and methods of fabricating the same
KR101205118B1 (en) * 2011-03-11 2012-11-26 에스케이하이닉스 주식회사 Semiconductor Device and Method for Manufacturing the same
US8293615B2 (en) * 2011-03-24 2012-10-23 International Business Machines Corporation Self-aligned dual depth isolation and method of fabrication
US9673102B2 (en) 2011-04-01 2017-06-06 Micron Technology, Inc. Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8648414B2 (en) * 2011-07-01 2014-02-11 Micron Technology, Inc. Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8912065B2 (en) * 2012-06-15 2014-12-16 Nanya Technology Corporation Method of fabricating semiconductor device
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
KR102013842B1 (en) 2013-02-08 2019-08-26 삼성전자주식회사 Method of manufacturing semiconductor device
US9023695B2 (en) * 2013-03-14 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning features of a semiconductor device
RU2626970C2 (en) * 2013-06-28 2017-08-02 Интел Корпорейшн Defect-free device manufacturing on the basis of rib in cross epitaxial overgrowth area
TWI530992B (en) * 2013-09-30 2016-04-21 華亞科技股份有限公司 Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same
US9508719B2 (en) 2014-11-26 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same
TWI638385B (en) * 2015-03-31 2018-10-11 聯華電子股份有限公司 Patterned sttructure of a semiconductor device and a manufacturing method thereof
US9548243B1 (en) * 2015-06-30 2017-01-17 International Business Machines Corporation Self aligned via and pillar cut for at least a self aligned double pitch
US10388644B2 (en) * 2016-11-29 2019-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing conductors and semiconductor device which includes conductors
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
US11189712B2 (en) 2019-08-22 2021-11-30 International Business Machines Corporation Formation of vertical transport field-effect transistor structure having increased effective width
CN114420694A (en) * 2020-06-19 2022-04-29 福建省晋华集成电路有限公司 Semiconductor memory
KR20220005723A (en) * 2020-07-07 2022-01-14 주식회사 프로텍 Method of Bonding Copper Pillar to PCB Using Mask

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4408764A1 (en) * 1993-03-15 1994-09-22 Toshiba Kawasaki Kk Semiconductor arrangement
US6844591B1 (en) * 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
GB2404083A (en) * 2003-07-14 2005-01-19 Samsung Electronics Co Ltd Integrated semiconductor device with recessed gate electrode
DE10361695B3 (en) * 2003-12-30 2005-02-03 Infineon Technologies Ag Transistor structure for dynamic random-access memory cell has recess structure between source/drain regions and vertical gate electrode enclosing active region on at least 2 sides
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors

Family Cites Families (209)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4419809A (en) 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
DE3242113A1 (en) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart METHOD FOR PRODUCING A THIN DIELECTRIC INSULATION IN A SILICON SEMICONDUCTOR BODY
US4716131A (en) 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4570325A (en) * 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
US4984039A (en) * 1985-05-03 1991-01-08 Texas Instruments Incorporated Tapered trench structure and process
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
GB8528967D0 (en) 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
US5514885A (en) * 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4838991A (en) * 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US4776922A (en) * 1987-10-30 1988-10-11 International Business Machines Corporation Formation of variable-width sidewall structures
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5053105A (en) 1990-07-19 1991-10-01 Micron Technology, Inc. Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
DE4034612A1 (en) 1990-10-31 1992-05-07 Huels Chemische Werke Ag METHOD FOR PRODUCING ORGANOSILANES CONTAINING METHACRYLOXY OR ACRYLOXY GROUPS
IT1243919B (en) 1990-11-20 1994-06-28 Cons Ric Microelettronica PROCEDURE FOR OBTAINING PLANARIZED SUBMICHROMETRIC GROOVES IN INTEGRATED CIRCUITS REALIZED WITH ULSI TECHNOLOGY
GB9105767D0 (en) * 1991-03-19 1991-11-06 British Aerospace Wing root design of forward swept wings
US5208172A (en) 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
US5315142A (en) * 1992-03-23 1994-05-24 International Business Machines Corporation High performance trench EEPROM cell
JPH05343370A (en) 1992-06-10 1993-12-24 Toshiba Corp Forming method for fine pattern
US5330879A (en) * 1992-07-16 1994-07-19 Micron Technology, Inc. Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
JPH0677480A (en) * 1992-08-24 1994-03-18 Hitachi Ltd Semiconductor device
US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
DE4236609A1 (en) 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
US5407785A (en) 1992-12-18 1995-04-18 Vlsi Technology, Inc. Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures
US5470661A (en) 1993-01-07 1995-11-28 International Business Machines Corporation Diamond-like carbon films from a hydrocarbon helium plasma
JPH06318680A (en) * 1993-05-10 1994-11-15 Nec Corp Semiconductor storage device and its manufacture
US6042998A (en) * 1993-09-30 2000-03-28 The University Of New Mexico Method and apparatus for extending spatial frequencies in photolithography images
KR970009054B1 (en) 1993-12-29 1997-06-03 현대전자산업 주식회사 Planar structured mos transistor device and its manufacturing method
JP3720064B2 (en) * 1994-01-20 2005-11-24 株式会社ルネサステクノロジ Semiconductor integrated circuit
JPH0855920A (en) 1994-08-15 1996-02-27 Toshiba Corp Manufacture of semiconductor device
JPH0855908A (en) 1994-08-17 1996-02-27 Toshiba Corp Semiconductor device
US5600153A (en) 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
KR100190757B1 (en) 1995-06-30 1999-06-01 김영환 Method of forming mosfet
JP3393286B2 (en) 1995-09-08 2003-04-07 ソニー株式会社 Pattern formation method
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JPH09293793A (en) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp Semiconductor device provided with thin film transistor and manufacture thereof
JP3164026B2 (en) * 1996-08-21 2001-05-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5989998A (en) * 1996-08-29 1999-11-23 Matsushita Electric Industrial Co., Ltd. Method of forming interlayer insulating film
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6395613B1 (en) 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
US5679591A (en) * 1996-12-16 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd Method of making raised-bitline contactless trenched flash memory cell
US6214727B1 (en) 1997-02-11 2001-04-10 Micron Technology, Inc. Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry
US5981333A (en) 1997-02-11 1999-11-09 Micron Technology, Inc. Methods of forming capacitors and DRAM arrays
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6288431B1 (en) * 1997-04-04 2001-09-11 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US6143476A (en) 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
DE59814170D1 (en) * 1997-12-17 2008-04-03 Qimonda Ag Memory cell arrangement and method for its production
US6291334B1 (en) * 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6004862A (en) 1998-01-20 1999-12-21 Advanced Micro Devices, Inc. Core array and periphery isolation technique
JP2975917B2 (en) * 1998-02-06 1999-11-10 株式会社半導体プロセス研究所 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6191444B1 (en) * 1998-09-03 2001-02-20 Micron Technology, Inc. Mini flash process and circuit
US6319782B1 (en) 1998-09-10 2001-11-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same
US6333866B1 (en) * 1998-09-28 2001-12-25 Texas Instruments Incorporated Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US6071789A (en) * 1998-11-10 2000-06-06 Vanguard International Semiconductor Corporation Method for simultaneously fabricating a DRAM capacitor and metal interconnections
DE19853268C2 (en) 1998-11-18 2002-04-11 Infineon Technologies Ag Field effect controlled transistor and method for its production
US6271141B2 (en) * 1999-03-23 2001-08-07 Micron Technology, Inc. Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines
US6211044B1 (en) * 1999-04-12 2001-04-03 Advanced Micro Devices Process for fabricating a semiconductor device component using a selective silicidation reaction
US6159801A (en) * 1999-04-26 2000-12-12 Taiwan Semiconductor Manufacturing Company Method to increase coupling ratio of source to floating gate in split-gate flash
US6110837A (en) 1999-04-28 2000-08-29 Worldwide Semiconductor Manufacturing Corp. Method for forming a hard mask of half critical dimension
US6136662A (en) * 1999-05-13 2000-10-24 Lsi Logic Corporation Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
DE19928781C1 (en) 1999-06-23 2000-07-06 Siemens Ag DRAM cell array has deep word line trenches for increasing transistor channel length and has no fixed potential word lines separating adjacent memory cells
JP2001077196A (en) 1999-09-08 2001-03-23 Sony Corp Manufacture of semiconductor device
US6282113B1 (en) * 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
US6362057B1 (en) * 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
US6582891B1 (en) * 1999-12-02 2003-06-24 Axcelis Technologies, Inc. Process for reducing edge roughness in patterned photoresist
JP2001175073A (en) * 1999-12-14 2001-06-29 Canon Inc Developer carrier, developing device, processing cartridge and image forming device
KR100311050B1 (en) 1999-12-14 2001-11-05 윤종용 Method for manufacturing electrode of capacitor
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6967140B2 (en) 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6297554B1 (en) * 2000-03-10 2001-10-02 United Microelectronics Corp. Dual damascene interconnect structure with reduced parasitic capacitance
US6423474B1 (en) * 2000-03-21 2002-07-23 Micron Technology, Inc. Use of DARC and BARC in flash memory processing
JP3805603B2 (en) 2000-05-29 2006-08-02 富士通株式会社 Semiconductor device and manufacturing method thereof
US6431887B1 (en) 2000-05-31 2002-08-13 Tyco Electronics Corporation Electrical connector assembly with an EMI shielded plug and grounding latch member
US6632741B1 (en) * 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
US6455372B1 (en) * 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics
US6348380B1 (en) * 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
SE517275C2 (en) 2000-09-20 2002-05-21 Obducat Ab Wet etching of substrate involves arranging on the substrate a passivating substance comprising active substance reacting with component contained in etchant to form etch protecting compound
US6335257B1 (en) 2000-09-29 2002-01-01 Vanguard International Semiconductor Corporation Method of making pillar-type structure on semiconductor substrate
US6340614B1 (en) * 2000-10-03 2002-01-22 Vanguard International Semiconductor Corporation Method of forming a DRAM cell
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US6667237B1 (en) 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
JP2002124585A (en) * 2000-10-17 2002-04-26 Hitachi Ltd Nonvolatile semiconductor memory device and production method therefor
US6534243B1 (en) 2000-10-23 2003-03-18 Advanced Micro Devices, Inc. Chemical feature doubling process
US6926843B2 (en) * 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US6664028B2 (en) * 2000-12-04 2003-12-16 United Microelectronics Corp. Method of forming opening in wafer layer
JP2002203913A (en) * 2000-12-28 2002-07-19 Hitachi Ltd Semiconductor storage device and method of manufacturing the same
US6531727B2 (en) * 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6424001B1 (en) * 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US6545904B2 (en) * 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
US7176109B2 (en) * 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
US6475867B1 (en) 2001-04-02 2002-11-05 Advanced Micro Devices, Inc. Method of forming integrated circuit features by oxidation of titanium hard mask
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6740594B2 (en) 2001-05-31 2004-05-25 Infineon Technologies Ag Method for removing carbon-containing polysilane from a semiconductor without stripping
US6960806B2 (en) 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
US6737333B2 (en) * 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003031686A (en) * 2001-07-16 2003-01-31 Sony Corp Semiconductor storage device and its manufacturing method
US6522584B1 (en) * 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6599684B2 (en) * 2001-08-13 2003-07-29 Eastman Kodak Company Color photothermographic element comprising a dye-forming system for forming a novel infrared dye
US6744094B2 (en) * 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
TW497138B (en) * 2001-08-28 2002-08-01 Winbond Electronics Corp Method for improving consistency of critical dimension
DE10142590A1 (en) * 2001-08-31 2003-04-03 Infineon Technologies Ag Production of resist structures used in semiconductor industry comprises applying a resist film on a substrate, forming a resist structure with bars from the film, and removing reinforced sections
JP2003133437A (en) * 2001-10-24 2003-05-09 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2003168749A (en) * 2001-12-03 2003-06-13 Hitachi Ltd Non-volatile semiconductor memory device and manufacturing method thereof
US7226853B2 (en) * 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure
TW576864B (en) 2001-12-28 2004-02-21 Toshiba Corp Method for manufacturing a light-emitting device
US6638441B2 (en) * 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
DE10207131B4 (en) * 2002-02-20 2007-12-20 Infineon Technologies Ag Process for forming a hardmask in a layer on a flat disk
US6759180B2 (en) 2002-04-23 2004-07-06 Hewlett-Packard Development Company, L.P. Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography
US6806123B2 (en) 2002-04-26 2004-10-19 Micron Technology, Inc. Methods of forming isolation regions associated with semiconductor constructions
US20030207584A1 (en) 2002-05-01 2003-11-06 Swaminathan Sivakumar Patterning tighter and looser pitch geometries
US6951709B2 (en) * 2002-05-03 2005-10-04 Micron Technology, Inc. Method of fabricating a semiconductor multilevel interconnect structure
US6602779B1 (en) * 2002-05-13 2003-08-05 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6900521B2 (en) * 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
US6734107B2 (en) * 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6559017B1 (en) 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
US6777725B2 (en) * 2002-06-14 2004-08-17 Ingentix Gmbh & Co. Kg NROM memory circuit with recessed bitline
KR100476924B1 (en) 2002-06-14 2005-03-17 삼성전자주식회사 Method Of Forming Fine Pattern Of Semiconductor Device
US6924191B2 (en) * 2002-06-20 2005-08-02 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor
US20030235076A1 (en) 2002-06-21 2003-12-25 Micron Technology, Inc. Multistate NROM having a storage density much greater than 1 Bit per 1F2
AU2003280498A1 (en) 2002-06-27 2004-01-19 Advanced Micro Devices, Inc. Method of defining the dimensions of circuit elements by using spacer deposition techniques
US6689695B1 (en) * 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US6835663B2 (en) 2002-06-28 2004-12-28 Infineon Technologies Ag Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
US6734063B2 (en) * 2002-07-22 2004-05-11 Infineon Technologies Ag Non-volatile memory cell and fabrication method
US20040018738A1 (en) 2002-07-22 2004-01-29 Wei Liu Method for fabricating a notch gate structure of a field effect transistor
US6913871B2 (en) * 2002-07-23 2005-07-05 Intel Corporation Fabricating sub-resolution structures in planar lightwave devices
US6673684B1 (en) * 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6764949B2 (en) * 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6939808B2 (en) * 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
US7071043B2 (en) * 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6888187B2 (en) * 2002-08-26 2005-05-03 International Business Machines Corporation DRAM cell with enhanced SER immunity
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US7205598B2 (en) 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
US6794699B2 (en) 2002-08-29 2004-09-21 Micron Technology Inc Annular gate and technique for fabricating an annular gate
US6756284B2 (en) * 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7119020B2 (en) 2002-12-04 2006-10-10 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US6686245B1 (en) * 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
JP2004214379A (en) * 2002-12-27 2004-07-29 Toshiba Corp Semiconductor device, method for manufacturing the same dynamic type semiconductor storage device,
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
DE10306281B4 (en) * 2003-02-14 2007-02-15 Infineon Technologies Ag Arrangement and method for the production of vertical transistor cells and transistor-controlled memory cells
US7084076B2 (en) 2003-02-27 2006-08-01 Samsung Electronics, Co., Ltd. Method for forming silicon dioxide film using siloxane
US7015124B1 (en) 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) * 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
JP4578785B2 (en) 2003-05-21 2010-11-10 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6835662B1 (en) 2003-07-14 2004-12-28 Advanced Micro Devices, Inc. Partially de-coupled core and periphery gate module process
DE10332725A1 (en) 2003-07-18 2005-02-24 Forschungszentrum Jülich GmbH Method for self-adjusting reduction of structures
US6972988B1 (en) 2003-08-08 2005-12-06 Micron Technology, Inc. State save-on-power-down using GMR non-volatile elements
US7105431B2 (en) * 2003-08-22 2006-09-12 Micron Technology, Inc. Masking methods
DE10345455A1 (en) 2003-09-30 2005-05-04 Infineon Technologies Ag Method for producing a hard mask and hard mask arrangement
KR100536801B1 (en) 2003-10-01 2005-12-14 동부아남반도체 주식회사 Semiconductor device and fabrication method thereof
US6867116B1 (en) 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
US6998332B2 (en) 2004-01-08 2006-02-14 International Business Machines Corporation Method of independent P and N gate length control of FET device made by sidewall image transfer technique
US6875703B1 (en) 2004-01-20 2005-04-05 International Business Machines Corporation Method for forming quadruple density sidewall image transfer (SIT) structures
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
US7064078B2 (en) 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
KR100577565B1 (en) * 2004-02-23 2006-05-08 삼성전자주식회사 and method for manufacturing fin Field Effect Transistor
US7030012B2 (en) * 2004-03-10 2006-04-18 International Business Machines Corporation Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM
WO2005094231A2 (en) 2004-03-19 2005-10-13 The Regents Of The University Of California Methods for fabrication of positional and compositionally controlled nanostructures on substrate
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7183205B2 (en) 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7473644B2 (en) 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
DE102004036461A1 (en) * 2004-07-28 2006-02-16 Infineon Technologies Ag Electronic data storage device for high read current
KR100704470B1 (en) 2004-07-29 2007-04-10 주식회사 하이닉스반도체 Method for fabrication of semiconductor device using amorphous carbon layer to sacrificial hard mask
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) * 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) * 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
KR100614651B1 (en) * 2004-10-11 2006-08-22 삼성전자주식회사 Apparatus And Method For Pattern Exposure, Photomask Used Therefor, Design Method For The Photomask, Illuminating System Therefor and Implementing Method For The Illuminating System
US7208379B2 (en) 2004-11-29 2007-04-24 Texas Instruments Incorporated Pitch multiplication process
KR100596795B1 (en) 2004-12-16 2006-07-05 주식회사 하이닉스반도체 Capacitor of semiconductor device and method for forming the same
US7323379B2 (en) 2005-02-03 2008-01-29 Mosys, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7431927B2 (en) * 2005-03-24 2008-10-07 Epitomics, Inc. TNFα-neutralizing antibodies
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
KR100640639B1 (en) 2005-04-19 2006-10-31 삼성전자주식회사 Semiconductor device having fine contact and method of manufacturing the same
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7547599B2 (en) 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US8716772B2 (en) * 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
US7476933B2 (en) * 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US20070210449A1 (en) 2006-03-07 2007-09-13 Dirk Caspary Memory device and an array of conductive lines and methods of making the same
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US8129289B2 (en) 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4408764A1 (en) * 1993-03-15 1994-09-22 Toshiba Kawasaki Kk Semiconductor arrangement
GB2404083A (en) * 2003-07-14 2005-01-19 Samsung Electronics Co Ltd Integrated semiconductor device with recessed gate electrode
US6844591B1 (en) * 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
DE10361695B3 (en) * 2003-12-30 2005-02-03 Infineon Technologies Ag Transistor structure for dynamic random-access memory cell has recess structure between source/drain regions and vertical gate electrode enclosing active region on at least 2 sides
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors
WO2006028777A1 (en) * 2004-09-01 2006-03-16 Micron Technology, Inc. Dram cells with vertical u-shaped transistors
EP1794791A1 (en) * 2004-09-01 2007-06-13 Micron Technology, Inc. Dram cells with vertical u-shaped transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9184161B2 (en) 2006-03-02 2015-11-10 Micron Technology, Inc. Vertical gated access transistor

Also Published As

Publication number Publication date
WO2007103147A2 (en) 2007-09-13
JP2009528701A (en) 2009-08-06
US9184161B2 (en) 2015-11-10
KR101364780B1 (en) 2014-02-21
EP2011147B1 (en) 2020-09-09
US20120049246A1 (en) 2012-03-01
US7736980B2 (en) 2010-06-15
US8592898B2 (en) 2013-11-26
JP5282888B2 (en) 2013-09-04
US20090104744A1 (en) 2009-04-23
KR20090003303A (en) 2009-01-09
CN101395714A (en) 2009-03-25
EP2011147A2 (en) 2009-01-07
CN101395714B (en) 2013-06-05
US7476933B2 (en) 2009-01-13
US20100230733A1 (en) 2010-09-16
US20140077295A1 (en) 2014-03-20
US8039348B2 (en) 2011-10-18
US20070205443A1 (en) 2007-09-06

Similar Documents

Publication Publication Date Title
WO2007103147A3 (en) U-shaped transistor and corresponding manufacturing method
WO2004107399A3 (en) Transistor with independant gate structures
TW200715566A (en) Display device and method of manufacturing the same
TW200614507A (en) Finfet transistor process
WO2007075996A3 (en) Apparatus and method for a fast recovery rectifier structure
TW200629422A (en) Method of manufacturing a capaciotr and a metal gate on a semiconductor device
WO2008042732A3 (en) Recessed sti for wide transistors
TW200725811A (en) A semiconductor device and method for making the same
TW200731415A (en) Methods for forming a semiconductor device
TW200711054A (en) A method of manufacturing a transistor and a method of forming a memory device
TW200644175A (en) Method for forming a semiconductor device
WO2003015173A3 (en) Floating gate memory array and methods of forming
SG131008A1 (en) Different sti depth for ron improvement for ldmos integration with submicron devices
WO2009063588A1 (en) Semiconductor device and method for manufacturing the same
WO2006104562A3 (en) Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
TW200802798A (en) Improved SOI substrates and SOI devices, and methods for forming the same
TW200741885A (en) Method of fabricating a recess channel array transistor
WO2007111771A3 (en) Method of forming field effect transistors and methods of forming integrated circuity comprising a transistor gate array and circuity peripheral to the gate array
TW200701371A (en) Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same
WO2011071598A3 (en) Quantum-well-based semiconductor devices
EP1873838A4 (en) Semiconductor device and method for manufacturing same
TW200635044A (en) Quasi-planar and finfet-like transistors on bulk silicon
WO2007146777A3 (en) Method of manufacturing gate sidewalls that avoids recessing
TW200642001A (en) A semiconductor device and fabrication thereof, a capacitor and fabrication thereof
TW200625608A (en) Non-volatile memory device and manufacturing method and operating method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07752033

Country of ref document: EP

Kind code of ref document: A2

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 200780007139.7

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2008557387

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087024116

Country of ref document: KR

Ref document number: 2007752033

Country of ref document: EP