WO2007103643A3 - Method and apparatus for thermal processing structures formed on a substrate - Google Patents

Method and apparatus for thermal processing structures formed on a substrate Download PDF

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Publication number
WO2007103643A3
WO2007103643A3 PCT/US2007/062672 US2007062672W WO2007103643A3 WO 2007103643 A3 WO2007103643 A3 WO 2007103643A3 US 2007062672 W US2007062672 W US 2007062672W WO 2007103643 A3 WO2007103643 A3 WO 2007103643A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
regions
processing steps
dopants
prior processing
Prior art date
Application number
PCT/US2007/062672
Other languages
French (fr)
Other versions
WO2007103643A2 (en
WO2007103643B1 (en
Inventor
Abhilash Mayur
Mark Yam
Ajit Balakrishna
Paul Carey
Dean Jennings
Stephen Moffatt
William Schaffer
Alexander N Lerner
Timothy N Thomas
Aaron Muir Hunter
Original Assignee
Applied Materials Inc
Abhilash Mayur
Mark Yam
Ajit Balakrishna
Paul Carey
Dean Jennings
Stephen Moffatt
William Schaffer
Alexander N Lerner
Timothy N Thomas
Aaron Muir Hunter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/459,856 external-priority patent/US20070212859A1/en
Application filed by Applied Materials Inc, Abhilash Mayur, Mark Yam, Ajit Balakrishna, Paul Carey, Dean Jennings, Stephen Moffatt, William Schaffer, Alexander N Lerner, Timothy N Thomas, Aaron Muir Hunter filed Critical Applied Materials Inc
Priority to CN2007800081420A priority Critical patent/CN101395712B/en
Priority to JP2008558449A priority patent/JP5558006B2/en
Priority to EP07757396A priority patent/EP1992013A2/en
Priority to KR1020087024646A priority patent/KR101113533B1/en
Priority to KR1020107024018A priority patent/KR101323222B1/en
Publication of WO2007103643A2 publication Critical patent/WO2007103643A2/en
Publication of WO2007103643A3 publication Critical patent/WO2007103643A3/en
Publication of WO2007103643B1 publication Critical patent/WO2007103643B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

The present invention generally describes one ore more apparatuses and various methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted damage created from prior processing steps, more evenly distribute dopants in various regions of the substrate, and/or activate various regions of the substrate. The preferential melting processes will allow more uniform distribution of the dopants in the melted region, due to the increased diffusion rate and solubility of the dopant atoms in the molten region of the substrate. The creation of a melted region thus allows: 1) the dopant atoms to redistribute more uniformly, 2) defects created in prior processing steps to be removed, and 3) regions that have hyper-abrupt dopant concentrations to be formed.
PCT/US2007/062672 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate WO2007103643A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2007800081420A CN101395712B (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate
JP2008558449A JP5558006B2 (en) 2006-03-08 2007-02-23 Method and apparatus for heat treatment structure formed on a substrate
EP07757396A EP1992013A2 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate
KR1020087024646A KR101113533B1 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate
KR1020107024018A KR101323222B1 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US78074506P 2006-03-08 2006-03-08
US60/780,745 2006-03-08
US11/459,852 2006-07-25
US11/459,856 US20070212859A1 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
US11/459,847 US7569463B2 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
US11/459,852 US20070221640A1 (en) 2006-03-08 2006-07-25 Apparatus for thermal processing structures formed on a substrate
US11/459,856 2006-07-25
US11/459,847 2006-07-25

Publications (3)

Publication Number Publication Date
WO2007103643A2 WO2007103643A2 (en) 2007-09-13
WO2007103643A3 true WO2007103643A3 (en) 2008-05-08
WO2007103643B1 WO2007103643B1 (en) 2008-06-26

Family

ID=38475646

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/062672 WO2007103643A2 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate

Country Status (4)

Country Link
EP (1) EP1992013A2 (en)
JP (1) JP5558006B2 (en)
KR (2) KR101113533B1 (en)
WO (1) WO2007103643A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9498845B2 (en) 2007-11-08 2016-11-22 Applied Materials, Inc. Pulse train annealing method and apparatus
US20090120924A1 (en) * 2007-11-08 2009-05-14 Stephen Moffatt Pulse train annealing method and apparatus
US9012315B2 (en) * 2013-08-09 2015-04-21 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
KR102216675B1 (en) * 2014-06-12 2021-02-18 삼성디스플레이 주식회사 Repairing apparatus for display apparatus and repairing method for disaplay apparatus
EP3611757A1 (en) * 2018-08-16 2020-02-19 Laser Systems & Solutions of Europe Method for forming a doped region on a semiconductor material

Citations (9)

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Publication number Priority date Publication date Assignee Title
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
EP0206764B1 (en) * 1985-06-21 1990-03-14 BRITISH TELECOMMUNICATIONS public limited company Fabrication of optical waveguides
US5182170A (en) * 1989-09-05 1993-01-26 Board Of Regents, The University Of Texas System Method of producing parts by selective beam interaction of powder with gas phase reactant
US20010039098A1 (en) * 2000-04-24 2001-11-08 Zhiheng Lu Method for fabricating silicon-on-insulator material
US20030138988A1 (en) * 1998-12-15 2003-07-24 Nec Corporation Method of manufacturing a solid-state imaging device
US20030146458A1 (en) * 2002-02-04 2003-08-07 Hitachi, Ltd. Semiconductor device and process for forming same
US20050139961A1 (en) * 2003-12-25 2005-06-30 Siltronic Ag Semiconductor substrate and method for production thereof
WO2005104265A1 (en) * 2004-04-27 2005-11-03 Koninklijke Philips Electronics, N.V. Method of forming an organic semiconducting device by a melt technique
US6982476B2 (en) * 2001-02-02 2006-01-03 Matrix Semiconductor Integrated circuit feature layout for improved chemical mechanical polishing

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JPS5696835A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Manufacture of semiconductor device
JPS5727035A (en) * 1980-07-25 1982-02-13 Hitachi Ltd Manufacture of semiconductor device
JP3326654B2 (en) * 1994-05-02 2002-09-24 ソニー株式会社 Method of manufacturing semiconductor chip for display
US5956603A (en) * 1998-08-27 1999-09-21 Ultratech Stepper, Inc. Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
KR100338768B1 (en) 1999-10-25 2002-05-30 윤종용 Method for removing oxide layer and semiconductor manufacture apparatus for removing oxide layer
US6902966B2 (en) * 2001-10-25 2005-06-07 Advanced Micro Devices, Inc. Low-temperature post-dopant activation process
WO2003046967A2 (en) * 2001-11-30 2003-06-05 Koninklijke Philips Electronics N.V. Method of forming a doped region in a semiconductor body comprising a step of amorphization by irradiation
US7154066B2 (en) 2002-11-06 2006-12-26 Ultratech, Inc. Laser scanning apparatus and methods for thermal processing
JP2004363355A (en) * 2003-06-05 2004-12-24 Hitachi Ltd Semiconductor device and method of manufacturing the same
US7098155B2 (en) 2003-09-29 2006-08-29 Ultratech, Inc. Laser thermal annealing of lightly doped silicon substrates
EP1524684B1 (en) * 2003-10-17 2010-01-13 Imec Method for providing a semiconductor substrate with a layer structure of activated dopants

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206764B1 (en) * 1985-06-21 1990-03-14 BRITISH TELECOMMUNICATIONS public limited company Fabrication of optical waveguides
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
US5182170A (en) * 1989-09-05 1993-01-26 Board Of Regents, The University Of Texas System Method of producing parts by selective beam interaction of powder with gas phase reactant
US20030138988A1 (en) * 1998-12-15 2003-07-24 Nec Corporation Method of manufacturing a solid-state imaging device
US20010039098A1 (en) * 2000-04-24 2001-11-08 Zhiheng Lu Method for fabricating silicon-on-insulator material
US6982476B2 (en) * 2001-02-02 2006-01-03 Matrix Semiconductor Integrated circuit feature layout for improved chemical mechanical polishing
US20030146458A1 (en) * 2002-02-04 2003-08-07 Hitachi, Ltd. Semiconductor device and process for forming same
US20050139961A1 (en) * 2003-12-25 2005-06-30 Siltronic Ag Semiconductor substrate and method for production thereof
WO2005104265A1 (en) * 2004-04-27 2005-11-03 Koninklijke Philips Electronics, N.V. Method of forming an organic semiconducting device by a melt technique

Also Published As

Publication number Publication date
JP2009529245A (en) 2009-08-13
EP1992013A2 (en) 2008-11-19
KR20100133454A (en) 2010-12-21
KR101323222B1 (en) 2013-10-30
KR20080104183A (en) 2008-12-01
KR101113533B1 (en) 2012-02-29
WO2007103643A2 (en) 2007-09-13
WO2007103643B1 (en) 2008-06-26
JP5558006B2 (en) 2014-07-23

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