WO2007109133B1 - Improved chip-scale package - Google Patents

Improved chip-scale package

Info

Publication number
WO2007109133B1
WO2007109133B1 PCT/US2007/006633 US2007006633W WO2007109133B1 WO 2007109133 B1 WO2007109133 B1 WO 2007109133B1 US 2007006633 W US2007006633 W US 2007006633W WO 2007109133 B1 WO2007109133 B1 WO 2007109133B1
Authority
WO
WIPO (PCT)
Prior art keywords
passivation
package
die
power electrode
package according
Prior art date
Application number
PCT/US2007/006633
Other languages
French (fr)
Other versions
WO2007109133A3 (en
WO2007109133A2 (en
Inventor
Martin Standing
Original Assignee
Int Rectifier Corp
Martin Standing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Rectifier Corp, Martin Standing filed Critical Int Rectifier Corp
Priority to JP2009500503A priority Critical patent/JP4977753B2/en
Priority to EP07753274A priority patent/EP2008304A4/en
Publication of WO2007109133A2 publication Critical patent/WO2007109133A2/en
Publication of WO2007109133A3 publication Critical patent/WO2007109133A3/en
Publication of WO2007109133B1 publication Critical patent/WO2007109133B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
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    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A power semiconductor package that includes a die having one electrode thereof electrically and mechanically attached to a web portion of a conductive clip.

Claims

AMENDED CLAIMS received by the International Bureau on 01 April 2008 (01.04.2008)WHAT TS CLAIMBD IS:
1. A semiconductor package comprising: a conductive clip having a web portion; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; a passivation body formed over at least said second power electrode; and a solder body on said second power electrode and extending beyond said passivation body, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion,
2. The package of claim 1, wherein said solder body is comprised of a lead free solder.
3- The package of claim 1, wherein said solder body is comprised of SnAgCu.
4. The package of claim 1, wherein said solder body is comprised of SnSb.
5. Canceled
6. The package of claim 1, wherein said passivation body includes a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
7. A package according to claim 6, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
S. A package according to claim 6, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy. 14
9. A package according to claim 6, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and MIy covers said flange portion.
10. A package according to claim 1, wherein said conductive clip includes two opposing rail portions each including a plurality of bumps.
11. A package according to claim 1 , wherein said die further includes a control electrode adjacent said second power electrode.
12. A package according claim I5 wherein said die is a power MOSFET.
13. A semiconductor package comprising: a conductive clip having a web portion; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; and a passivation body formed over at least said second power electrode, said passivation body including an opening exposing said second power electrode, and having a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
14. A package according to claim 13, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
15. A package according to claim 13, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy.
16. A package according to claim 13, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion, 15
17. A package according to claim 13, wherein said conductive clip includes two opposing rail portions each including a plurality of bumps.
IS. A package according to claim 13, wherein said die further includes a control electrode adjacent said second power electrode.
19. A package according to claim 13, wherein said die is a power MOSFET.
20. A package according to claim 13, further comprising a solder body on said second power electrode and extending beyond said passivation body.
21. A package according to claim 20, wherein said solder body is comprised of a lead free solder.
22. A package according to claim 20, wherein said solder body is comprised of SnAgCu.
23. A package according to claim 20, wherein said solder body is comprised of SnSb.
24. A package according to claim 13, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion.
25. A semiconductor package comprising: a conductive clip having a web portion, and two opposing rail portions each rail including a plurality of bumps; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; and a passivation body formed over at least said second power electrode; wherein said second power electrode is configured for connection to a conductive pad on a support body by a conductive adhesive, and said bumps are configured to space said passivation body from said support body to provide a clearance between said passivation body and said support body. 16
26. The package of claim 25, wherein said clearance is up to 175 μm.
27. The package of claim 25, further comprising a solder body on said second power electrode and extending beyond said passivation body.
28. The package of claim 27, wherein said solder body is comprised of a lead free solder.
29. The package of claim 28, wherein said solder body is comprised of SnAgCu.
30. The package of claim 28, wherein said solder body is comprised of SnSb.
31. The package of claim 25, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion.
32. The package of claim 25, wherein said passivation body includes a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
33. The package of claim 32, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
34. The package of claim 32, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy.
35. The package of claim 25, wherein said die further includes a control electrode adjacent said second power electrode.
36. The package of claim 25, wherein said die is a power MOSFET.
PCT/US2007/006633 2006-03-17 2007-03-16 Improved chip-scale package WO2007109133A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009500503A JP4977753B2 (en) 2006-03-17 2007-03-16 Improved chip scale package
EP07753274A EP2008304A4 (en) 2006-03-17 2007-03-16 Improved chip-scale package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/378,607 US20070215997A1 (en) 2006-03-17 2006-03-17 Chip-scale package
US11/378,607 2006-03-17

Publications (3)

Publication Number Publication Date
WO2007109133A2 WO2007109133A2 (en) 2007-09-27
WO2007109133A3 WO2007109133A3 (en) 2008-04-03
WO2007109133B1 true WO2007109133B1 (en) 2008-07-31

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PCT/US2007/006633 WO2007109133A2 (en) 2006-03-17 2007-03-16 Improved chip-scale package

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US (1) US20070215997A1 (en)
EP (1) EP2008304A4 (en)
JP (1) JP4977753B2 (en)
TW (1) TWI341013B (en)
WO (1) WO2007109133A2 (en)

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US7982309B2 (en) * 2007-02-13 2011-07-19 Infineon Technologies Ag Integrated circuit including gas phase deposited packaging material
WO2017002368A1 (en) * 2015-07-01 2017-01-05 パナソニックIpマネジメント株式会社 Semiconductor device
US9966341B1 (en) 2016-10-31 2018-05-08 Infineon Technologies Americas Corp. Input/output pins for chip-embedded substrate

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US20070215997A1 (en) 2007-09-20
JP2009530826A (en) 2009-08-27
EP2008304A2 (en) 2008-12-31
WO2007109133A3 (en) 2008-04-03
TW200741990A (en) 2007-11-01
EP2008304A4 (en) 2011-03-23
WO2007109133A2 (en) 2007-09-27
TWI341013B (en) 2011-04-21
JP4977753B2 (en) 2012-07-18

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