WO2007109133B1 - Improved chip-scale package - Google Patents
Improved chip-scale packageInfo
- Publication number
- WO2007109133B1 WO2007109133B1 PCT/US2007/006633 US2007006633W WO2007109133B1 WO 2007109133 B1 WO2007109133 B1 WO 2007109133B1 US 2007006633 W US2007006633 W US 2007006633W WO 2007109133 B1 WO2007109133 B1 WO 2007109133B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- passivation
- package
- die
- power electrode
- package according
- Prior art date
Links
Classifications
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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Abstract
A power semiconductor package that includes a die having one electrode thereof electrically and mechanically attached to a web portion of a conductive clip.
Claims
1. A semiconductor package comprising: a conductive clip having a web portion; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; a passivation body formed over at least said second power electrode; and a solder body on said second power electrode and extending beyond said passivation body, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion,
2. The package of claim 1, wherein said solder body is comprised of a lead free solder.
3- The package of claim 1, wherein said solder body is comprised of SnAgCu.
4. The package of claim 1, wherein said solder body is comprised of SnSb.
5. Canceled
6. The package of claim 1, wherein said passivation body includes a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
7. A package according to claim 6, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
S. A package according to claim 6, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy. 14
9. A package according to claim 6, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and MIy covers said flange portion.
10. A package according to claim 1, wherein said conductive clip includes two opposing rail portions each including a plurality of bumps.
11. A package according to claim 1 , wherein said die further includes a control electrode adjacent said second power electrode.
12. A package according claim I5 wherein said die is a power MOSFET.
13. A semiconductor package comprising: a conductive clip having a web portion; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; and a passivation body formed over at least said second power electrode, said passivation body including an opening exposing said second power electrode, and having a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
14. A package according to claim 13, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
15. A package according to claim 13, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy.
16. A package according to claim 13, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion, 15
17. A package according to claim 13, wherein said conductive clip includes two opposing rail portions each including a plurality of bumps.
IS. A package according to claim 13, wherein said die further includes a control electrode adjacent said second power electrode.
19. A package according to claim 13, wherein said die is a power MOSFET.
20. A package according to claim 13, further comprising a solder body on said second power electrode and extending beyond said passivation body.
21. A package according to claim 20, wherein said solder body is comprised of a lead free solder.
22. A package according to claim 20, wherein said solder body is comprised of SnAgCu.
23. A package according to claim 20, wherein said solder body is comprised of SnSb.
24. A package according to claim 13, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion.
25. A semiconductor package comprising: a conductive clip having a web portion, and two opposing rail portions each rail including a plurality of bumps; a semiconductor die having a first power electrode electrically and mechanically connected to said web portion, and a second power electrode opposite said first power electrode; and a passivation body formed over at least said second power electrode; wherein said second power electrode is configured for connection to a conductive pad on a support body by a conductive adhesive, and said bumps are configured to space said passivation body from said support body to provide a clearance between said passivation body and said support body. 16
26. The package of claim 25, wherein said clearance is up to 175 μm.
27. The package of claim 25, further comprising a solder body on said second power electrode and extending beyond said passivation body.
28. The package of claim 27, wherein said solder body is comprised of a lead free solder.
29. The package of claim 28, wherein said solder body is comprised of SnAgCu.
30. The package of claim 28, wherein said solder body is comprised of SnSb.
31. The package of claim 25, wherein said clip includes a wall spaced from and surrounding said die, said wall including a flange portion, wherein said passivation body resides within said space between said die and said wall and fully covers said flange portion.
32. The package of claim 25, wherein said passivation body includes a first passivation layer comprised of a first passivation material and a second passivation layer comprised of a second passivation material.
33. The package of claim 32, wherein said first passivation material is a carbon based polymer and said second passivation material is a silicon based polymer.
34. The package of claim 32, wherein said first passivation material is a carbon based epoxy and said second passivation material is a silicon based epoxy.
35. The package of claim 25, wherein said die further includes a control electrode adjacent said second power electrode.
36. The package of claim 25, wherein said die is a power MOSFET.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009500503A JP4977753B2 (en) | 2006-03-17 | 2007-03-16 | Improved chip scale package |
EP07753274A EP2008304A4 (en) | 2006-03-17 | 2007-03-16 | Improved chip-scale package |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/378,607 US20070215997A1 (en) | 2006-03-17 | 2006-03-17 | Chip-scale package |
US11/378,607 | 2006-03-17 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2007109133A2 WO2007109133A2 (en) | 2007-09-27 |
WO2007109133A3 WO2007109133A3 (en) | 2008-04-03 |
WO2007109133B1 true WO2007109133B1 (en) | 2008-07-31 |
Family
ID=38516940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/006633 WO2007109133A2 (en) | 2006-03-17 | 2007-03-16 | Improved chip-scale package |
Country Status (5)
Country | Link |
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US (1) | US20070215997A1 (en) |
EP (1) | EP2008304A4 (en) |
JP (1) | JP4977753B2 (en) |
TW (1) | TWI341013B (en) |
WO (1) | WO2007109133A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005061015B4 (en) * | 2005-12-19 | 2008-03-13 | Infineon Technologies Ag | A method of manufacturing a semiconductor device having a vertical semiconductor device |
US7982309B2 (en) * | 2007-02-13 | 2011-07-19 | Infineon Technologies Ag | Integrated circuit including gas phase deposited packaging material |
WO2017002368A1 (en) * | 2015-07-01 | 2017-01-05 | パナソニックIpマネジメント株式会社 | Semiconductor device |
US9966341B1 (en) | 2016-10-31 | 2018-05-08 | Infineon Technologies Americas Corp. | Input/output pins for chip-embedded substrate |
Family Cites Families (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS482463U (en) * | 1971-05-21 | 1973-01-12 | ||
US3972062A (en) * | 1973-10-04 | 1976-07-27 | Motorola, Inc. | Mounting assemblies for a plurality of transistor integrated circuit chips |
JPS629722Y2 (en) * | 1981-01-13 | 1987-03-06 | ||
JPS6184041A (en) * | 1984-10-02 | 1986-04-28 | Fujitsu Ltd | Semiconductor device |
DE3521572A1 (en) * | 1985-06-15 | 1986-12-18 | Brown, Boveri & Cie Ag, 6800 Mannheim | PERFORMANCE SEMICONDUCTOR MODULE WITH CERAMIC SUBSTRATE |
JP2702131B2 (en) * | 1987-06-12 | 1998-01-21 | キヤノン株式会社 | Image reading apparatus and image information reading apparatus having the same |
US4976813A (en) * | 1988-07-01 | 1990-12-11 | Amoco Corporation | Process for using a composition for a solder mask |
US4901135A (en) * | 1988-08-15 | 1990-02-13 | General Electric Company | Hermetically sealed housing with welding seal |
US5108825A (en) * | 1989-12-21 | 1992-04-28 | General Electric Company | Epoxy/polyimide copolymer blend dielectric and layered circuits incorporating it |
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
US5139972A (en) * | 1991-02-28 | 1992-08-18 | General Electric Company | Batch assembly of high density hermetic packages for power semiconductor chips |
JP3258764B2 (en) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same |
FR2709021B1 (en) * | 1993-08-09 | 1995-10-27 | Sgs Thomson Microelectronics | Heat sink for plastic housing. |
US5446316A (en) * | 1994-01-06 | 1995-08-29 | Harris Corporation | Hermetic package for a high power semiconductor device |
US6359335B1 (en) * | 1994-05-19 | 2002-03-19 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
US5688716A (en) * | 1994-07-07 | 1997-11-18 | Tessera, Inc. | Fan-out semiconductor chip assembly |
US5629835A (en) * | 1994-07-19 | 1997-05-13 | Olin Corporation | Metal ball grid array package with improved thermal conductivity |
US5572070A (en) * | 1995-02-06 | 1996-11-05 | Rjr Polymers, Inc. | Integrated circuit packages with heat dissipation for high current load |
US5818699A (en) * | 1995-07-05 | 1998-10-06 | Kabushiki Kaisha Toshiba | Multi-chip module and production method thereof |
DE69616186T2 (en) * | 1995-07-19 | 2002-07-11 | Raytheon Co | Epoxy adhesive with thermal conductivity that is stable and flexible at room temperature |
JPH09293754A (en) * | 1996-04-24 | 1997-11-11 | Canon Inc | Electric circuit part, manufacture thereof, conductive ball, conductive connection member, and manufacture thereof |
US5949654A (en) * | 1996-07-03 | 1999-09-07 | Kabushiki Kaisha Toshiba | Multi-chip module, an electronic device, and production method thereof |
US6075289A (en) * | 1996-10-24 | 2000-06-13 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
US6011304A (en) * | 1997-05-05 | 2000-01-04 | Lsi Logic Corporation | Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid |
US5893726A (en) * | 1997-12-15 | 1999-04-13 | Micron Technology, Inc. | Semiconductor package with pre-fabricated cover and method of fabrication |
JPH11354680A (en) * | 1998-06-11 | 1999-12-24 | Sony Corp | Printed wiring board and semiconductor package using the same |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
EP0978871A3 (en) * | 1998-08-05 | 2001-12-19 | Harris Corporation | A low power packaging design |
JP3895884B2 (en) * | 1999-03-25 | 2007-03-22 | 三洋電機株式会社 | Semiconductor device |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US20020016070A1 (en) * | 2000-04-05 | 2002-02-07 | Gerald Friese | Power pads for application of high current per bond pad in silicon technology |
US7119447B2 (en) * | 2001-03-28 | 2006-10-10 | International Rectifier Corporation | Direct fet device for high frequency application |
US6930397B2 (en) * | 2001-03-28 | 2005-08-16 | International Rectifier Corporation | Surface mounted package with die bottom spaced from support board |
USD503691S1 (en) * | 2001-03-28 | 2005-04-05 | International Rectifier Corporation | Conductive clip for a semiconductor package |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
US7476964B2 (en) * | 2001-06-18 | 2009-01-13 | International Rectifier Corporation | High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing |
JP3868777B2 (en) * | 2001-09-11 | 2007-01-17 | 株式会社東芝 | Semiconductor device |
US6784540B2 (en) * | 2001-10-10 | 2004-08-31 | International Rectifier Corp. | Semiconductor device package with improved cooling |
TW517365B (en) * | 2001-11-29 | 2003-01-11 | Orient Semiconductor Elect Ltd | Heat dissipation plate and its bonding process with substrate |
JP3897596B2 (en) * | 2002-01-07 | 2007-03-28 | 日本テキサス・インスツルメンツ株式会社 | Mounted body of semiconductor device and wiring board |
US20030131975A1 (en) * | 2002-01-11 | 2003-07-17 | Sabina Houle | Integrated heat spreader with mechanical interlock designs |
US6677669B2 (en) * | 2002-01-18 | 2004-01-13 | International Rectifier Corporation | Semiconductor package including two semiconductor die disposed within a common clip |
US6841865B2 (en) * | 2002-11-22 | 2005-01-11 | International Rectifier Corporation | Semiconductor device having clips for connecting to external elements |
US7088004B2 (en) * | 2002-11-27 | 2006-08-08 | International Rectifier Corporation | Flip-chip device having conductive connectors |
US6896976B2 (en) * | 2003-04-09 | 2005-05-24 | International Rectifier Corporation | Tin antimony solder for MOSFET with TiNiAg back metal |
US7443693B2 (en) * | 2003-04-15 | 2008-10-28 | Wavezero, Inc. | Electromagnetic interference shielding for a printed circuit board |
US8368223B2 (en) * | 2003-10-24 | 2013-02-05 | International Rectifier Corporation | Paste for forming an interconnect and interconnect formed from the paste |
US7315081B2 (en) * | 2003-10-24 | 2008-01-01 | International Rectifier Corporation | Semiconductor device package utilizing proud interconnect material |
JP4312616B2 (en) * | 2004-01-26 | 2009-08-12 | Necエレクトロニクス株式会社 | Semiconductor device |
US8368211B2 (en) * | 2004-03-11 | 2013-02-05 | International Rectifier Corporation | Solderable top metalization and passivation for source mounted package |
US20050269677A1 (en) * | 2004-05-28 | 2005-12-08 | Martin Standing | Preparation of front contact for surface mounting |
US7678680B2 (en) * | 2004-06-03 | 2010-03-16 | International Rectifier Corporation | Semiconductor device with reduced contact resistance |
DE102004030042B4 (en) * | 2004-06-22 | 2009-04-02 | Infineon Technologies Ag | Semiconductor device having a semiconductor chip mounted on a carrier, in which the heat transferred from the semiconductor chip to the carrier is limited, and a method for producing a semiconductor device |
US7235877B2 (en) * | 2004-09-23 | 2007-06-26 | International Rectifier Corporation | Redistributed solder pads using etched lead frame |
US7692316B2 (en) * | 2004-10-01 | 2010-04-06 | International Rectifier Corporation | Audio amplifier assembly |
JP2006222298A (en) * | 2005-02-10 | 2006-08-24 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
US7476976B2 (en) * | 2005-02-23 | 2009-01-13 | Texas Instruments Incorporated | Flip chip package with advanced electrical and thermal properties for high current designs |
TWI304234B (en) * | 2005-03-04 | 2008-12-11 | Int Rectifier Corp | Semiconductor package fabrication |
US20060270106A1 (en) * | 2005-05-31 | 2006-11-30 | Tz-Cheng Chiu | System and method for polymer encapsulated solder lid attach |
US7365981B2 (en) * | 2005-06-28 | 2008-04-29 | Delphi Technologies, Inc. | Fluid-cooled electronic system |
US8143729B2 (en) * | 2008-01-25 | 2012-03-27 | International Rectifier Corporation | Autoclave capable chip-scale package |
-
2006
- 2006-03-17 US US11/378,607 patent/US20070215997A1/en not_active Abandoned
-
2007
- 2007-03-16 WO PCT/US2007/006633 patent/WO2007109133A2/en active Application Filing
- 2007-03-16 JP JP2009500503A patent/JP4977753B2/en active Active
- 2007-03-16 EP EP07753274A patent/EP2008304A4/en not_active Withdrawn
- 2007-03-19 TW TW096109330A patent/TWI341013B/en not_active IP Right Cessation
Also Published As
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US20070215997A1 (en) | 2007-09-20 |
JP2009530826A (en) | 2009-08-27 |
EP2008304A2 (en) | 2008-12-31 |
WO2007109133A3 (en) | 2008-04-03 |
TW200741990A (en) | 2007-11-01 |
EP2008304A4 (en) | 2011-03-23 |
WO2007109133A2 (en) | 2007-09-27 |
TWI341013B (en) | 2011-04-21 |
JP4977753B2 (en) | 2012-07-18 |
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