WO2007112066A3 - Lattice-mismatched semiconductor structures and related methods for device fabrication - Google Patents

Lattice-mismatched semiconductor structures and related methods for device fabrication Download PDF

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Publication number
WO2007112066A3
WO2007112066A3 PCT/US2007/007373 US2007007373W WO2007112066A3 WO 2007112066 A3 WO2007112066 A3 WO 2007112066A3 US 2007007373 W US2007007373 W US 2007007373W WO 2007112066 A3 WO2007112066 A3 WO 2007112066A3
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WO
WIPO (PCT)
Prior art keywords
lattice
related methods
device fabrication
semiconductor structures
mismatched semiconductor
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PCT/US2007/007373
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French (fr)
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WO2007112066A2 (en
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Anthony J Lochtefeld
Matthew T Currie
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Amberwave Systems Corp
Anthony J Lochtefeld
Matthew T Currie
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Application filed by Amberwave Systems Corp, Anthony J Lochtefeld, Matthew T Currie filed Critical Amberwave Systems Corp
Publication of WO2007112066A2 publication Critical patent/WO2007112066A2/en
Publication of WO2007112066A3 publication Critical patent/WO2007112066A3/en

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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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Abstract

Lattice-mismatched materials having configurations that trap defects within sidewall- containing structures.
PCT/US2007/007373 2006-03-24 2007-03-23 Lattice-mismatched semiconductor structures and related methods for device fabrication WO2007112066A2 (en)

Applications Claiming Priority (2)

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US78556706P 2006-03-24 2006-03-24
US60/785,567 2006-03-24

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WO2007112066A3 true WO2007112066A3 (en) 2007-11-29

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Cited By (1)

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US8878243B2 (en) 2014-11-04

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