WO2007130615A3 - A method for reading a multilevel cell in a non-volatile memory device - Google Patents

A method for reading a multilevel cell in a non-volatile memory device Download PDF

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Publication number
WO2007130615A3
WO2007130615A3 PCT/US2007/010904 US2007010904W WO2007130615A3 WO 2007130615 A3 WO2007130615 A3 WO 2007130615A3 US 2007010904 W US2007010904 W US 2007010904W WO 2007130615 A3 WO2007130615 A3 WO 2007130615A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
data
cell
reading
volatile memory
Prior art date
Application number
PCT/US2007/010904
Other languages
French (fr)
Other versions
WO2007130615A2 (en
Inventor
Chang Wan Ha
Original Assignee
Micron Technology Inc
Chang Wan Ha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Chang Wan Ha filed Critical Micron Technology Inc
Priority to CN2007800157148A priority Critical patent/CN101432819B/en
Publication of WO2007130615A2 publication Critical patent/WO2007130615A2/en
Publication of WO2007130615A3 publication Critical patent/WO2007130615A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.
PCT/US2007/010904 2006-05-04 2007-05-04 A method for reading a multilevel cell in a non-volatile memory device WO2007130615A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2007800157148A CN101432819B (en) 2006-05-04 2007-05-04 A method for reading a multilevel cell in a non-volatile memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/417,573 US7917685B2 (en) 2006-05-04 2006-05-04 Method for reading a multilevel cell in a non-volatile memory device
US11/417,573 2006-05-04

Publications (2)

Publication Number Publication Date
WO2007130615A2 WO2007130615A2 (en) 2007-11-15
WO2007130615A3 true WO2007130615A3 (en) 2008-01-24

Family

ID=38626166

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/010904 WO2007130615A2 (en) 2006-05-04 2007-05-04 A method for reading a multilevel cell in a non-volatile memory device

Country Status (4)

Country Link
US (3) US7917685B2 (en)
KR (1) KR101071019B1 (en)
CN (1) CN101432819B (en)
WO (1) WO2007130615A2 (en)

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US8261158B2 (en) 2009-03-13 2012-09-04 Fusion-Io, Inc. Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US8589766B2 (en) * 2010-02-24 2013-11-19 Apple Inc. Codeword remapping schemes for non-volatile memories
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
KR101703279B1 (en) 2010-08-05 2017-02-06 삼성전자 주식회사 Flash memory device and read method thereof
US9135998B2 (en) 2010-11-09 2015-09-15 Micron Technology, Inc. Sense operation flags in a memory device
TWI420313B (en) * 2010-12-24 2013-12-21 Phison Electronics Corp Data management method, memory controller and embedded memory storage apparatus using the same
JP5426600B2 (en) * 2011-03-30 2014-02-26 株式会社東芝 Semiconductor memory
KR102123946B1 (en) * 2012-12-28 2020-06-17 삼성전자주식회사 A method of operating MLC memory device and MLC memory device
US20140269086A1 (en) * 2013-03-14 2014-09-18 Sandisk Technologies Inc. System and method of accessing memory of a data storage device
KR101460881B1 (en) * 2013-03-28 2014-11-20 주식회사 티엘아이 Apparatus and method for knowledge information management
CN104142801B (en) * 2013-05-09 2017-04-12 群联电子股份有限公司 Data writing method, storage controller and storage storing device
KR102422478B1 (en) 2016-05-10 2022-07-19 삼성전자주식회사 Read method of nonvolatile memory devices
US10153021B1 (en) 2017-06-09 2018-12-11 Micron Technology, Inc. Time-based access of a memory cell
US10153022B1 (en) * 2017-06-09 2018-12-11 Micron Technology, Inc Time-based access of a memory cell
US10445173B2 (en) 2017-06-26 2019-10-15 Macronix International Co., Ltd. Method and device for programming non-volatile memory
TWI648675B (en) * 2017-08-29 2019-01-21 群聯電子股份有限公司 Data storage method, memory control circuit unit and memory storage device
US10755793B2 (en) * 2017-10-31 2020-08-25 Micron Technology, Inc. SLC page read
US10621091B2 (en) * 2018-05-04 2020-04-14 Micron Technology, Inc. Apparatuses and methods to perform continuous read operations
WO2020128547A1 (en) * 2018-12-21 2020-06-25 Micron Technology, Inc. Method and device to ensure a secure memory access
US11416177B2 (en) * 2020-08-11 2022-08-16 Micron Technology, Inc. Memory sub-system storage mode control
US11393845B2 (en) 2020-08-28 2022-07-19 Micron Technology, Inc. Microelectronic devices, and related memory devices and electronic systems
US11562785B1 (en) 2021-08-30 2023-01-24 Micron Technology, Inc. Microelectronic devices, and related memory devices and electronic systems

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Also Published As

Publication number Publication date
KR20080111564A (en) 2008-12-23
WO2007130615A2 (en) 2007-11-15
US20110179218A1 (en) 2011-07-21
US20130339577A1 (en) 2013-12-19
US8656092B2 (en) 2014-02-18
US8375179B2 (en) 2013-02-12
US20070260817A1 (en) 2007-11-08
CN101432819B (en) 2011-09-21
CN101432819A (en) 2009-05-13
KR101071019B1 (en) 2011-10-06
US7917685B2 (en) 2011-03-29

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