WO2007134317A1 - Downhill wire bonding for semiconductor device - Google Patents

Downhill wire bonding for semiconductor device Download PDF

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Publication number
WO2007134317A1
WO2007134317A1 PCT/US2007/068959 US2007068959W WO2007134317A1 WO 2007134317 A1 WO2007134317 A1 WO 2007134317A1 US 2007068959 W US2007068959 W US 2007068959W WO 2007134317 A1 WO2007134317 A1 WO 2007134317A1
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WO
WIPO (PCT)
Prior art keywords
lead
capillary
wire
stitch
angle
Prior art date
Application number
PCT/US2007/068959
Other languages
French (fr)
Inventor
Meng Thee Chia
Original Assignee
Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/747,987 external-priority patent/US20080286959A1/en
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Publication of WO2007134317A1 publication Critical patent/WO2007134317A1/en

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    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the invention relates to the packaging of semiconductor devices and more particularly to a device and a method of downhill wire bonding between the bond pads of the integrated circuit and lead fingers.
  • Various techniques are used for packaging integrated circuits and for wire bonding between different locations of a semiconductor die, as well as between the semiconductor die and an external location such as a lead finger on a lead frame.
  • the lead fingers are generally formed of copper or a copper alloy such as A42 and the bond pads on the die are generally aluminum.
  • Wire bonding is performed by placing a capillary over a bond pad of the semiconductor die for making a ball bond with a ball of the wire extending out of the capillary and bonding the ball to the bond pad.
  • the capillary is then moved to a lead finger of the lead frame to which a bond is to be made with the wire traveling with respect to the capillary bore and a stitch bond is then made to the lead finger using the capillary with the wire then being broken, leaving a small wire pigtail extending out of the capillary.
  • wire bonding techniques form the wire connection between the bond pads of the semiconductor die and the lead fingers of the lead frame by forming a ball bond on the bond pads of the semiconductor die and looping the wire up and over to the lead fingers where the stitch bonds are formed to complete the wire bonding.
  • the capillary creates a stress on the wire which depends on the curvature and more particularly on the angle of approach.
  • the stress on the wire is proportional to the angle of approach of the wire bonding. The higher the angle of approach is, the more important the stress become. This causes the heel of the stitch bond to crack or to break away from the surface of contact and therefore to be unreliable, which leads to diminished yield due to faulty bonding.
  • the QFN package is a particular IC packaging that gained attention in the early 2001 as the latest package being no-lead that offered size reduction and good electrical performance especially for high power with exposed die pad and short leads within the package.
  • the miniature electronic devices may require three wires connected to one lead finger. With this type of exposed die pad, the resulting wire bonding angle is increased since the wire bonding between the die and the lead finger is a downhill bonding.
  • broken heel stitch is a serious reliability issue which cannot always be detected by test.
  • reliable wire bonding needs still to be improved especially in the case of configuration where more than one wire is connected to a lead finger. For instance in a configuration where three bonding wires are connected to a single lead finger, a broken heel stitch will cause the three bonding wires to be disconnected from the lead finger.
  • the invention provides a method of downhill wire bonding between the bond pads of an integrated circuit and lead fingers that lessens thermal and mechanical stresses of downhill wire bonding.
  • the above-noted problem is addressed by reducing the angle of approach of the capillary during the downhill wire bonding process between various components of the semiconductor.
  • the stitch platform is welded with a gold wire that loops from the semiconductor die to the lead finger or stitch platform. It is done using the thermosonic process meaning a welding process at high temperature with ultrasound.
  • the downhill wire bonding process for QFN is performed with a capillary using gold wire that connects the semiconductor die (substrate or the Integrated Circuit) to the lead fingers or stitch platform.
  • the gold wire is molten into a ball by applying high current.
  • the molten ball is compressed against the bond pads of the integrated circuit using temperature and ultrasonic energy.
  • the capillary is lifted vertically from the bond pads of the semiconductor die to loop over to the lead finger and the gold wire is compressed against the lead finger or the stitch platform with a reduced angle of approach of the capillary.
  • a method of downhill wire bonding between an integrated circuit and a plurality of lead fingers comprises the steps of: (a) forming a stitch bond on a wire bonding location on a die pad of the integrated circuit; (b) lifting vertically the wire by a height; (c) moving the wire away from the wire bonding location on said die pad of the integrated circuit to one of said plurality of lead fingers; (d) approaching one of said plurality of lead fingers with a reduced angle of approach; (e) forming a stitch bond on one of said plurality of lead fingers; and (f) bonding said one of said plurality of lead fingers to said die pad of the integrated circuit with a bonding wire which has a reduced angle with the surface of the lead finger.
  • a method of downhill wire bonding between an integrated circuit and a plurality of lead fingers comprises the steps of: (a) etching each said plurality of lead fingers to increase lead finger thickness; (b) providing lead frame with said plurality of lead fingers with increased thickness; (c) providing integrated circuit with a plurality of bonding pads; (d) applying adhesive to bond integrated circuit to a lead frame die; and (e) approaching a capillary with a reduced angle of approach to bond said plurality of bonding pads of the integrated circuit to said plurality of lead fingers with a bonding wire threaded through the bore of a capillary.
  • FIG. 1 is a plan view of a QFN L-lead design according to the prior art.
  • FIG. 2 is a partial cross-sectional view A-A of the QFN L-lead design according to the prior art.
  • FIG. 3 shows the heel of a stitch bond in a perspective view.
  • FIG. 4 shows a small crack of the heel of a stitch bond in an elevation view.
  • FIG. 5 is a plan view of a QFN L-lead design with an increased stitch platform on the lead finger according to the invention.
  • FIG. 6 is a partial cross-sectional view B-B of the QFN L-lead design with an increased stitch platform or lead finger according to the invention.
  • FIG. 7a and 7b show the comparison of partial cross- sectional view C-C between a design without an increased stitch platform or lead finger and a design with an increased stitch platform or lead finger and a reduction in the height of capillary lift.
  • FIG. 8 is another partial cross-sectional view C-C of another QFN L-lead design with an increased stitch platform or lead finger in more details.
  • FIG. 9 is a block diagram of an exemplary method for manufacturing a QFN L-lead with an increased stitch platform or lead finger.
  • FIG. 1 a standard semiconductor 10 is shown wherein a die 16 is coupled to a lead frame die 12. Die 16 and lead frame die 12 are bonded to one another, and may be electrically connected to one another.
  • die 16 comprises an integrated circuit wherein a plurality of conductive leads 18 are operable to connect die 16 to a plurality of lead fingers 20.
  • FIG. 2 shows a partial cross-sectional view A-A of the standard semiconductor 10 of
  • FIG. 1 shows how conductive leads 18 couple die 16 to the plurality of lead fingers 20.
  • the plurality of conductive leads 18 may be electrically coupled to a plurality of bonding pads (not shown) associated with the plurality of lead fingers 20 in order to electrically couple die 16 to lead fingers 20.
  • a standard capillary which has a gold wire, for example, extending through a bore enables to dispense conductive leads 18 by moving the capillary from die 16 to lead fingers 20 with the application of ultrasonic energy in a standard manner.
  • capillary is lifted vertically from die 16, moves toward a selected lead finger 20 and then lowers as it approaches the selected lead finger 20 with an inner angle 22 (or outer angle 21) to form a stitch bond on the selected lead finger 20.
  • the angle of approach or the inner angle 22 of the capillary determines the angle formed by the conductive lead 18 threaded through the bore of the capillary with the surface of the selected lead finger 20.
  • a standard angle of approach is very often above 60 degrees. It can even reach 90 degrees to become vertical to the surface of the lead finger 20.
  • the capillary is making the looping routine between die 16 and the plurality of lead fingers 20 with the gold wire being threaded through the bore of the capillary.
  • the capillary is then making the same stitch bond with the gold wire on all the lead fingers 20 with the application of ultrasonic energy. If the angle of approach of capillary is reduced for all the lead fingers 20, the risk of breaking the heels of all the stitch bonds will also be drastically reduced, which will consequently increase the reliability of the semiconductor.
  • FIG. 3 shows the heel of a stitch bond on a lead finger in a perspective view. If the angle of approach of the capillary is high, the surface of contact between lead 18 and lead finger 20 is reduced.
  • FIG. 4 shows a small crack of the heel of a stitch bond in an elevation view.
  • the small crack appears due to the thermal stress and mechanical stress that are applied to the heel of the stitch bond.
  • the inner angle 22 formed between lead 18 and the surface of the lead finger 20 should be reduced as much as possible to limit the thermal and mechanical stresses on the heel of the stitch bond and to increase the quality of the downhill wire bonding and the reliability of the semiconductor.
  • the angle of approach of the capillary should be as low as possible to increase the surface of contact between leads 18 and lead fingers 20.
  • the height at which the capillary is lifted vertically from die 16 before it moves toward the lead fingers 20 is the height at which the capillary is lifted vertically from die 16 before it moves toward the lead fingers 20.
  • the height should be as low as possible in order to have a nearly horizontal approach to the lead fingers 20.
  • the capillary is lifted vertically above the plane of the bond pad of die 16 at a height which is generally between 0.010 to 0.015 inches.
  • this height may be reduced to 0.006 inches in thinner packages but cannot cross beyond this limit since the gold wire may be damaged and cracked by a smaller loop height.
  • the reduction in the height of the capillary lift is shown in FIG. 7b and FIG. 8.
  • stitch platform is a generic term to designate the area of the stitch bond.
  • the area of the stitch platform depends on the application of the semiconductor.
  • the lead finger is the whole area of the stitch platform.
  • the stitch platform can just be portion of the lead finger or can be physically located independently from the lead finger.
  • FIG. 5 is a plan view of a QFN L- lead design with an increased stitch platform on the lead finger in a preferred embodiment.
  • a semiconductor 100 is shown wherein a die 116 is coupled to a lead frame die 112. Die 116 and lead frame die 112 are bonded to one another. In some embodiments, die 116 is electrically connected to lead frame die 112.
  • die 116 comprises an integrated circuit wherein a plurality of conductive leads 118 are operable to connect die 116 to a plurality of lead fingers 120.
  • Lead fingers 120 has an increased thickness shown with a shaded area 130 that enables to reduce the angle of the approach of the capillary during the downhill wire bonding of conductive leads 118.
  • lead fingers 120 can be, for example, a layer of polyimide film to which is secured a copper trace layer by means of adhesive layer.
  • die 116 and lead frame die 112 Prior to electrically connecting die 116 to lead frame die 112, die 116 and lead frame die 112 are physically bonded to one another via an adhesive 114 (shown in FIG. 2).
  • the adhesive 114 may comprise a fluid- like epoxy that is operable to be cured by an application of heat thereto.
  • FIG. 6 is a partial cross-sectional view B-B of the QFN L-lead design with the increased stitch platform or increased lead finger according to the invention.
  • Die 116 are connected to the plurality of lead fingers 120 by conductive leads 118.
  • All lead fingers 120 have an increased stitch platform by a height H that can be for instance more than 13 mils or more than 100 microns.
  • the thickness of lead fingers 120 is increased from 203 microns to 333 microns, which is represented by a shaded area 130.
  • the plurality of conductive leads 118 are electrically coupled to a plurality of bonding pads (not shown) associated with the plurality of lead fingers 120 in order to electrically couple die 116 to lead fingers 120.
  • the plurality of conductive leads 118 are made of gold wire.
  • a capillary which uses gold wire as conductive leads 118 moves its bore from die 116 to the increased stitch platform of lead fingers 120 using the application of ultrasonic energy in a standard manner.
  • the capillary is lifted vertically from die 116, moves toward a selected lead finger 120 with the increased stitch platform and then lowered as it approaches the selected lead finger 120 with an inner angle 122 (or outer angle 121).
  • the inner angle 122 is lower than the previously mentioned inner angle 22, provided that the coordinates of the stitch between the two configurations without and with increased stitch platform did not change (on the OXY axis) but only for its vertical position (OZ).
  • the angle of approach or the inner angle 122 of the capillary determines the angle formed by conductive lead 118 threaded through the bore of the capillary with the surface of lead finger 120. As previously mentioned, the higher the inner angle 122 is, the more important the stress on the heel of the stitch bond will be. In a preferred embodiment, the angle of approach of the capillary is reduced to less than 45 degrees, for instance between 35- 40 degrees.
  • FIG. 7a and 7b show the comparison of partial cross- sectional view C-C between a design without an increased stitch platform or lead finger and a design with an increased stitch platform or lead finger and a reduction in the height of capillary lift.
  • Both figures enable to show how the angle of approach 22 corresponding to a configuration without the increased stitch platform can be reduced to the angle of approach 122 corresponding to a configuration with the increased stitch platform and with a reduction in the height of capillary lift. It is not necessary to combine the increased stitch platform with the reduction in the height of capillary lift to reduce the angle of approach 22 to 122. But by combining both factors, the angle of approach is even more reduced.
  • FIG. 8 is a partial cross-sectional view C-C of another QFN L-lead design illustrating the compounds used with an increased stitch platform.
  • the integrated circuit 116 is bonded to the lead frame die 112 by an adhesive 114.
  • the compounds used for lead fingers 120 may be identical to the ones used for lead frame die 112.
  • a first layer of Copper base 158 is coated on both sides by a layer of Nickel (Ni) 156 with a thickness of 1 to 2 microns, which are then coated on both sides by a layer of Palladium (Pd) with a thickness of 0.02 to 0.1 micron, which are then coated by a thin layer of Gold (Au) with a thickness of 0.003 to 0.009 micron.
  • the plurality of lead fingers 120 or the lead frame die 112 may comprise compounds such as metal or metal allow including one or more copper, silver, gold, nickel, aluminum, palladium and titanium.
  • the total thickness of each lead finger 120 which has an increased thickness 130 represented by height H can be for instance more than 333 microns.
  • the additional height indicated by H may be for instance equivalent to 13 mils or more than 100 microns, represents an increase by more than 50%, since the thickness of lead fingers 120 is increased from 203 microns to total of 333 microns.
  • FIG. 9 is a block diagram of an exemplary method of manufacturing a QFN L-lead with an increased stitch platform or lead finger.
  • the lead fingers are etched to increase the thickness of the stitch platform.
  • the stitch platform represents the whole surface of the lead finger.
  • the lead frame is provided with lead fingers design and increased lead finger thickness.
  • the lead frame and the lead fingers can comprise the same compounds or different compounds.
  • an adhesive is applied to one or more of the interior regions.
  • the adhesive for example, comprises one or more components, such as a fluid-like resin.
  • the integrated circuit of the die is bonded to the lead fingers using gold wire dispensed by a capillary.

Abstract

A downhill wire bonding process for QFN uses a capillary having a gold wire for connecting a substrate and a stitch platform, wherein applying a high current moltens the gold wire into a ball. The molten ball is compressed against substrate bond pads using high temperature and ultrasonic energy. Vertical lifting of capillary relative to bond pads so as to loop over to the stitch platform compresses pads against the platform with the capillary having reduced angle of approach. Increasing the thickness of the stitch platform so as to reduce the capillary approach angle improves downhill wire bonding of the lead frames between various components of the semiconductor. Reducing capillary vertical lift height from the substrate before looping over to the stitch platform can also reduce capillary approach angle.

Description

DOWNHILL WIRE BONDING FOR SEMICONDUCTOR DEVICE
The invention relates to the packaging of semiconductor devices and more particularly to a device and a method of downhill wire bonding between the bond pads of the integrated circuit and lead fingers. BACKGROUND
Various techniques are used for packaging integrated circuits and for wire bonding between different locations of a semiconductor die, as well as between the semiconductor die and an external location such as a lead finger on a lead frame. The lead fingers are generally formed of copper or a copper alloy such as A42 and the bond pads on the die are generally aluminum. Wire bonding is performed by placing a capillary over a bond pad of the semiconductor die for making a ball bond with a ball of the wire extending out of the capillary and bonding the ball to the bond pad. The capillary is then moved to a lead finger of the lead frame to which a bond is to be made with the wire traveling with respect to the capillary bore and a stitch bond is then made to the lead finger using the capillary with the wire then being broken, leaving a small wire pigtail extending out of the capillary.
In many applications, such as wireless technologies or miniature electronic devices, it is desirable to reduce the thickness of the final packaging. And with the continued miniaturization of the packaging of semiconductor devices, in spite of the use of sophisticated bonding techniques such as the Ball Grid Array (BGA) or the Mini Ball Grid Array (MBGA), it is necessary to maintain and if possible to improve the reliability of wire bonding for such thin packages.
As previously mentioned, wire bonding techniques form the wire connection between the bond pads of the semiconductor die and the lead fingers of the lead frame by forming a ball bond on the bond pads of the semiconductor die and looping the wire up and over to the lead fingers where the stitch bonds are formed to complete the wire bonding.
Furthermore, by looping the wire up and down to complete the wire bonding, the capillary creates a stress on the wire which depends on the curvature and more particularly on the angle of approach. The stress on the wire is proportional to the angle of approach of the wire bonding. The higher the angle of approach is, the more important the stress become. This causes the heel of the stitch bond to crack or to break away from the surface of contact and therefore to be unreliable, which leads to diminished yield due to faulty bonding. The QFN package is a particular IC packaging that gained attention in the early 2001 as the latest package being no-lead that offered size reduction and good electrical performance especially for high power with exposed die pad and short leads within the package. In some QFN packages, the miniature electronic devices may require three wires connected to one lead finger. With this type of exposed die pad, the resulting wire bonding angle is increased since the wire bonding between the die and the lead finger is a downhill bonding.
As for traditional packaging, broken heel stitch is a serious reliability issue which cannot always be detected by test. Despite actions taken to enhance the wire bonding process that showed reduction in the number of broken heel stitches, reliable wire bonding needs still to be improved especially in the case of configuration where more than one wire is connected to a lead finger. For instance in a configuration where three bonding wires are connected to a single lead finger, a broken heel stitch will cause the three bonding wires to be disconnected from the lead finger. SUMMARY
The invention provides a method of downhill wire bonding between the bond pads of an integrated circuit and lead fingers that lessens thermal and mechanical stresses of downhill wire bonding.
In accordance with one aspect of the invention, the above-noted problem is addressed by reducing the angle of approach of the capillary during the downhill wire bonding process between various components of the semiconductor. The stitch platform is welded with a gold wire that loops from the semiconductor die to the lead finger or stitch platform. It is done using the thermosonic process meaning a welding process at high temperature with ultrasound. The downhill wire bonding process for QFN is performed with a capillary using gold wire that connects the semiconductor die (substrate or the Integrated Circuit) to the lead fingers or stitch platform. The gold wire is molten into a ball by applying high current. The molten ball is compressed against the bond pads of the integrated circuit using temperature and ultrasonic energy. To complete the connection, the capillary is lifted vertically from the bond pads of the semiconductor die to loop over to the lead finger and the gold wire is compressed against the lead finger or the stitch platform with a reduced angle of approach of the capillary.
There are two factors that enable reduction in the angle of approach of the capillary: increasing the thickness of the lead finger or the stitch platform; and/or reducing the height by which the capillary is lifted vertically from the semiconductor die before it loops over to the lead finger or the stitch platform.
According to one embodiment, a method of downhill wire bonding between an integrated circuit and a plurality of lead fingers comprises the steps of: (a) forming a stitch bond on a wire bonding location on a die pad of the integrated circuit; (b) lifting vertically the wire by a height; (c) moving the wire away from the wire bonding location on said die pad of the integrated circuit to one of said plurality of lead fingers; (d) approaching one of said plurality of lead fingers with a reduced angle of approach; (e) forming a stitch bond on one of said plurality of lead fingers; and (f) bonding said one of said plurality of lead fingers to said die pad of the integrated circuit with a bonding wire which has a reduced angle with the surface of the lead finger.
According to another embodiment, a method of downhill wire bonding between an integrated circuit and a plurality of lead fingers comprises the steps of: (a) etching each said plurality of lead fingers to increase lead finger thickness; (b) providing lead frame with said plurality of lead fingers with increased thickness; (c) providing integrated circuit with a plurality of bonding pads; (d) applying adhesive to bond integrated circuit to a lead frame die; and (e) approaching a capillary with a reduced angle of approach to bond said plurality of bonding pads of the integrated circuit to said plurality of lead fingers with a bonding wire threaded through the bore of a capillary.
The embodiments advantageously provide an improved QFN L-lead semiconductor package which comprises an integrated circuit bonded to a lead frame die with an adhesive, said integrated circuit having a plurality of die pads; and a plurality of lead fingers electrically wire bonded with said plurality of die pads of said integrated circuit; wherein each said plurality of lead fingers presents an increased stitch platform thickness. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a QFN L-lead design according to the prior art. FIG. 2 is a partial cross-sectional view A-A of the QFN L-lead design according to the prior art.
FIG. 3 shows the heel of a stitch bond in a perspective view.
FIG. 4 shows a small crack of the heel of a stitch bond in an elevation view. FIG. 5 is a plan view of a QFN L-lead design with an increased stitch platform on the lead finger according to the invention.
FIG. 6 is a partial cross-sectional view B-B of the QFN L-lead design with an increased stitch platform or lead finger according to the invention.
FIG. 7a and 7b show the comparison of partial cross- sectional view C-C between a design without an increased stitch platform or lead finger and a design with an increased stitch platform or lead finger and a reduction in the height of capillary lift.
FIG. 8 is another partial cross-sectional view C-C of another QFN L-lead design with an increased stitch platform or lead finger in more details.
FIG. 9 is a block diagram of an exemplary method for manufacturing a QFN L-lead with an increased stitch platform or lead finger.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The invention is directed towards a device and process for reducing the mechanical and thermal stress of stitch bonding by reducing the angle of approach of the downhill wire bonding. In FIG. 1, a standard semiconductor 10 is shown wherein a die 16 is coupled to a lead frame die 12. Die 16 and lead frame die 12 are bonded to one another, and may be electrically connected to one another. In the example shown in FIG.l, die 16 comprises an integrated circuit wherein a plurality of conductive leads 18 are operable to connect die 16 to a plurality of lead fingers 20. FIG. 2 shows a partial cross-sectional view A-A of the standard semiconductor 10 of
FIG. 1. And more particularly, FIG. 2 shows how conductive leads 18 couple die 16 to the plurality of lead fingers 20. Once die 16 and lead frame die 12 are physically bonded to one another, the plurality of conductive leads 18 may be electrically coupled to a plurality of bonding pads (not shown) associated with the plurality of lead fingers 20 in order to electrically couple die 16 to lead fingers 20. A standard capillary which has a gold wire, for example, extending through a bore enables to dispense conductive leads 18 by moving the capillary from die 16 to lead fingers 20 with the application of ultrasonic energy in a standard manner. In more details, capillary is lifted vertically from die 16, moves toward a selected lead finger 20 and then lowers as it approaches the selected lead finger 20 with an inner angle 22 (or outer angle 21) to form a stitch bond on the selected lead finger 20. The angle of approach or the inner angle 22 of the capillary determines the angle formed by the conductive lead 18 threaded through the bore of the capillary with the surface of the selected lead finger 20. The higher the inner angle 22 is, the more important the stress on the heel of the stitch bond will be. A standard angle of approach is very often above 60 degrees. It can even reach 90 degrees to become vertical to the surface of the lead finger 20.
Different types of stress are applied on the heel of the stitch bond: thermal stress and mechanical stress. These stresses tend to increase the risk of crack of the heel of the stitch bond and therefore of breaking the electrical contact between die 16 and the associated lead finger 20. Therefore, the angle of approach of the capillary should be reduced to an acceptable minimum.
Lead after lead, the capillary is making the looping routine between die 16 and the plurality of lead fingers 20 with the gold wire being threaded through the bore of the capillary. The capillary is then making the same stitch bond with the gold wire on all the lead fingers 20 with the application of ultrasonic energy. If the angle of approach of capillary is reduced for all the lead fingers 20, the risk of breaking the heels of all the stitch bonds will also be drastically reduced, which will consequently increase the reliability of the semiconductor.
FIG. 3 shows the heel of a stitch bond on a lead finger in a perspective view. If the angle of approach of the capillary is high, the surface of contact between lead 18 and lead finger 20 is reduced.
FIG. 4 shows a small crack of the heel of a stitch bond in an elevation view. The small crack appears due to the thermal stress and mechanical stress that are applied to the heel of the stitch bond. The inner angle 22 formed between lead 18 and the surface of the lead finger 20 should be reduced as much as possible to limit the thermal and mechanical stresses on the heel of the stitch bond and to increase the quality of the downhill wire bonding and the reliability of the semiconductor.
Therefore, in order to strengthen the heel of the stitch bond, the angle of approach of the capillary should be as low as possible to increase the surface of contact between leads 18 and lead fingers 20.
One factor that will favor the reduction of the angle of approach of the capillary is the height at which the capillary is lifted vertically from die 16 before it moves toward the lead fingers 20. The height should be as low as possible in order to have a nearly horizontal approach to the lead fingers 20. To avoid damaging the gold wire, the capillary is lifted vertically above the plane of the bond pad of die 16 at a height which is generally between 0.010 to 0.015 inches. However, in a preferred embodiment, this height may be reduced to 0.006 inches in thinner packages but cannot cross beyond this limit since the gold wire may be damaged and cracked by a smaller loop height. In a preferred embodiment, the reduction in the height of the capillary lift is shown in FIG. 7b and FIG. 8.
Another factor that will favor the reduction of the angle of approach of the capillary is to etch the stitch platform or the lead finger to increase its height by a reasonable amount so that the angle of approach of the capillary is as low as possible, which will be described in more details in FIG. 5, FIG. 6 and FIG. 7b. It should be kept in mind that the term "stitch platform" is a generic term to designate the area of the stitch bond. The area of the stitch platform depends on the application of the semiconductor. In a preferred embodiment, the lead finger is the whole area of the stitch platform. In other embodiments, the stitch platform can just be portion of the lead finger or can be physically located independently from the lead finger. FIG. 5 is a plan view of a QFN L- lead design with an increased stitch platform on the lead finger in a preferred embodiment. A semiconductor 100 is shown wherein a die 116 is coupled to a lead frame die 112. Die 116 and lead frame die 112 are bonded to one another. In some embodiments, die 116 is electrically connected to lead frame die 112. In FIG. 5, die 116 comprises an integrated circuit wherein a plurality of conductive leads 118 are operable to connect die 116 to a plurality of lead fingers 120. Lead fingers 120 has an increased thickness shown with a shaded area 130 that enables to reduce the angle of the approach of the capillary during the downhill wire bonding of conductive leads 118.
In a preferred embodiment, lead fingers 120 can be, for example, a layer of polyimide film to which is secured a copper trace layer by means of adhesive layer. Prior to electrically connecting die 116 to lead frame die 112, die 116 and lead frame die 112 are physically bonded to one another via an adhesive 114 (shown in FIG. 2). The adhesive 114 may comprise a fluid- like epoxy that is operable to be cured by an application of heat thereto.
FIG. 6 is a partial cross-sectional view B-B of the QFN L-lead design with the increased stitch platform or increased lead finger according to the invention. Die 116 are connected to the plurality of lead fingers 120 by conductive leads 118. All lead fingers 120 have an increased stitch platform by a height H that can be for instance more than 13 mils or more than 100 microns. In a preferred embodiment, the thickness of lead fingers 120 is increased from 203 microns to 333 microns, which is represented by a shaded area 130. As in the conventional semiconductor, once die 116 and lead frame die 112 are physically bonded to one another, the plurality of conductive leads 118 are electrically coupled to a plurality of bonding pads (not shown) associated with the plurality of lead fingers 120 in order to electrically couple die 116 to lead fingers 120. In a preferred embodiment, the plurality of conductive leads 118 are made of gold wire.
A capillary which uses gold wire as conductive leads 118 moves its bore from die 116 to the increased stitch platform of lead fingers 120 using the application of ultrasonic energy in a standard manner. In more details, the capillary is lifted vertically from die 116, moves toward a selected lead finger 120 with the increased stitch platform and then lowered as it approaches the selected lead finger 120 with an inner angle 122 (or outer angle 121). The inner angle 122 is lower than the previously mentioned inner angle 22, provided that the coordinates of the stitch between the two configurations without and with increased stitch platform did not change (on the OXY axis) but only for its vertical position (OZ).
The angle of approach or the inner angle 122 of the capillary determines the angle formed by conductive lead 118 threaded through the bore of the capillary with the surface of lead finger 120. As previously mentioned, the higher the inner angle 122 is, the more important the stress on the heel of the stitch bond will be. In a preferred embodiment, the angle of approach of the capillary is reduced to less than 45 degrees, for instance between 35- 40 degrees.
FIG. 7a and 7b show the comparison of partial cross- sectional view C-C between a design without an increased stitch platform or lead finger and a design with an increased stitch platform or lead finger and a reduction in the height of capillary lift. Both figures enable to show how the angle of approach 22 corresponding to a configuration without the increased stitch platform can be reduced to the angle of approach 122 corresponding to a configuration with the increased stitch platform and with a reduction in the height of capillary lift. It is not necessary to combine the increased stitch platform with the reduction in the height of capillary lift to reduce the angle of approach 22 to 122. But by combining both factors, the angle of approach is even more reduced.
FIG. 8 is a partial cross-sectional view C-C of another QFN L-lead design illustrating the compounds used with an increased stitch platform. The integrated circuit 116 is bonded to the lead frame die 112 by an adhesive 114. The compounds used for lead fingers 120 may be identical to the ones used for lead frame die 112. For instance in a preferred embodiment, a first layer of Copper base 158 is coated on both sides by a layer of Nickel (Ni) 156 with a thickness of 1 to 2 microns, which are then coated on both sides by a layer of Palladium (Pd) with a thickness of 0.02 to 0.1 micron, which are then coated by a thin layer of Gold (Au) with a thickness of 0.003 to 0.009 micron. In other embodiments, the plurality of lead fingers 120 or the lead frame die 112 may comprise compounds such as metal or metal allow including one or more copper, silver, gold, nickel, aluminum, palladium and titanium.
In a preferred embodiment, the total thickness of each lead finger 120 which has an increased thickness 130 represented by height H, can be for instance more than 333 microns. The additional height indicated by H may be for instance equivalent to 13 mils or more than 100 microns, represents an increase by more than 50%, since the thickness of lead fingers 120 is increased from 203 microns to total of 333 microns.
FIG. 9 is a block diagram of an exemplary method of manufacturing a QFN L-lead with an increased stitch platform or lead finger. At step 901, the lead fingers are etched to increase the thickness of the stitch platform. In some embodiment, the stitch platform represents the whole surface of the lead finger. At step 903, the lead frame is provided with lead fingers design and increased lead finger thickness. The lead frame and the lead fingers can comprise the same compounds or different compounds. At step 907, an adhesive is applied to one or more of the interior regions. The adhesive, for example, comprises one or more components, such as a fluid-like resin. At step 909, the integrated circuit of the die is bonded to the lead fingers using gold wire dispensed by a capillary.
Though the invention has been described with respect to a specific example embodiments, those skilled in the art to which the invention relates will appreciate that many other embodiments and variations thereof can be implemented, without departing from the scope of the claimed invention.

Claims

CLAIMSWhat is claimed is:
1. A method of downhill wire bonding between an integrated circuit and a lead finger, the method comprising the steps of: forming a stitch bond between a wire and a wire bonding location on a die pad of the integrated circuit; lifting the wire vertically by a height after forming the stitch bond; moving the wire away from the wire bonding location toward the lead finger; approaching the lead finger with the wire at a reduced angle of approach; and forming a stitch bond between the wire and a surface of the lead finger; wherein the lead finger is connected to the die pad with the wire, and the wire makes a reduced angle of less than 45 degrees with the surface of the lead finger.
2. The method of claim 1, wherein the angle is 30 to 40 degrees.
3. The method of claim 1, wherein the angle of approach is reduced by increasing a thickness of the lead finger.
4. The method of claim 1 or 2, wherein the lead finger thickness is at least 330 microns.
5. The method of claim 1 or 3, wherein the angle of approach is reduced by minimizing a height by which the wire is lifted from the wire bonding location.
6. The method of claim 1, 2 or 3, wherein the height by which the wire is lifted is no more than 0.006 inches.
7. The method of claim 1, 2 or 3, wherein said bonding wire is a gold alloy.
8. The method of claim 1, 2 or 3, further comprising etching said lead finger.
9. The method of claim 1, further comprising forming a QFN L-lead semiconductor package.
PCT/US2007/068959 2006-05-15 2007-05-15 Downhill wire bonding for semiconductor device WO2007134317A1 (en)

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US11/747,987 US20080286959A1 (en) 2007-05-14 2007-05-14 Downhill Wire Bonding for QFN L - Lead
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129220B2 (en) 2009-08-24 2012-03-06 Hong Kong Polytechnic University Method and system for bonding electrical devices using an electrically conductive adhesive

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904503A (en) * 1996-12-20 1999-05-18 Texas Instruments Incorporated Method of forming flat inner lead tips on lead frame
US5960262A (en) * 1997-09-26 1999-09-28 Texas Instruments Incorporated Stitch bond enhancement for hard-to-bond materials
US6112973A (en) * 1997-10-31 2000-09-05 Texas Instruments Incorporated Angled transducer-dual head bonder for optimum ultrasonic power application and flexibility for tight pitch leadframe
US6388336B1 (en) * 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
US20050109819A1 (en) * 2003-11-26 2005-05-26 Kulicke & Soffa Industries, Inc. Low loop height ball bonding method and apparatus
US6927479B2 (en) * 2003-06-25 2005-08-09 St Assembly Test Services Ltd Method of manufacturing a semiconductor package for a die larger than a die pad

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904503A (en) * 1996-12-20 1999-05-18 Texas Instruments Incorporated Method of forming flat inner lead tips on lead frame
US5960262A (en) * 1997-09-26 1999-09-28 Texas Instruments Incorporated Stitch bond enhancement for hard-to-bond materials
US6112973A (en) * 1997-10-31 2000-09-05 Texas Instruments Incorporated Angled transducer-dual head bonder for optimum ultrasonic power application and flexibility for tight pitch leadframe
US6388336B1 (en) * 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
US6927479B2 (en) * 2003-06-25 2005-08-09 St Assembly Test Services Ltd Method of manufacturing a semiconductor package for a die larger than a die pad
US20050109819A1 (en) * 2003-11-26 2005-05-26 Kulicke & Soffa Industries, Inc. Low loop height ball bonding method and apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129220B2 (en) 2009-08-24 2012-03-06 Hong Kong Polytechnic University Method and system for bonding electrical devices using an electrically conductive adhesive
US8833418B2 (en) 2009-08-24 2014-09-16 The Hong Kong Polytechnic University Method and system for bonding electrical devices using an electrically conductive adhesive

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