WO2007138076A1

WO2007138076A1 - Configuration of a slave node in relation to the polarity of a differential two-wire bus

Info

Publication number: WO2007138076A1
Application number: PCT/EP2007/055252
Authority: WO
Inventors: Klaus Fritzsche; Horst Hinkelmann
Original assignee: Honeywell Technologies Sarl
Priority date: 2006-05-31
Filing date: 2007-05-30
Publication date: 2007-12-06
Also published as: DE102006000264B3

Abstract

Method and bus interface for configuring a slave node on a differential two-wire bus with a receiving line and a transmitting line in relation to the polarity of the two-wire bus, wherein the following steps are to be taken for the slave node: Determination of a synchronization period of a master node in which no useful data are transmitted; Examination of a level on the receiving line of the two-wire bus during the synchronization period in comparison to a reference level of the receiving line for the synchronization period; and Inversion of the polarity of the two-wire bus on the slave node, if the level on the receiving line is unequal to the reference level.

Description

CONFIGURATION OF A SLAVE NODE WITH REGARD TO THE

POLARITY OF A DIFFERENTIAL TWO-WIRE BUSH

The invention relates to the configuration of a slave node with respect to the polarity of a differential two-wire bus to which the slave node is connected, and more particularly to a method of configuring the slave node and a bus interface for the slave node.

In the prior art, bus systems are known for connecting (micro) controllers and / or input / output modules of different components to be networked. As is known, bus systems can be operated according to the master-slave principle, according to which a slave node can not or may not access the shared medium and has to wait until it is asked by the (or one of) the master node.

In known bus systems, a distinction can be made between ground-based and differential buses, wherein the information in a ground-based bus is coded as a voltage level on one line versus the ground level on another line of the bus and on a differential bus as a voltage difference between voltage levels on different lines of the bus Buses are coded. An example of a bulk bus is an RS-232 or EIA-232 bus. One

An example of a differential bus is an RS-485 or EIA-485 bus.

In particular, in a differential bus with two lines, ie a differential two-wire bus, is the Polarity of the two lines crucial for the correct decoding of the transmitted information. Therefore, its lines, which are usually marked with + and - must always be connected with the correct polarity.

It is therefore a disadvantage of the prior art that the installation of such differential buses is difficult and error prone.

Accordingly, the object of the invention is to provide a method and a bus interface for a slave node, which make it possible to operate a differential two-wire bus with any polarity.

The object is achieved with the method according to claim 1 and the bus interface according to claim 7.

Further advantageous embodiments of the invention are set forth in the dependent claims.

It is an advantage of the invention that in the installation of a differential two-wire bus no consideration must be taken to its polarity, so the bus can be operated with any polarity.

The invention solves the problems of the prior art in that a wiring of

Bus system is facilitated and troubleshooting in case of miswiring is avoided.

According to one aspect of the invention, a synchronization cycle of a master Knotens what can be implemented in a simple and efficient way.

According to one aspect of the invention, the levels on the receive line and the transmit line of the bus are inverted by respective exclusive-OR gates. This implementation is advantageous because of its low complexity and can be easily adapted to the system's underlying logic family (eg, transistor-transistor logic).

Hereinafter, preferred embodiments of the invention will be described in more detail with reference to the drawings. Showing:

FIG. 1 shows a schematic block diagram of the bus interface of a slave node according to an embodiment of the invention,

FIG. 2 shows a flow diagram of a method according to an embodiment of the invention, and

FIG. 3 shows exemplary time sequences of a method according to an exemplary embodiment of the invention.

Referring to Figure 1, the connection of a differential two-wire bus (+, -), such as an RS-485 bus, to a slave node 2, such as a (micro) controller or I / O module, is illustrated. The connection is made via a corresponding bus driver 1, which controls the release for sending data onto the bus for the slave node 2 via a line DE. With RxD, the receiving line is designated in FIG. 1 and TxD denotes the transmission line in FIG. In the embodiments described here and below is a Implementation according to transistor-transistor logic (TTL) is based on, although the invention is not limited thereto.

The bus interface according to the invention is structurally connected between a physical cable port and the bus driver and a UART, i. a universal asynchronous transceiver located in the slave node.

The bus interface 2 according to the invention comprises a detection device 3 which detects a synchronization period of a master node, i. a period in which the sender of the master node is activated but does not transmit user data. Such a synchronization period occurs after the master node is started after it has set the signal polarity, and periodically, for example once per second. The duration of this period is for example about 30 ms.

According to one aspect of the invention, the synchronization period is detected by means of a timer 6 which is connected to the detection device. For this purpose, the timer 6 is set to a predetermined timer duration which is shorter than the length of the synchronization period, for example about 20 ms. The timer is started or restarted when the

Slave node is put into operation when data is received, or when a frame error occurs (see Figure 3). A synchronization period is therefore detected when no user data is received for the set timer duration.

The bus interface according to the invention further comprises a level check device 4 which is activated when the detection device detects a synchronization period and is connected to the detection device 3. The Level checker 4 checks the level on receive line RxD in the sync period as compared to a reference level expected during the sync period, depending on the logic family used. In the case of the TTL logic family, for example, a high level is expected in the synchronization period without payload data transmission.

Furthermore, the bus interface according to the invention comprises an inversion device 5, which is indicated by way of example in FIG. 1 by the dashed box. If the tested level is not equal to the expected reference level, the inverter 5 inverts the polarity of the two-wire bus at the slave node 2.

According to one aspect of the invention, the inversion of the bus polarity is accomplished by inversion of the levels on both the receive line RxD and the transmit line TxD. In the exemplary embodiment illustrated according to FIG. 1, such an inversion is represented by two exclusive ORs.

Gates (also known as antivalence gate) implemented, each having the input and transmission line as an input and an inverting line INV as another, common input. For inverting the polarity, the level of the inverting line INV is determined by the

Inverting device 5 inverted, i. brought from a low to a high level in TTL.

It should be noted that FIG. 1 shows only parts of the slave node 2 required for understanding the invention. For example, transmitter and receiver are not shown.

Referring to FIG. 2, a basic flowchart of a configuration method according to an embodiment is shown of the invention performed on a slave node in its bus interface.

After detection of a synchronization period in step Sl, a level applied to the receiving line RxD is checked in step S2 in comparison to an expected reference level. If the checked level is not equal to the reference level ("No" in step S3), the bus polarity is inverted (step S4), for example, by inverting the levels on the receiving and transmitting lines, and then, as in the case of equality, of the checked level and reference levels ("Yes" in step S3), receive payload (step S5). The method is carried out continuously, which is indicated in Figure 2 by the arrow from step S5 to step Sl, which due to the periodicity of

Synchronization period and the level check periodically occurs at each timer expiration.

According to FIG. 3, three exemplary timings of a configuration method according to an exemplary embodiment of the invention are illustrated. All three operations are preceded by the setting of the signal polarity on the bus by the master node and a first synchronization period after its commissioning.

The first procedure, labeled a), illustrates a case where the bus is inactive when the slave node is started up.

At start-up time tθ, the paths of the transmitter and receiver are initialized at the slave node in the normal mode. Accordingly, due to the fail-safe property in the TTL logic family, the output of the receiver on the receiving line RxD is at a high level when the bus is inactive. At time tl, a timer with predetermined timer duration T started to detect a synchronization period. At the expiration of the duration T at t2, the level of the receiving line and thus the polarity of the bus is checked, and found to be correct in the illustrated example.

At time t3, the master node restarts a synchronization period Sync, i. the master node activates its transmitter for transmission in idle mode, ie without user data transmission. At this time, the master node sends a byte which, in the illustrated example, is an inverse, i. wrong, has polarity. As a result, a low level is present on the receive line during sync period Sync at the slave node, although it should be high according to the TTL logic family. The byte sent by the master node is received at the slave node with a frame error at time t4 and therefore ignored. At t4, a timer with duration T is started again due to the byte reception. When it expires at time t5, the level on the

Receive line compared to the expected high level according to TTL logic family tested. At this time, it is found that the level is not equal to the expected reference level, and it is concluded that the polarity of the bus is wrong, whereupon it is changed as described above, for example, by raising the level of the inverting line INV of FIG. 1 to a high level.

After the end of the master synchronization period at time t6, the master node sends a payload message which is properly received by the prior inversion of the bus polarity at the slave node, although the two-wire bus's wires are connected in reverse. The second process, labeled b), illustrates a case in which the bus is active when the slave node is started up. This means that when the slave node is started up at t0, user data is transmitted in the form of messages on the bus.

All received bytes are ignored at the slave node (regardless of the presence of frame errors) before the first time a timer expiration has occurred, i. before a master synchronization period Sync has been detected for the first time. In FIG. 3 this is the case between times tθ 'and tl' or t2 '.

As described above, the timer is restarted after each data reception, wherein in Figure 2, the first

Timer expiration after the timer duration T at time t2 'is done. At time t2 ', the level of the receiving line or the polarity of the bus is checked by comparing the applied level (here high) with the expected reference level (here high, because of TTL). Since the tested level at t2 'coincides with the reference level, no inversion of level or polarity is necessary, i. the level of the inverter line INV remains low. The reception of payload data messages sent by the master node after the end of synchronization period Sync at time t3 'is properly possible.

The third process, designated c), also illustrates a case where the bus is active when the slave node is started up.

In contrast to the sequence indicated by b), in this case, after the expiration of the timer duration T at the time t2 ", it is determined that the applied level is on the receive line (here low) is not equal to the reference level (here high, because of TTL), which is why at t2 '' the RxD level as well as the TxD level, and thus also the polarity of the bus, is inverted. This is done according to an aspect of the invention described above by applying a high level on the inverting line INV, which forms an input of both of the exclusive-OR gates shown in FIG. Due to the polarity inversion, the slave node is able to properly receive the payload message sent after the end of the sync period at time t3 "although the two-wire bus lines are connected in reverse.

In summary, the slave node determines the timing of the timer expiration, i. the capture of a

Synchronization period of the master node used to adapt to the polarity of the bus.

Although the invention and its embodiments are described above by way of example, assuming the use of the TTL logic family, it is equally applicable to the use of other logic families. Also, the invention is applicable to any differential two-wire bus, even though the embodiments described above are related to the RS-485 bus by way of example.

Claims

claims

A method of configuring a slave node on a differential two-wire bus having a receive line and a transmit line related to the polarity of the

Two-wire bus, where the following at the slave node

Steps to be performed:

Detecting (S1) a synchronization period from a master node in which no payload data is transmitted; Checking (S2, S3) a level on the receiving line of the two-wire bus during the synchronization period in

Comparison to a reference level of the receiving line for the synchronization period; and inverting (S4) the polarity of the two-wire bus at the slave node when the level on the receiving line is not equal to the reference level.

2. The method of claim 1, wherein the synchronization period is detected by elapse of a predetermined timer duration after determining a frame error when the bus is idle at the time the slave node is powered up or after receiving payload data.

3. The method according to claim 2, wherein the predetermined

Timer duration is shorter than a predetermined length of the synchronization period.

4. Method according to one of the preceding claims, in which the polarity of the bus is inverted by the

Level on the receiving line and the level on the transmission line are inverted.

The method according to one of the preceding claims, wherein the differential two-wire bus is an RS-485 bus.

6. The method according to any one of the preceding claims, wherein the differential two-wire bus is operated according to transistor-transistor logic.

7. bus interface for a slave node on a differential two-wire bus with a receiving line

(RxD) and a transmission line (TxD), where the

Bus interface is configured to configure the slave node with respect to the polarity of the two-wire bus, with a detection device (2) for detecting a

Synchronization period from a master node in which no user data is transmitted; a level checker (4) for checking a level on the receiving line of the two-wire bus during

Synchronization period compared to a reference level of the receiving line for the synchronization period; and inverting means (5) for inverting the polarity of the two-wire bus at the slave node when the

Level on the receiving line is not equal to the reference level.

8. A bus interface according to claim 7, further comprising a timer (6) for detecting the synchronization period by elapse of a predetermined timer duration after determining a frame error when the bus is inactive at startup of the slave node, or after receiving payload data.

9. The bus interface of claim 8, wherein the predetermined timer duration is shorter than a predetermined length of the synchronization period.

A bus interface according to any one of claims 7 to 9, wherein the inverting means (5) comprises: an exclusive-OR gate whose inputs are the receiving line (RxD) and an inverting line (INV), and an exclusive-OR gate, whose inputs are the transmission line (TxD) and the inversion line (INV).

11. The bus interface according to claim 10, wherein the inversion device is set up, the polarity of

Invert the bus by inverting the level of the inverting line.

The bus interface of any one of claims 7 to 11, wherein the differential two-wire bus is an RS-485 bus.

13. The bus interface according to claim 7, wherein the differential two-wire bus is operated according to transistor-transistor logic.