WO2007143508A3 - Sliding-window, block-based branch target address cache - Google Patents

Sliding-window, block-based branch target address cache Download PDF

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Publication number
WO2007143508A3
WO2007143508A3 PCT/US2007/070111 US2007070111W WO2007143508A3 WO 2007143508 A3 WO2007143508 A3 WO 2007143508A3 US 2007070111 W US2007070111 W US 2007070111W WO 2007143508 A3 WO2007143508 A3 WO 2007143508A3
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WO
WIPO (PCT)
Prior art keywords
block
instruction
btac
window
sliding
Prior art date
Application number
PCT/US2007/070111
Other languages
French (fr)
Other versions
WO2007143508A2 (en
Inventor
Rodney Wayne Smith
James Norris Dieffenderfer
Brian Michael Stempel
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Rodney Wayne Smith
James Norris Dieffenderfer
Brian Michael Stempel
Thomas Andrew Sartorius
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Rodney Wayne Smith, James Norris Dieffenderfer, Brian Michael Stempel, Thomas Andrew Sartorius filed Critical Qualcomm Inc
Priority to AT07797948T priority Critical patent/ATE535862T1/en
Priority to JP2009514477A priority patent/JP5231403B2/en
Priority to CN2007800204454A priority patent/CN101460922B/en
Priority to EP07797948A priority patent/EP2024820B1/en
Publication of WO2007143508A2 publication Critical patent/WO2007143508A2/en
Publication of WO2007143508A3 publication Critical patent/WO2007143508A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Abstract

A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
PCT/US2007/070111 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache WO2007143508A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT07797948T ATE535862T1 (en) 2006-06-05 2007-05-31 SLIDING WINDOW, BLOCK BASED JUMP DESTINATION ADDRESS CACHE
JP2009514477A JP5231403B2 (en) 2006-06-05 2007-05-31 Sliding window block based branch target address cache
CN2007800204454A CN101460922B (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache
EP07797948A EP2024820B1 (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/422,186 US7827392B2 (en) 2006-06-05 2006-06-05 Sliding-window, block-based branch target address cache
US11/422,186 2006-06-05

Publications (2)

Publication Number Publication Date
WO2007143508A2 WO2007143508A2 (en) 2007-12-13
WO2007143508A3 true WO2007143508A3 (en) 2008-01-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070111 WO2007143508A2 (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache

Country Status (7)

Country Link
US (1) US7827392B2 (en)
EP (1) EP2024820B1 (en)
JP (2) JP5231403B2 (en)
KR (1) KR101016541B1 (en)
CN (2) CN103019652B (en)
AT (1) ATE535862T1 (en)
WO (1) WO2007143508A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US8407187B2 (en) 2010-06-16 2013-03-26 Microsoft Corporation Validating files using a sliding window to access and correlate records in an arbitrarily large dataset
US9201658B2 (en) * 2012-09-24 2015-12-01 Apple Inc. Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries
US9262328B2 (en) * 2012-11-27 2016-02-16 Nvidia Corporation Using cache hit information to manage prefetches
US9563562B2 (en) 2012-11-27 2017-02-07 Nvidia Corporation Page crossing prefetches
US9639471B2 (en) 2012-11-27 2017-05-02 Nvidia Corporation Prefetching according to attributes of access requests
GB2501582B (en) 2013-02-11 2014-12-24 Imagination Tech Ltd Speculative load issue
US9489204B2 (en) * 2013-03-15 2016-11-08 Qualcomm Incorporated Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
US10747540B2 (en) * 2016-11-01 2020-08-18 Oracle International Corporation Hybrid lookahead branch target cache
US20190004805A1 (en) * 2017-06-28 2019-01-03 Qualcomm Incorporated Multi-tagged branch prediction table
US11915004B2 (en) * 2021-12-20 2024-02-27 Arm Limited Control flow prediction

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
US20020194462A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
EP1624369A2 (en) * 2004-08-04 2006-02-08 VIA Technologies, Inc. Apparatus for predicting multiple branch target addresses

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
US5414822A (en) * 1991-04-05 1995-05-09 Kabushiki Kaisha Toshiba Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
KR100310581B1 (en) * 1993-05-14 2001-12-17 피터 엔. 데트킨 Inference recording mechanism of branch target buffer
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
JP3494484B2 (en) * 1994-10-12 2004-02-09 株式会社ルネサステクノロジ Instruction processing unit
JP3494736B2 (en) * 1995-02-27 2004-02-09 株式会社ルネサステクノロジ Branch prediction system using branch destination buffer
GB9521980D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Branch target buffer
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US5774710A (en) * 1996-09-19 1998-06-30 Advanced Micro Devices, Inc. Cache line branch prediction scheme that shares among sets of a set associative cache
US5918044A (en) * 1996-10-31 1999-06-29 International Business Machines Corporation Apparatus and method for instruction fetching using a multi-port instruction cache directory
JPH10133874A (en) * 1996-11-01 1998-05-22 Mitsubishi Electric Corp Branch predicting mechanism for superscalar processor
DE69727773T2 (en) * 1996-12-10 2004-12-30 Texas Instruments Inc., Dallas Improved branch prediction in a pipeline microprocessor
US6119222A (en) * 1996-12-23 2000-09-12 Texas Instruments Incorporated Combined branch prediction and cache prefetch in a microprocessor
US6108775A (en) * 1996-12-30 2000-08-22 Texas Instruments Incorporated Dynamically loadable pattern history tables in a multi-task microprocessor
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
US6263427B1 (en) * 1998-09-04 2001-07-17 Rise Technology Company Branch prediction mechanism
US6601161B2 (en) * 1998-12-30 2003-07-29 Intel Corporation Method and system for branch target prediction using path information
EP1150213B1 (en) * 2000-04-28 2012-01-25 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Data processing system and method
WO2002008895A1 (en) * 2000-07-21 2002-01-31 Koninklijke Philips Electronics N.V. Data processor with branch target buffer
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US6877083B2 (en) * 2001-10-16 2005-04-05 International Business Machines Corporation Address mapping mechanism for behavioral memory enablement within a data processing system
US6792521B2 (en) * 2001-10-16 2004-09-14 International Business Machines Corporation Behavioral memory mechanism for a data processing system
US6675279B2 (en) * 2001-10-16 2004-01-06 International Business Machines Corporation Behavioral memory enabled fetch prediction mechanism within a data processing system
JP3738842B2 (en) * 2002-06-04 2006-01-25 富士通株式会社 Information processing apparatus with delayed branch function
US7266676B2 (en) * 2003-03-21 2007-09-04 Analog Devices, Inc. Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays
US7174444B2 (en) * 2003-03-31 2007-02-06 Intel Corporation Preventing a read of a next sequential chunk in branch prediction of a subject chunk
US7124287B2 (en) * 2003-05-12 2006-10-17 International Business Machines Corporation Dynamically adaptive associativity of a branch target buffer (BTB)
US20040250054A1 (en) * 2003-06-09 2004-12-09 Stark Jared W. Line prediction using return prediction information
US7096348B2 (en) * 2003-12-15 2006-08-22 Freescale Semiconductor, Inc. Method and apparatus for allocating entries in a branch target buffer
JP2006048132A (en) * 2004-07-30 2006-02-16 Fujitsu Ltd Branching prediction device, control method of the branching prediction device, and information processing device
US7328332B2 (en) * 2004-08-30 2008-02-05 Texas Instruments Incorporated Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
KR100630702B1 (en) * 2004-10-05 2006-10-02 삼성전자주식회사 Controller for instruction cache and instruction translation look-aside buffer, and method of controlling the same
US7447882B2 (en) * 2005-04-20 2008-11-04 Arm Limited Context switching within a data processing system having a branch prediction mechanism
US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US20080040576A1 (en) * 2006-08-09 2008-02-14 Brian Michael Stempel Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set
US7707396B2 (en) * 2006-11-17 2010-04-27 International Business Machines Corporation Data processing system, processor and method of data processing having improved branch target address cache
US7937573B2 (en) * 2008-02-29 2011-05-03 Freescale Semiconductor, Inc. Metric for selective branch target buffer (BTB) allocation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
US20020194462A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
EP1624369A2 (en) * 2004-08-04 2006-02-08 VIA Technologies, Inc. Apparatus for predicting multiple branch target addresses

Also Published As

Publication number Publication date
CN103019652A (en) 2013-04-03
KR101016541B1 (en) 2011-02-24
US7827392B2 (en) 2010-11-02
CN101460922A (en) 2009-06-17
EP2024820B1 (en) 2011-11-30
CN103019652B (en) 2015-04-29
EP2024820A2 (en) 2009-02-18
CN101460922B (en) 2013-01-02
KR20090017687A (en) 2009-02-18
JP2009540439A (en) 2009-11-19
JP5231403B2 (en) 2013-07-10
JP2013080497A (en) 2013-05-02
ATE535862T1 (en) 2011-12-15
US20070283134A1 (en) 2007-12-06
JP5734945B2 (en) 2015-06-17
WO2007143508A2 (en) 2007-12-13

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