WO2007143508A3 - Sliding-window, block-based branch target address cache - Google Patents

Sliding-window, block-based branch target address cache Download PDF

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Publication number
WO2007143508A3
WO2007143508A3 PCT/US2007/070111 US2007070111W WO2007143508A3 WO 2007143508 A3 WO2007143508 A3 WO 2007143508A3 US 2007070111 W US2007070111 W US 2007070111W WO 2007143508 A3 WO2007143508 A3 WO 2007143508A3
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WO
WIPO (PCT)
Prior art keywords
block
instruction
btac
window
sliding
Prior art date
Application number
PCT/US2007/070111
Other languages
French (fr)
Other versions
WO2007143508A2 (en
Inventor
Rodney Wayne Smith
James Norris Dieffenderfer
Brian Michael Stempel
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Rodney Wayne Smith
James Norris Dieffenderfer
Brian Michael Stempel
Thomas Andrew Sartorius
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Rodney Wayne Smith, James Norris Dieffenderfer, Brian Michael Stempel, Thomas Andrew Sartorius filed Critical Qualcomm Inc
Priority to EP07797948A priority Critical patent/EP2024820B1/en
Priority to AT07797948T priority patent/ATE535862T1/en
Priority to JP2009514477A priority patent/JP5231403B2/en
Priority to CN2007800204454A priority patent/CN101460922B/en
Publication of WO2007143508A2 publication Critical patent/WO2007143508A2/en
Publication of WO2007143508A3 publication Critical patent/WO2007143508A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
PCT/US2007/070111 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache WO2007143508A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07797948A EP2024820B1 (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache
AT07797948T ATE535862T1 (en) 2006-06-05 2007-05-31 SLIDING WINDOW, BLOCK BASED JUMP DESTINATION ADDRESS CACHE
JP2009514477A JP5231403B2 (en) 2006-06-05 2007-05-31 Sliding window block based branch target address cache
CN2007800204454A CN101460922B (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/422,186 2006-06-05
US11/422,186 US7827392B2 (en) 2006-06-05 2006-06-05 Sliding-window, block-based branch target address cache

Publications (2)

Publication Number Publication Date
WO2007143508A2 WO2007143508A2 (en) 2007-12-13
WO2007143508A3 true WO2007143508A3 (en) 2008-01-31

Family

ID=38654617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070111 WO2007143508A2 (en) 2006-06-05 2007-05-31 Sliding-window, block-based branch target address cache

Country Status (7)

Country Link
US (1) US7827392B2 (en)
EP (1) EP2024820B1 (en)
JP (2) JP5231403B2 (en)
KR (1) KR101016541B1 (en)
CN (2) CN103019652B (en)
AT (1) ATE535862T1 (en)
WO (1) WO2007143508A2 (en)

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US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US8407187B2 (en) 2010-06-16 2013-03-26 Microsoft Corporation Validating files using a sliding window to access and correlate records in an arbitrarily large dataset
US9201658B2 (en) * 2012-09-24 2015-12-01 Apple Inc. Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries
US9639471B2 (en) 2012-11-27 2017-05-02 Nvidia Corporation Prefetching according to attributes of access requests
US9262328B2 (en) * 2012-11-27 2016-02-16 Nvidia Corporation Using cache hit information to manage prefetches
US9563562B2 (en) 2012-11-27 2017-02-07 Nvidia Corporation Page crossing prefetches
GB2501582B (en) 2013-02-11 2014-12-24 Imagination Tech Ltd Speculative load issue
US9489204B2 (en) * 2013-03-15 2016-11-08 Qualcomm Incorporated Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
US10747540B2 (en) * 2016-11-01 2020-08-18 Oracle International Corporation Hybrid lookahead branch target cache
US20190004805A1 (en) * 2017-06-28 2019-01-03 Qualcomm Incorporated Multi-tagged branch prediction table
US11915004B2 (en) * 2021-12-20 2024-02-27 Arm Limited Control flow prediction

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EP1624369A2 (en) * 2004-08-04 2006-02-08 VIA Technologies, Inc. Apparatus for predicting multiple branch target addresses

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Also Published As

Publication number Publication date
JP2009540439A (en) 2009-11-19
US7827392B2 (en) 2010-11-02
CN103019652A (en) 2013-04-03
US20070283134A1 (en) 2007-12-06
KR20090017687A (en) 2009-02-18
ATE535862T1 (en) 2011-12-15
EP2024820A2 (en) 2009-02-18
EP2024820B1 (en) 2011-11-30
WO2007143508A2 (en) 2007-12-13
JP5734945B2 (en) 2015-06-17
CN101460922A (en) 2009-06-17
CN103019652B (en) 2015-04-29
KR101016541B1 (en) 2011-02-24
JP2013080497A (en) 2013-05-02
CN101460922B (en) 2013-01-02
JP5231403B2 (en) 2013-07-10

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