WO2007146665A3 - Power distribution system for integrated circuits - Google Patents

Power distribution system for integrated circuits Download PDF

Info

Publication number
WO2007146665A3
WO2007146665A3 PCT/US2007/070401 US2007070401W WO2007146665A3 WO 2007146665 A3 WO2007146665 A3 WO 2007146665A3 US 2007070401 W US2007070401 W US 2007070401W WO 2007146665 A3 WO2007146665 A3 WO 2007146665A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuits
distribution system
power distribution
bypass
cavity
Prior art date
Application number
PCT/US2007/070401
Other languages
French (fr)
Other versions
WO2007146665A2 (en
Inventor
Steve Weir
Scott Mcmorrow
Original Assignee
Teraspeed Consulting Group Llc
Steve Weir
Scott Mcmorrow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/757,261 external-priority patent/US7886431B2/en
Priority claimed from US11/757,265 external-priority patent/US7773390B2/en
Priority claimed from US11/757,269 external-priority patent/US20070279882A1/en
Application filed by Teraspeed Consulting Group Llc, Steve Weir, Scott Mcmorrow filed Critical Teraspeed Consulting Group Llc
Publication of WO2007146665A2 publication Critical patent/WO2007146665A2/en
Publication of WO2007146665A3 publication Critical patent/WO2007146665A3/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231Capacitors or dielectric substances
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04Assemblies of printed circuits
    • H05K2201/049PCB for one component, e.g. for mounting onto mother PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/09309Core having two or more power planes; Capacitive laminate of two power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array

Abstract

Power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.
PCT/US2007/070401 2006-06-06 2007-06-05 Power distribution system for integrated circuits WO2007146665A2 (en)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US80408906P 2006-06-06 2006-06-06
US60/804,089 2006-06-06
US88714807P 2007-01-29 2007-01-29
US60/887,148 2007-01-29
US88714907P 2007-01-30 2007-01-30
US60/887,149 2007-01-30
US11/757,261 US7886431B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,265 US7773390B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,261 2007-06-01
US11/757,269 US20070279882A1 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,265 2007-06-01
US11/757,269 2007-06-01

Publications (2)

Publication Number Publication Date
WO2007146665A2 WO2007146665A2 (en) 2007-12-21
WO2007146665A3 true WO2007146665A3 (en) 2008-12-04

Family

ID=38832653

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070401 WO2007146665A2 (en) 2006-06-06 2007-06-05 Power distribution system for integrated circuits

Country Status (2)

Country Link
TW (1) TW200826753A (en)
WO (1) WO2007146665A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9241400B2 (en) 2013-08-23 2016-01-19 Seagate Technology Llc Windowed reference planes for embedded conductors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

Also Published As

Publication number Publication date
WO2007146665A2 (en) 2007-12-21
TW200826753A (en) 2008-06-16

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