WO2008008662A3 - External memory interface engine and serial communication input output interface engine - Google Patents

External memory interface engine and serial communication input output interface engine Download PDF

Info

Publication number
WO2008008662A3
WO2008008662A3 PCT/US2007/072675 US2007072675W WO2008008662A3 WO 2008008662 A3 WO2008008662 A3 WO 2008008662A3 US 2007072675 W US2007072675 W US 2007072675W WO 2008008662 A3 WO2008008662 A3 WO 2008008662A3
Authority
WO
WIPO (PCT)
Prior art keywords
interface engine
configurable
processor
external memory
device interface
Prior art date
Application number
PCT/US2007/072675
Other languages
French (fr)
Other versions
WO2008008662A2 (en
Inventor
James D Pennock
Ronald Baker
Brian R Parker
Christopher Belcher
Original Assignee
Harman Int Ind
James D Pennock
Ronald Baker
Brian R Parker
Christopher Belcher
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/771,743 external-priority patent/US9141567B2/en
Priority claimed from US11/771,764 external-priority patent/US20080016289A1/en
Application filed by Harman Int Ind, James D Pennock, Ronald Baker, Brian R Parker, Christopher Belcher filed Critical Harman Int Ind
Publication of WO2008008662A2 publication Critical patent/WO2008008662A2/en
Publication of WO2008008662A3 publication Critical patent/WO2008008662A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Abstract

A configurable device interface enhances the ability of a processor to communicate with other devices. The configurable device interface provides programmers with an efficient mechanism for communicating with a wide variety of external memories, each of which may have their own unique interface requirements. As a result, the configurable device interface permits a data processor to operate without hard coded dedicated state machines, and without waiting for an external memory to complete an instruction before the data processor may perform its next instruction. A configurable device interface enhances the ability of a processor to communicate with other devices. A configurable serial interface promotes efficient data transmission and reception. The configurable serial interface includes a source of transmit data that the configurable serial interface may access even while data reception is simultaneously completing.
PCT/US2007/072675 2006-07-11 2007-07-02 External memory interface engine and serial communication input output interface engine WO2008008662A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US83028306P 2006-07-11 2006-07-11
US60/830,283 2006-07-11
US11/771,743 2007-06-29
US11/771,743 US9141567B2 (en) 2006-07-11 2007-06-29 Serial communication input output interface engine
US11/771,764 2007-06-29
US11/771,764 US20080016289A1 (en) 2006-07-11 2007-06-29 External memory interface engine

Publications (2)

Publication Number Publication Date
WO2008008662A2 WO2008008662A2 (en) 2008-01-17
WO2008008662A3 true WO2008008662A3 (en) 2008-05-22

Family

ID=38800722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/072675 WO2008008662A2 (en) 2006-07-11 2007-07-02 External memory interface engine and serial communication input output interface engine

Country Status (1)

Country Link
WO (1) WO2008008662A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2128725B1 (en) * 2008-05-28 2011-06-29 Siemens Aktiengesellschaft Method for allocating memory in a buffer store

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809217A (en) * 1985-10-31 1989-02-28 Allen-Bradley Company, Inc. Remote I/O port for transfer of I/O data in a programmable controller
DE19529718A1 (en) * 1995-08-11 1997-02-13 Siemens Ag Buffer circuit arranged on a module
US6421274B1 (en) * 2001-03-23 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and reading and writing method thereof
US20030167368A1 (en) * 2002-03-01 2003-09-04 Yuji Tanaka Transmission control circuit, reception control circuit, communications control circuit, and communications control unit
EP1517331A2 (en) * 2003-09-16 2005-03-23 Samsung Electronics Co., Ltd. Memory system and control method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809217A (en) * 1985-10-31 1989-02-28 Allen-Bradley Company, Inc. Remote I/O port for transfer of I/O data in a programmable controller
DE19529718A1 (en) * 1995-08-11 1997-02-13 Siemens Ag Buffer circuit arranged on a module
US6421274B1 (en) * 2001-03-23 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and reading and writing method thereof
US20030167368A1 (en) * 2002-03-01 2003-09-04 Yuji Tanaka Transmission control circuit, reception control circuit, communications control circuit, and communications control unit
EP1517331A2 (en) * 2003-09-16 2005-03-23 Samsung Electronics Co., Ltd. Memory system and control method thereof

Also Published As

Publication number Publication date
WO2008008662A2 (en) 2008-01-17

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