WO2008009168A1

WO2008009168A1 - Method for protecting configuration information on programmable logic device

Info

Publication number: WO2008009168A1
Application number: PCT/CN2006/001630
Authority: WO
Inventors: Bo He; Tao Wang
Original assignee: Bo He; Tao Wang
Priority date: 2006-07-10
Filing date: 2006-07-10
Publication date: 2008-01-24

Abstract

A method for protecting a configuration information on a programmable logic device, includes: (1) a user identification area in which the user identification information corresponding to the different users is stored is set on the programmable logic device, and the case that any user can't write the user identification information of the other user into the user identification area can be ensured by the technical means; (2) the user identification information determines a method for compiling an original circuit into the configuration information;(3) when configuring the programmable logic device, it can configure itself after interpreting the inputted configuration information based on the user identification information, the interpreting method matching the compiling method in step(2).

Description

Method for protecting configuration information of programmable logic device

The invention relates to a method for protecting configuration information of a programmable logic device (PLD), which can be applied to a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a general array logic (GAL), Programmable Logic Array (PLA), Programmable Array Logic (PAL) programmable logic device. Background technique

At present, various programmable logic devices are widely used, such as field programmable gate array (FPGA), complex programmable logic device (CPLD), general array logic (GAL), programmable logic array (PLA), programmable array. Logic (PAL). Usually in these programmable logic device applications, it is necessary to use on-chip or off-chip programmable non-volatile memory such as one-time programmable read only memory (OTP ROM), electrically erasable read-only memory (EEPROM), flash memory (Flash ) to store the configuration information of the programmable logic device. In the circuit development phase based on programmable logic devices, programmable logic devices are often configured by a computer through a download cable.

Figure 1 illustrates the flow of a customer developing a circuit on a programmable logic device in the prior art. See Figure 1, S11: The customer obtains the programmable logic device from the manufacturer or supplier; S12: According to the public, general compilation rules, the customer's circuit design is compiled into a common configuration file by computer software; S13: Customer will The configuration file is written into the on-chip non-volatile memory of the above programmable logic device or the non-volatile memory of the off-chip electrical connection. Some programmable logic devices (such as most PLDs, CPLDs) are configured after being written into the configuration file, and have the design function after power-on; some programmable logic devices (such as most FPGAs) need to be powered on. After reading the configuration file in the non-volatile memory, the configuration can be completed, or the configuration can be completed by the computer after downloading the cable after power-on.

After the above steps, the customer's circuit design is implemented on the programmable logic device. Referring next to Figures 2A, 2B and 2C, the flow shown in Figure 1 is shown in block diagram form. 2A shows a block diagram structure of the configuration information memory on-chip, FIG. 2B shows a block diagram structure of the configuration information memory on the off-chip, and FIG. 2C shows a block diagram structure diagram in which configuration information is input from the computer to the programmable logic device. The 2C solution for computer configuration is generally only used during the development phase and rarely used in actual products. The reason is obvious. There is very little computer system in the actual product. Therefore, most systems using programmable logic devices have their configuration information stored in non-volatile memory. . However, whether the non-volatile memory is on-chip or off-chip, and is always implemented on a certain physical material (such as silicon wafer), any person skilled in the relevant art can use certain physical or chemical methods. The configuration information stored in the non-volatile memory is read out at a lower cost. For convenience of description, a person who attempts to read other people's configuration information for a programmable logic device without authorization is hereinafter referred to as a cracker.

If the cracker reads the configuration information stored in the memory 22A or 22B (shown in Fig. 2A or Fig. 2B), the quick copy can be realized by purchasing the same programmable logic device and writing the configuration information.

To this end, many methods for protecting the configuration information of programmable logic devices have been developed. The guiding principles of these methods are to prevent configuration information from being stored in the memory 22A or 22B (shown in FIG. 2A or FIG. 2B) by various means. Read or increase the time and cost of the cracker reading configuration information. For example, the encryption bit is set for protection, and the encryption bit is enabled after the configuration information is written to the memory to prevent the information from being read. An easy way to disable the protection mechanism: The cracker can open the integrated circuit package and then use some specific methods (such as focused ion beam (FIB)) to control the encryption bit signal to achieve the purpose of reading the configuration information. Therefore, the method of using the encryption bit increases the cracking cost, and the effect of preventing the crack is general. Summary of the invention

The object of the present invention is to solve the above problems and provide an inexpensive method for protecting configuration information of a programmable logic device, which does not rely on preventing customer configuration information from being read out, thereby greatly increasing the cost of cracking. It greatly prolongs the time required for cracking, and can effectively prevent the customer's configuration information from being easily cracked without the control of the manufacturer and the customer.

The technical solution of the present invention is: a method for protecting configuration information of a programmable logic device, for protecting a customer based on the programmable logic device when the programmable logic device is controlled by a manufacturer and a customer Configuration information, where the protection method includes:

(1) adding a customer identification area in the programmable logic device, wherein the customer identification area stores customer identification information corresponding to different customers, and technically ensures that any customer cannot write other customer's customers in the customer identification area. Identification information;

(2) the customer identification information determines a compilation method from the original circuit design to the configuration information corresponding to one-to-one, and the compilation method does not need to be disclosed, and can be grasped only by the manufacturer and the corresponding customer;

(3) When configuring the programmable logic device, the programmable logic device will first be based on the customer. The identification information is used to configure itself after the input configuration information is interpreted accordingly, and the interpretation method matches the compilation method in step (2). Similarly, the method of interpretation is not required to be disclosed, but can only be mastered by the manufacturer and the corresponding customer.

The foregoing method for protecting configuration information of a programmable logic device, wherein, in step (1), the technical means that the customer identification area is implemented by a one-time programmable read-only memory, and the manufacturer is in the customer The identification area presets the customer identification information corresponding to the customer.

The foregoing method for protecting configuration information of a programmable logic device, wherein, in step (1), the technical means refers to: first, a customer identification configuration number provided by a manufacturer to a customer, and then programmable by the customer The logic device inputs the customer identification configuration number, and the customer identification configuration number is processed by the programmable logic device to generate customer identification information and stored in the customer identification area. The specific content of the processing function need not be disclosed only by the manufacturer, and the customer identification configuration number provided to each customer can be grasped only by the manufacturer and the corresponding customer.

The foregoing method for protecting configuration information of a programmable logic device, wherein the processing function includes a combination of a certain complexity of verification, operation, or checksum operation to increase the difficulty of cracking, and the processing function is implemented. The body may be a new piece of hardware circuitry added to the programmable logic device, or if the programmable logic device has an embedded microprocessor, the processor may also execute an embedded program to perform the processing function.

The foregoing method for protecting configuration information of a programmable logic device, wherein the interpretation method comprises a combination of a certain complexity of verification, operation, or checksum operation to increase the difficulty of cracking, and the interpretation function is implemented. The body may be a new piece of hardware circuitry added to the programmable logic device, or if the programmable logic device has an embedded microprocessor, the processor may also execute an embedded program to perform the interpretation function. The hardware circuit or embedded program implementing the interpretation method is consistent for different customers, but the hardware circuit or the embedded program may interpret the input configuration information differently according to different customer identification information. The specific content of the hardware circuit or embedded program implementing the interpretation method is only known by the manufacturer, and the determined logical function exhibited by the interpretation method under the determined customer identification is only by the manufacturer and the customer corresponding to the customer identification. grasp.

The above method for protecting configuration information of a programmable logic device, wherein the compiling method and the interpreting method are static, and the behavior of compiling and interpreting does not change with time.

The above method for protecting configuration information of a programmable logic device, wherein the compiling method and the interpreting method are dynamic, and the compiling and interpreting behaviors are different under different conditions.

Compared with the prior art, the present invention has the following beneficial effects: The present invention is controlled by customer identification information. How the configuration information is compiled and interpreted. Even if the cracker reads the customer identification information and the configuration information, since the other party's customer identification information cannot be written to the programmable logic device, the programmable logic device to which the configuration information can be applied cannot be obtained, and rapid imitation cannot be realized. BRIEF abstract

1 is a flow chart of a prior art customer development circuit based on a programmable logic device.

2A is a block diagram of one embodiment of a prior art customer development logic circuit.

2B is a block diagram of another embodiment of a prior art customer development logic circuit.

2C is a block diagram of another embodiment of a prior art customer development logic circuit.

3 is a flow diagram of one embodiment of a client development logic circuit in accordance with the present invention.

4 is a logic circuit diagram of an embodiment of a decoding circuit in the embodiment of FIG.

Figure 5 is a flow diagram of another embodiment of a client development logic circuit in accordance with the present invention.

Figure 6 is a logic circuit diagram of an embodiment of a codec circuit in the embodiment of Figure 5.

Figure 7 is a logic circuit diagram of an embodiment of a decoding circuit that dynamically compiles and interprets. BEST MODE FOR CARRYING OUT THE INVENTION

The invention will now be further described with reference to the drawings and embodiments.

Figure 3 illustrates a flow diagram of a simple embodiment of an FPGA employing the present invention and an embodiment of a customer developing a logic circuit on the FPGA platform. The scheme adds two parts of the circuit to the existing FPGA: one is the customer identification area and the hardware circuit responsible for writing the customer identification to the area; the other is a decoding circuit, which will come from on-chip or off-chip memory. The configuration information is decoded and then handed over to the FPGA. This process is described in detail below in conjunction with Figure 3.

Step S31: Customer A obtains an FPGA from a manufacturer or a supplier, and the customer identification area of the FPGA is not configured, that is, the customer identification area is a default value. A new hardware circuit has been added to the FPGA. The function of the hardware circuit is only controlled by the manufacturer, and its output is connected to the input of the customer identification area. At the same time, the manufacturer provides the customer identification configuration number corresponding to the customer A, the customer identification configuration number is unique and only the manufacturer and the customer A know. After obtaining the FPGA, the client A writes the customer identification configuration number to the FPGA. The customer identification configuration number is formed into the customer identification information by the checksum operation of the newly added hardware circuit and stored in the customer identification area. The customer identification configuration number and the customer identification information may be a binary string, and the operation operation of the hardware circuit is mainly a bit operation of a binary string, and may be an inverse operation, an OR operation, a reordering, or the like. Because the information in the customer identification area can only be input through the hardware circuit Modification, and the function of the hardware circuit is confidential. The customer identification configuration number is only known to both the manufacturer and the customer, so even if the cracker reads the customer identification information on the customer identification area, the hardware circuit is not known. The function, the corresponding customer identification configuration number cannot be pushed out, and the desired customer identification information cannot be written to the customer identification area of the FPGA. For example, the customer identification configuration number assigned by the manufacturer to customer A is "1010", and customer A inputs the identification number to the hardware circuit, and the function of the hardware circuit is to replace the input end of the binary string and then repeat After 6 times of output, the decoding circuit converts "1010" into customer identification information "001100110011001100110011" and stores it in the customer identification area of customer A.

It should be understood that the above hardware circuit is not necessary. If the FPGA has an embedded microprocessor, the processor may execute an embedded program to complete the processing function, and the function of the program is the same as that of the hardware circuit. , can also play the role of converting the customer identification configuration number into customer identification information. Or combine a hardware circuit and a program to achieve the same function. Any implementation that can perform the same function should be included in the scope of the present invention.

Step S32: According to the public, general compilation rules, the circuit design of the client A is compiled into general configuration information in the computer. This step belongs to the prior art and is the same as step S12 of Fig. 1.

Step S33: Determine an encoding manner according to the customer identification information of the customer A, and convert the general configuration information obtained in the previous step into the configuration information dedicated to the customer A. This encoding method is inverse to the decoding function of the decoding circuit in step S35. Still taking the customer identification information "001100110011001100110011" of the customer A in step S31 as an example, the customer identification information indicates that in step S35, the decoding method of the FPGA is the first two bits of the Byte data of the obtained configuration information. Negate. Obviously, the inverse processing is to reverse the first two bits of each Byte data of the general configuration information, so the corresponding encoding method in this step is also to invert the first two bits of the Byte data of the general configuration information to generate the client A dedicated. Configuration information. Here, the coding method is provided by the manufacturer to the customer A and is kept confidential by the manufacturer and customer A.

Step S34: The configuration information dedicated to the client A is written into the non-volatile memory for configuring the FPGA. The non-volatile memory can be designed in the chip of the FPGA chip, or can be disposed on the off-chip and electrically connected to the FPGA. In general, the non-volatile memory is a read only memory (ROM). This step is also a prior art and is the same as step S13 in Fig. 1. Through the above conversion means, even if the cracker reads out the configuration information of the client A stored in the ROM, the quick copying cannot be realized. Since the configuration information of the client A stored in the ROM has been encoded by the step S33, it cannot be used by the ordinary FPGA. It is identified, so even if the cracker goes to the market to purchase the same type of FPGA, the configuration information cannot be applied due to the lack of decoding operation corresponding to the encoding operation. To directly apply this configuration information, the customer ID configuration number of customer A must be obtained to write the customer logo corresponding to the configuration information to the customer logo area of the FPGA.

Step S35: After the FPGA is powered on, the configuration information specific to the client A is read and decoded into a common general configuration information by a decoding circuit in the FPGA, and then used to configure itself. The encoding process of this step and step S33 is reciprocal. The decoding circuit for all customers' FPGAs is the same, but different client identification information can control the decoding circuit to exhibit different decoding functions. As described above, the decoding circuit is configured by the client identification information of the client A to function as the first two bits of the Byte data of the obtained configuration information, and the logic circuit device realizes its specific function, as will be obtained above. For example, the first two bits of each Byte data of the configuration information are reversed. The implementation of the decoding circuit is as shown by the dashed box in FIG. In the configuration information memory 41, an inverter 43A, 43B is provided to each of the first two bit lines of the FPGA 42, and the remaining bit lines are directly connected to the configuration information memory 41 and the FPGA 42 without any device. If the configuration data is serially entered into the FPGA, it can be converted to parallel data before doing the above processing. Of course, the actual decoding circuit is not limited to one design, and it is included in the scope of the claims as long as the required decoding function is achieved.

Fig. 5 shows a flow of a simple embodiment using the CPLD of the present invention and another embodiment of the customer's circuit development on the CPLD platform. The scheme adds two parts of the circuit based on the existing CPLD: one is the customer identification area and the hardware circuit responsible for writing the customer identification to the area; the second is a piece of compiled code circuit, which decodes the input configuration information. The on-chip non-volatile memory is further written, and when the on-chip configuration information is required to be read, the configuration information of the on-chip non-volatile memory is encoded and output. The flow will be described in detail below in conjunction with FIG. 5.

Step S51: This step is similar to step S31 of the embodiment shown in FIG. 3, that is, the CPLD adds a customer identification area and corresponding hardware circuits compared to the existing CPLD. The description will not be repeated here. For example, the customer identification configuration number assigned by the manufacturer to customer B is "1101", and customer B inputs the customer identification configuration number to the hardware circuit, which converts "1101" into customer identification information.

"110111011101110111011101" is stored in the customer identification area.

Step S52: According to the public, general compilation rules, the circuit design of the client B is compiled into general configuration information in the computer. This step belongs to the prior art and is the same as step S12 of Fig. 1. Step S53: This step is the same as step S33 of the embodiment shown in FIG. Taking the customer identification information "110111011101110111011101" of the customer B in step S51 as an example, the customer identification information indicates that in step S54, the decoding method of the CPLD is to exchange the last two bits of the Byte data of the obtained configuration information. Obviously, the inverse processing is to exchange the last two bits of each Byte data of the general configuration information, so the corresponding encoding method in this step is also to exchange the last two bits of the Byte data of the general configuration information to generate the customer B dedicated. Configuration information. Here, the encoding method is provided by the manufacturer to the customer B and is kept confidential by the manufacturer and the customer B.

Step S54: The configuration information that has been compiled into the client B is written into the non-volatile memory in the CPLD chip. During the writing process, the configuration information sent to the CPLD is first decoded by the hardware codec circuit in the CPLD chip and then written into the non-volatile memory in the chip, and the specific decoding function of the codec circuit is identified by the on-chip customer. Information is decided. Taking customer B as an example, the customer identification information determines that the CPLD's codec circuit exchanges the last two bits of each Byte data of the input configuration information and then writes it to the non-volatile memory. After the writing is completed, the configuration information can be read out from the CPLD to verify whether the writing process is correct. During the reading process, the encoding and decoding circuit performs an encoding function that is reciprocal to the decoding process, so that the output configuration information is the same as the originally input configuration information. For verification.

The implementation of step S54 is similar to the step S35 of the embodiment of Fig. 3, that is, adding a codec circuit that interchanges the last two bits of each Byte configuration data. The codec circuit implements its specific function by the logic circuit device. Taking the function of exchanging the last two bits of each Byte configuration data as described above, the implementation of the codec circuit is as shown by the dotted line frame in FIG. A module 62 for interchanging two bits of signals is provided on the last two bit (bit) data line of the data bus of the CPLD on-chip non-volatile memory 63 connected to the CPLD input interface 61. The remaining bit data lines are not provided with any device. The CPLD input interface 61 and the on-chip memory 63 are directly connected. The bit data line 64 is connected to the input port A of the module 62, and the bit data line 65 is connected to the input port B of the module 62. After processing by the module 62, the output port C outputs the signal received by the input port B, and the output port D is output. Output the signal received by input A. If the configuration data is serially entered into the CPLD, it must be converted to parallel data before doing the above processing. Of course, the actual codec circuit does not have a design, and it is included in the scope of the claims as long as the required decoding function is achieved.

In both of the above embodiments, the way of compiling and interpreting is static. That is to say, in the compile and explain mode, no conditions are set. For the same client, the method of compiling the common configuration file obtained by the original development process into its own dedicated configuration file is time-independent. It is also possible to set the way of compiling and interpreting to be dynamic. The so-called dynamic means: You can set a condition to perform different compilation and interpretation operations under different conditions. For example, customer C's customer identification information 3⁄4 "110000001100110011011000" , the decoding method represented by the customer identification information is as follows: In the previous 1000 Byte configuration data, the first two digits of the configuration data are inverted, and the last two bits in the next 1000 Byte configuration data are exchanged. Then repeat the above process. The logic implementation of the decoding circuit is shown in the dashed box of Figure 7. A configuration information store (e.g., ROM) 71 that stores FPGA configuration data is coupled to modules 72 and 73, respectively, wherein module 72 can implement the inversion of the first two bits of the configuration data, and module 73 can effect the exchange of the last two bits of the configuration data. Modules 72 and 73 are coupled to a selector 74. The selector 74 has a selection terminal Sel that receives a control signal and an output terminal that is connected to the FPGA 75. The selector 74 selects a signal on one of the input ports as an output according to different control signals. In this example, the control signal refers to whether the condition that the 1000OO configuration data is full is satisfied. Of course, the corresponding dynamic method is also used in the process of compiling and obtaining the dedicated configuration information. It should be understood that the dynamic method described herein is for the foregoing static method, and can be applied to the embodiment shown in FIG. 3, and can also be applied to the embodiment shown in FIG. 5.

It should be understood that the step S31 of the embodiment of FIG. 3 and the step S51 of the embodiment shown in FIG. 5 can also be implemented in another manner. The manufacturer pre-writes the customer's corresponding customer identification information in the customer identification area according to the customer information before the programmable logic device leaves the factory. The customer identification area is implemented by one programmable read only memory (OTP ROM). That is to say, once the programmable logic device is shipped, its internal customer identification area cannot be erased.

In order to further increase the difficulty of cracking, the foregoing implementation method of the present invention can be further strengthened in the following three points. The first point: The code of the codec circuit and the circuit of the programmable logic device itself can be mixed together, which makes it difficult for the cracker to obtain the codec circuit, so that the client-specific compiler interpretation mode cannot be known. The second point: The codec circuit should have a certain complexity, which makes it difficult for the cracker to guess the function of the codec circuit. For example, the binary information from the customer identification area is first reordered and some mathematical operations are performed, and then the obtained configuration information is reordered and partially inverted according to the operation result, and the obtained result is output to the programmable logic device. For example, if the cracker reads the binary string of the customer identification information "110011001100110011001101", it is easy to associate with the compiler conversion mode as the last two digits of the configuration information. If the customer identification information is also converted, the bits of the binary string are reordered or logically converted into a new binary string, and the configuration information is processed according to the result. Even if the cracker reads the binary string of the customer identification information, the user cannot easily obtain the information of the client-specific conversion method. The third point: The processing function from the customer identification configuration number to the customer identification information should have a certain complexity. The customer ID configuration number can be longer and a checksum is added. The customer identification configuration number entered into the programmable logic device is verified Then re-sort and some logic operations are then output to the customer identification area.

It should be understood that the focus of the present invention is on compiling the configuration information of the programmable logic device in a client-specific compilation manner so that the cracker cannot quickly copy it even if the configuration information is obtained. The specific customer identification, the specific compilation and interpretation mode, the specific implementation of the codec circuit, and the like mentioned above are only examples, and are not intended to limit the present invention.

The above embodiments are provided to enable a person skilled in the art to implement or use the present invention, and those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept. The scope of protection of the invention is not limited by the embodiments described above, but should be the maximum range of the innovative features mentioned in the claims.

Claims

Claims 1 to a method of protecting configuration information of a programmable logic device for protecting circuit design information developed by a customer based on the programmable logic device while the programmable logic device is out of manufacturer and customer control, The method of protection includes:

(2) the customer identification information determines a compilation method from the original circuit design to the configuration information corresponding to one-to-one;

(3) When configuring the programmable logic device, the programmable logic device first configures the input configuration information according to the customer identification information, and then configures itself, and the interpretation method and the step (2) The compilation method in the match.

The method for protecting configuration information of a programmable logic device according to claim 1, wherein in the step (1), the technical means that the customer identification area is implemented by a one-time programmable read only memory. The customer identification information corresponding to the customer is preset by the manufacturer in the customer identification area.

The method for protecting configuration information of a programmable logic device according to claim 1, wherein in the step (1), the technical means refers to a customer identification configuration number first provided by the manufacturer to the customer. The customer identification configuration number is input by the customer to the programmable logic device, and the customer identification configuration number is processed by the programmable logic device to generate customer identification information and stored in the customer identification area.

The method for protecting configuration information of a programmable logic device according to claim 3, wherein the processing function comprises a combination of a certain complexity of verification, operation, or checksum operation to increase cracking. Difficulty, and the main body that implements the processing function may be a new hardware circuit added to the programmable logic device, or if the programmable logic device has an embedded microprocessor, the processor may execute an embedded program. Complete this processing function.

5 . The method for protecting configuration information of a programmable logic device according to claim 1 , wherein In the step (3), the interpretation method includes a combination of a certain complexity of verification, operation, or checksum operation to increase the difficulty of cracking, and the main body that implements the interpretation function may be a programmable logic device. A new piece of hardware circuitry is added, or if the programmable logic device has an embedded microprocessor, the processor can also execute an embedded program to perform the interpretation function.

The method for protecting configuration information of a programmable logic device according to claim 1, wherein in step (3), the hardware circuit or the embedded program implementing the interpretation method is consistent for different customers. However, the hardware circuit or the embedded program may differently interpret the input configuration information according to different customer identification information.

The method of protecting configuration information of a programmable logic device according to claim 1, wherein the compiling method and the interpreting method are static, and the behavior of compiling and interpreting does not change with time.

The method for protecting configuration information of a programmable logic device according to claim 1, wherein the compiling method and the interpreting method are dynamic, and the compiling and interpreting behaviors are different under different conditions.