WO2008021582A3 - Mram refreshing - Google Patents

Mram refreshing Download PDF

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Publication number
WO2008021582A3
WO2008021582A3 PCT/US2007/063009 US2007063009W WO2008021582A3 WO 2008021582 A3 WO2008021582 A3 WO 2008021582A3 US 2007063009 W US2007063009 W US 2007063009W WO 2008021582 A3 WO2008021582 A3 WO 2008021582A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
mram
refreshing
operating
cells
Prior art date
Application number
PCT/US2007/063009
Other languages
French (fr)
Other versions
WO2008021582A2 (en
Inventor
Romney R Katti
Original Assignee
Honeywell Int Inc
Romney R Katti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Int Inc, Romney R Katti filed Critical Honeywell Int Inc
Priority to EP07840128A priority Critical patent/EP2024976A2/en
Publication of WO2008021582A2 publication Critical patent/WO2008021582A2/en
Publication of WO2008021582A3 publication Critical patent/WO2008021582A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1695—Protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Abstract

A nonvolatile memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive memory bit. The memory includes toggle circuitry for altering the resistive states of memory cells within the memory without changing the logical states of the memory cells. The memory may be toggled to balance resistive decay associated with operating a memory bit under certain conditions or in extreme environments.
PCT/US2007/063009 2006-06-02 2007-03-01 Mram refreshing WO2008021582A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07840128A EP2024976A2 (en) 2006-06-02 2007-03-01 Nonvolatile memory with data clearing functionality

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/446,547 US7499313B2 (en) 2006-06-02 2006-06-02 Nonvolatile memory with data clearing functionality
US11/446,547 2006-06-02

Publications (2)

Publication Number Publication Date
WO2008021582A2 WO2008021582A2 (en) 2008-02-21
WO2008021582A3 true WO2008021582A3 (en) 2008-04-03

Family

ID=38789906

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/063009 WO2008021582A2 (en) 2006-06-02 2007-03-01 Mram refreshing

Country Status (3)

Country Link
US (1) US7499313B2 (en)
EP (1) EP2024976A2 (en)
WO (1) WO2008021582A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5019223B2 (en) * 2007-11-21 2012-09-05 株式会社東芝 Semiconductor memory device
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
US9042164B2 (en) 2012-03-26 2015-05-26 Honeywell International Inc. Anti-tampering devices and techniques for magnetoresistive random access memory
US8730715B2 (en) 2012-03-26 2014-05-20 Honeywell International Inc. Tamper-resistant MRAM utilizing chemical alteration
US8995166B2 (en) * 2012-12-20 2015-03-31 Intermolecular, Inc. Multi-level memory array having resistive elements for multi-bit data storage
US9147454B2 (en) * 2013-01-14 2015-09-29 Qualcomm Incorporated Magnetic tunneling junction non-volatile register with feedback for robust read and write operations

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052302A (en) * 1999-09-27 2000-04-18 Motorola, Inc. Bit-wise conditional write method and system for an MRAM
US20030206433A1 (en) * 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US6693826B1 (en) * 2001-07-30 2004-02-17 Iowa State University Research Foundation, Inc. Magnetic memory sensing method and apparatus
US6704230B1 (en) * 2003-06-12 2004-03-09 International Business Machines Corporation Error detection and correction method and apparatus in a magnetoresistive random access memory
US20060013039A1 (en) * 2004-07-19 2006-01-19 Daniel Braun Read out scheme for several bits in a single MRAM soft layer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5756366A (en) 1995-12-21 1998-05-26 Honeywell Inc. Magnetic hardening of bit edges of magnetoresistive RAM
US6269027B1 (en) 1998-04-14 2001-07-31 Honeywell, Inc. Non-volatile storage latch
US6455177B1 (en) 1999-10-05 2002-09-24 Seagate Technology Llc Stabilization of GMR devices
US6178111B1 (en) 1999-12-07 2001-01-23 Honeywell Inc. Method and apparatus for writing data states to non-volatile storage devices
US6493258B1 (en) 2000-07-18 2002-12-10 Micron Technology, Inc. Magneto-resistive memory array
US6512690B1 (en) * 2001-08-15 2003-01-28 Read-Rite Corporation High sensitivity common source amplifier MRAM cell, memory array and read/write scheme
JP3808799B2 (en) * 2002-05-15 2006-08-16 株式会社東芝 Magnetic random access memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052302A (en) * 1999-09-27 2000-04-18 Motorola, Inc. Bit-wise conditional write method and system for an MRAM
US6693826B1 (en) * 2001-07-30 2004-02-17 Iowa State University Research Foundation, Inc. Magnetic memory sensing method and apparatus
US20030206433A1 (en) * 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US6704230B1 (en) * 2003-06-12 2004-03-09 International Business Machines Corporation Error detection and correction method and apparatus in a magnetoresistive random access memory
US20060013039A1 (en) * 2004-07-19 2006-01-19 Daniel Braun Read out scheme for several bits in a single MRAM soft layer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FURAYAMA T: "Trends and challenges of large scale embedded memories", CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004. PROCEEDINGS OF THE IEEE 2004 ORLANDO, FL, USA OCT. 3-6, 2004, PISCATAWAY, NJ, USA,IEEE, 3 October 2004 (2004-10-03), pages 449 - 456, XP010742343, ISBN: 0-7803-8495-4 *
JYH-MING WANG ET AL: "NEW EFFICIENT DESIGNS FOR XOR AND XNOR FUNCTIONS ON THE TRANSISTOR LEVEL", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 29, no. 7, 1 July 1994 (1994-07-01), pages 780 - 786, XP000460513, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
US7499313B2 (en) 2009-03-03
US20070279970A1 (en) 2007-12-06
EP2024976A2 (en) 2009-02-18
WO2008021582A2 (en) 2008-02-21

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